JP2000048558A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which data in a desired bit width is generated without increasing an area occupied by an array and without lowering the access of a column. SOLUTION: A memory array is divided into a plurality of memory subblocks MSB's in the row direction and the column direction. A column selection line S10a and a column selection line S10b are arranged in an interblock region AR0 to an interblock region ARm+1 so as to be extened in the column direction. Block decoding circuits DEC's which generate local column selection signals are arranged so as to correspond to the memory subblocks MSB's. A main I/O line pair group MIOG0 to a main I/O line pair group MIOGm are arranged and installed on the memory subblock; MSB's, Respective columns of the memory subblocks MSB's are connected to the corresponding main I/O line pairs according to the local column selection signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a configuration of a memory array capable of easily expanding a data bit width and realizing high-speed data access.

[0002]

2. Description of the Related Art FIG. 52 shows a conventional semiconductor memory device (DRAM: dynamic memory) having a storage capacity of 64 Mbits.
FIG. 2 is a diagram schematically showing an arrangement of an array mat of a random access memory. In FIG. 52, the semiconductor memory device CH includes four memory mats MTa to MTd each having a storage capacity of 16 M bits. Peripheral circuits PHa to PHc are arranged in a central area between these memory mats MTa to MTd. Peripheral circuit PHa includes a circuit that controls an access operation to memory mats MTa to MTd. Peripheral circuits PHb and PHc include a data input / output circuit and an external signal input circuit.
Generate an internal signal for Ha.

[0003] As shown in FIG.
By dividing memory mats MTa to MTd and arranging them, the lengths of word lines arranged corresponding to memory cell rows and bit lines arranged corresponding to memory cell columns are shortened, and high-speed memory A cell selection operation is realized.

FIG. 53 shows a memory mat MT shown in FIG.
It is a figure showing composition of a-MTd. In FIG. 53,
One memory mat MT is shown. As shown in FIG.
The memory mat MT is divided into 16 memory sub-blocks MSB along the row direction by the word line shunt region WS, and is divided into 32 memory sub-blocks MSB by the sense amplifier band SAB along the column direction. A column selection line CSL extending from a column decoder CD arranged on one side of the memory mat MT in the column direction and shared by memory sub-blocks MSB arranged in the column direction is provided. A column select signal from column decoder CD is transmitted onto select line CSL. Here, the word line shunt region is electrically connected to a relatively high-resistance gate electrode layer made of, for example, polysilicon, to which a memory cell is connected, and a lower-resistance conductive layer made of, for example, aluminum on the gate electrode layer. Indicates the area to be connected.
In this word line shunt region WS, by connecting the upper low-resistance conductor and the lower gate electrode layer,
The resistance of the word line is reduced equivalently. Sense amplifier band S
AB includes a sense amplifier circuit arranged corresponding to each column of memory sub-block MSB, and detects, amplifies and latches memory cell data in the corresponding column when activated.

[0005] This memory mat MT is 16 · 32 = 5.
It is divided into 12 memory sub-blocks MSB. The memory sub-block MSB includes 32K memory cells arranged in 256 rows and 128 columns. Memory mat MT
Is divided into a plurality of memory sub-blocks MSB, so that only the memory sub-blocks including the selected memory cell are driven to reduce current consumption, and are connected to bit lines (memory cell columns) in each selected memory sub-block. The number of memory cells is reduced, the bit line capacitance is correspondingly reduced, and the read voltage appearing on the bit lines when a memory cell is selected is increased.

FIG. 54 shows a memory mat MT shown in FIG.
FIG. 3 is a diagram showing a more detailed configuration of FIG. In FIG. 54, two memory sub-blocks M included in memory mat MT
Shown are SBa and MSBb. Two memory sub-blocks MSBa and MS aligned along these row directions
Local I / O line pairs LIOa to LIOd are provided commonly to Bb. These local I / O line pairs LIOa-L
IOd is the memory sub-block MSBa and MSBb
, And another local I / O line pair is arranged in an adjacent memory sub-block (not shown).

Memory sub-blocks MSBa and MSB
b, that is, the word line shunt region WS
In the word line shunt region WS, main I / O line pairs MIOa-MI
Od is placed. These main I / O line pairs MIOa
To MIOd are provided commonly to memory sub-blocks arranged in line in the column direction. A local I / O line pair provided for a memory sub-block selected by a row decoder (not shown) is connected to a main I / O line pair.

A column select signal from a column decode circuit CDK included in column decoder CD is transmitted onto a column select line CSL extending over the memory sub-blocks in the column direction. Column select line CSL
Are commonly provided to memory sub-blocks arranged in line along the column direction, and transmit a column selection signal to these memory sub-blocks. Main I / O line pair MI
Main I / O at the time of activation for each of Oa to MIOd
Main amplifier MAP for amplifying data on line pair
a to MAPd are provided.

In the arrangement shown in FIG. 54, when column select line CSL is selected, memory sub-block MSB
In b, four columns of memory cells are selected, and each column is connected to a local I / O line LIOa to LIOd, respectively, and then connected to a main I / O line pair MIOa to MIOd.

Eight arrangements shown in FIG. 54 are provided along the row direction. In the case of a four-way system in which four sense amplifiers (columns) are selected by one column selection line CSL and connected to a local I / O line pair, eight memory sub-blocks out of sixteen memory sub-blocks are local I
Connected to the main I / O line pair via the / O line pair,
A total of 4.8 = 32 bits of data can be selected simultaneously. In this case, 2K (= 128 · 16) sense amplifiers are provided along the row direction, and memory cell data is latched in each sense amplifier. Therefore, 32-bit data specified by the column address is selected from the 2K-bit data.

As shown in FIG. 52, this memory mat M
Four Ts are provided inside the semiconductor memory device, so that 128-bit word data can be transferred inside the chip. When each mat is used as a bank, 32-bit word data is input / output per bank.

FIG. 55 shows a conventional 256 Mbit DRAM.
It is a figure which shows schematically the arrangement | positioning of the mat of FIG. In FIG. 55, this DRAM includes memory mats MT0 to MT7 arranged in the row direction and memory mats MT0 to MT7.
0 to MT7 and memory mats MT8 to
MT15. In a region between memory mats MT0 to MT7 and memory mats MT8 to MT15, peripheral circuits PH are arranged along the row direction. Peripheral circuit PH includes a data input / output circuit, and an address signal and external control signal input circuit.

Each of the memory mats MT0 to MT15 is
It has a storage capacity of 16 Mbits. Main word driver group MWD is arranged between adjacent memory mats. In a 256 Mbit DRAM, a word line has a hierarchical structure of a main word line and a sub word line in order to drive a word line to a selected state at high speed. A memory cell is connected to the sub-word line, and no memory cell is connected to the main word line. A sub word line driver is arranged between the main word line and the sub word line. The main word line having a small load capacity is driven to the selected state at high speed, and the sub word line provided at the end thereof is driven to the selected state at high speed.

The memory mats MT0 to MT shown in FIG.
Each of T15 is divided into a plurality of memory sub-blocks MSB in the row and column directions, similarly to the memory mats shown in FIGS. 53 and 54, respectively. Since the sub-word line drive circuit is provided, the size of the memory sub-block increases, and the memory sub-block is
54, and has twice the storage capacity of 128 K bits (512 rows and 256 columns) in place of the configuration shown in FIG. Therefore, each of the memory mats MT (MT0 to MT15) is divided into eight memory sub blocks along the row direction. The arrangement of the local I / O line pairs and the global I / O line pairs is the same as the configuration shown in FIG. Therefore, in one mat, a memory cell of 4/4 = 16 bits is selected to input / output data. When the DRAM shown in FIG. 55 has a four-bank configuration, one bank is composed of four memory mats, so that data of a 64-bit word configuration can be input / output per bank.

[0015]

In a conventional semiconductor memory device (DRAM), data is input / output via a main I / O line pair arranged in a word line shunt region or a sub word line driver region. In order to perform high-speed data transfer between the DRAM and a processor provided outside the DRAM, it is desirable that the data bit width be as wide as possible. Many data words can be transferred in one data transfer cycle. However, the conventional DRAM has a problem that the bit width of a data word cannot be sufficiently increased.

Normally, SDRAM (synchronous DRA)
M), 4 banks, RDRAM (Ranbus DRA)
M), 16 banks are provided, and in an SLDRAM (sync link DRAM), 8 banks are provided.
With such a multi-bank configuration, an increase in access time due to an operation of driving another word line (row) to a selected state after driving a selected word line to a non-selected state at the time of page boundary access is eliminated. That is, the plurality of banks are sequentially driven to an active state in an interleaved manner,
At the time of page switching, by accessing another bank, continuous access is performed without increasing access time at the time of page switching. If there are many banks,
Even when a plurality of clock cycles are required for the row selection operation, the banks can be accessed in each clock cycle by sequentially driving the banks to the selected state, and the DRAM can be accessed in accordance with a high-speed clock signal.
Can be operated.

Therefore, in recent years, the number of banks provided in the semiconductor memory device has been increasing. As the number of banks increases, the number of memory cells allocated to one bank decreases, and it becomes difficult to allocate a sufficient bit width to one data. The number of words performed is reduced). For example,
When the DRAM shown in FIG. 55 has a 4-bank configuration, data access of a 64-bit word configuration can be performed for one bank. However, in the case of an 8-bank configuration, only memory cells are selected from two memory mats, so that only data of a 32-bit word configuration per bank can be handled.

In order to realize high-speed data transfer between a processor and a DRAM, a plurality of data are generally prefetched internally. The prefetched data is sequentially transmitted in synchronization with the clock signal.

FIG. 56 schematically shows a structure of a data reading unit of a conventional clock synchronous semiconductor memory device (synchronous DRAM). In FIG. 56, a plurality of data read simultaneously from memory bank BK are latched by latch circuit LK. The latch circuit LK outputs the selection signal φ
The latched data is sequentially applied to the transfer circuit TK according to sel. The transfer circuit TK transfers data provided from the latch circuit LK in synchronization with the clock signal CLK and outputs the data via an output circuit (not shown).

Normally, a path for transferring data from a sense amplifier to a latch circuit LK in a memory bank BK (one or a plurality of memory mats) (data latched by a sense amplifier is transferred via an internal main I / O line pair). The path to the main amplifier) takes the most time. By simultaneously transferring a plurality of data to the latch circuit LK and sequentially selecting and outputting the data in synchronization with the clock signal CLK,
The worst delay in the data transfer from the memory bank BK to the latch circuit LK can be apparently eliminated.
In order to increase the data transfer speed, the latch circuit L
It is desirable that a large number of data be latched and sequentially transferred at K. In particular, in recent clock-synchronous DRAMs, data is input / output by a DDR (double data rate) method, and external data is transferred in synchronization with both rising and falling edges of a clock signal. Done. When data transfer is performed at twice the speed of such a clock signal, for example, two worst delays are provided by providing two latch circuits LK, transferring data to the latch circuits alternately and latching the data, and then sequentially transferring the data. Data transfer is performed at high speed by eliminating the influence of the route.
In such high-speed data transfer, to prefetch a large amount of data, the number of data word bits is limited because the number of main I / O line pairs is constant. Therefore, the number of bits of a data word transferred to the outside in one clock cycle is limited, and high-speed transfer cannot be realized.

Although the design rules have been refined due to the progress of process technology, the chip size tends to increase as the storage capacity increases. In order to reduce the chip size as much as possible and reduce the cost, increase the storage capacity of the memory sub-block by increasing the division unit of the bit lines and word lines, reduce the number of circuits other than memory cells, and Reduction of the occupied area has been performed. Increasing the division unit of the bit line and the word line is equivalent to increasing the storage capacity of the memory sub-block and reducing the area between blocks, ie, the area where the main I / O line pair is arranged. Therefore, even if the size of the memory mat increases, the number of sense amplifiers activated at a time increases, and the number of data bits latched at a time increases, the number of main I / O line pairs increases the memory capacity. The number of data bits that can be transferred outside the array is limited. To solve this,
It is conceivable to increase the layout area of the local I / O line pairs and the main I / O line pairs, that is, the layout area of the sense amplifier band, the sub-word line driver, and the like to increase the number of wirings. However, in this case, the chip size obviously increases due to the increase in the layout area.

Therefore, in the conventional array structure of the semiconductor memory device, a data word having a sufficient bit width cannot be generated, and a problem arises in that high-speed data transfer cannot be realized.

As the storage capacity increases, the size of the memory mat also increases, and the length in the column extending direction also increases. Now, as shown in FIG. 57, in one memory mat, a memory sub-block MSB0 farthest from the column decoder and a memory sub-block MSBn closest to the column decoder are considered. These memory sub-blocks MSB0 and MSBn are arranged aligned in the column direction and share a column selection line CSL for transmitting a column selection signal from a column decoder (not shown). Local I / O line pairs LIO0 and LIOn are provided for memory sub-blocks MSB0 and MSBn, respectively, and main I / O line pair MIO is arranged commonly to these memory sub-blocks MSB0 and MSBn. The main amplifier MAP is connected to the main I / O line pair MIO.
And a write driver WRD.

In a synchronous semiconductor memory device, data read / write is performed by simultaneously giving a read / write command and a column address. At the time of data writing, write driver WRD is activated to transmit write data onto main I / O line pair MIO. When writing data to memory sub-block MSB0, data transmitted by write driver WRD is transmitted to a sense amplifier provided in memory sub-block MSB0. Similarly, when writing data to memory sub-block MSBn, write data from write driver WRD is transferred to a sense amplifier provided in memory sub-block MSBn. There is a signal propagation delay Td due to the wiring capacitance and wiring resistance of this main I / O line pair MIO. When the storage capacity increases and the size of the memory mat in the column direction increases, the length of the main I / O line pair correspondingly increases, and the signal propagation delay Td also increases. Therefore, since the time required for data writing is determined in the worst case, the writing operation cannot be completed unless at least the delay time Td has elapsed since the activation of write driver WRD (actually, Has a sense amplifier and a main I /
Also consider the signal propagation delay between the O line pair). A command designating the next operation mode needs to be given after the completion of the data writing. The same applies to the case where read data is transmitted to the main amplifier MAP at the time of data reading, and the time required for reading is determined by the delay time Td, which makes it impossible to shorten the so-called CAS latency. Occurs. This means that in FIG. 56, the signal propagation time in the transfer path from the memory bank BK to the latch circuit LK becomes longer, and high-speed data reading cannot be performed.

Therefore, an object of the present invention is to provide a semiconductor memory device capable of realizing high-speed data transfer.

Another object of the present invention is to provide a semiconductor memory device capable of greatly increasing the number of data bits that can be simultaneously transferred inside a chip without increasing the chip size.

Still another object of the present invention is to provide a multi-bank semiconductor memory device capable of transferring a data word having an arbitrary bit width at a high speed.

[0028]

According to a first aspect of the present invention, there is provided a semiconductor memory device including a plurality of memory blocks each having a plurality of memory cells arranged in a matrix and arranged in a row and column direction. , A plurality of column selection lines extending in the column direction to extend outside the memory array and between the memory blocks, respectively, and transmitting a column selection signal, and extending in the column direction over the memory block A plurality of internal data lines arranged and grouped corresponding to a column block, and each corresponding to a memory block, each of which selects a column of a corresponding memory block according to a column selection signal on a column selection line. Column selection circuit connected to the internal data line of the corresponding group.

According to a second aspect of the present invention, in the semiconductor memory device, each of the column selection circuits of the first aspect is arranged in a region between memory blocks and an external region of the memory array, and designates a memory block arranged in a row direction. A decoding circuit for generating a column selection signal for a corresponding memory block according to a row block designation signal to be performed and a column selection signal on a corresponding column selection line.

In the semiconductor memory device according to the third aspect, each of the decode circuits according to the second aspect is shared by a column selection circuit provided in a memory block disposed on both sides along a row direction of a corresponding region.

In the semiconductor memory device according to a fourth aspect, each of the column selection circuits according to the first or second aspect is dispersedly arranged on both sides of the corresponding memory block along the column direction.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the first aspect, at least the memory block arranged along the row direction forms a bank, and the column selection circuit outputs a bank designating signal for specifying the bank. Is activated, the column selection operation is activated.

A semiconductor memory device according to a sixth aspect of the present invention is the semiconductor memory device according to the first aspect, further comprising a column selection signal group corresponding to an inter-memory block area and a memory array external area on one side in the column direction of the memory array. And placed
A plurality of column decoding circuits for generating a column selection signal on a corresponding column selection line according to a given column address signal are included.

According to a seventh aspect of the present invention, in the semiconductor memory device, each of the plurality of column decode circuits of the sixth aspect is grouped corresponding to each column block, and is activated according to a column block designating signal for specifying the column block. Then, a given address signal is decoded to generate a column selection signal.

An eighth aspect of the present invention provides the semiconductor memory device, wherein the decoding circuit of the second aspect includes a plurality of decoders provided on both sides of the memory block in the row direction and transmitting column selection signals in mutually opposite directions.

According to a ninth aspect of the present invention, the plurality of decoders of the eighth aspect drive a common column selection line.

According to a tenth aspect of the present invention, in the storage device of the eighth aspect, each of the plurality of memory blocks is divided into a plurality of groups in the row direction, and a plurality of decoders are provided in each of the plurality of groups. It is provided correspondingly and transmits a column selection signal to a corresponding group.

According to a eleventh aspect of the present invention, in the semiconductor memory device, the decoding circuit of the second aspect is arranged for every predetermined number of memory blocks along the column direction in the inter-memory block region and the external region of the memory array. In the region, the arrangement of the block decode circuits differs.

According to a twelfth aspect of the present invention, there is provided the semiconductor memory device according to the first aspect of the present invention, wherein the semiconductor memory device is further provided corresponding to a column block, and provided on an internal data line provided corresponding to a column block corresponding to the activation. And a plurality of read circuits for amplifying the data. Each of the plurality of read circuits includes a plurality of read amplifiers provided corresponding to the internal data lines.

The semiconductor memory device according to the twelfth aspect further includes a read amplifier provided for a group specified by the data group specifying signal in response to a data group specifying signal for specifying a group of internal data lines. A data selection circuit for reading data to the global data bus is further provided.

According to a thirteenth aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, further comprising an internal data provided corresponding to a memory column block and provided corresponding to a column block corresponding to the activation. Includes a plurality of write / read circuits for exchanging data with lines. Each of the plurality of write / read circuits includes a write driver and a read amplifier provided corresponding to each of the internal data lines.

According to a thirteenth aspect of the present invention, the semiconductor memory device further includes a write / read circuit provided for a group specified by the data group specifying signal in accordance with a data group specifying signal for specifying a group of internal data lines. A data selection circuit is provided for activating data transfer with the global data bus.

A semiconductor memory device according to a fourteenth aspect has a plurality of banks each having a plurality of memory cells arranged in a matrix and capable of independently selecting / deselecting a memory cell row. . Each of the multiple banks
It is divided into multiple sub-banks.

The semiconductor memory device of claim 14 further comprises:
A plurality of internal data lines arranged extending in the column direction over the plurality of banks, and a column of memory cells in a sub-bank of the bank designated according to a bank / sub-bank address signal specifying the bank and the sub-bank. And a plurality of write / read circuits provided corresponding to the plurality of internal data lines, respectively, for transmitting and receiving data to and from the corresponding internal data lines when activated. . These multiple writes /
The read circuit is divided into a plurality of groups.

According to a fourteenth aspect of the present invention, the semiconductor memory device further selects a write / read circuit of a designated group from the plurality of write / read circuits according to the group address signal and connects the selected write / read circuit to the global data bus. A data selection circuit is provided.

According to a fifteenth aspect of the present invention, each of the plurality of write / read circuits of the fourteenth aspect includes a latch circuit for latching applied data.

In a semiconductor memory device according to a sixteenth aspect, the sub-bank selection circuit of the fourteenth aspect connects a column of memory cells of a specified sub-bank to an internal data line for a predetermined period in response to a sub-bank specifying signal.

A semiconductor memory device according to a seventeenth aspect is the semiconductor memory device according to the fourteenth aspect, further comprising a write circuit included in the write / read circuit in response to a data write instruction provided together with the data group specifying signal. There is further provided control means for activating and writing data to the subbank specified by the subbank specifying signal via the subbank selection circuit.

The semiconductor memory device according to the eighteenth aspect is the semiconductor memory device according to the fourteenth aspect of the present invention, further comprising, in response to the subbank activation signal, the internal bank connected to the internal data line being returned to an inactive state. A control circuit for stopping precharging of the data line is provided.

According to a nineteenth aspect of the present invention, in the semiconductor memory device according to the third or fourth aspect, the device is further provided corresponding to a column and arranged at least between memory blocks adjacent in the column direction. A plurality of shared sense amplifier groups each having a plurality of sense amplifiers are provided.

By arranging column selection lines in the inter-memory block area and the memory array external area and arranging internal data lines on the memory array, the number of internal data lines can be increased without increasing the array occupation area. Can be increased, and the number of data bits can be increased accordingly. The column selection lines connect the memory cell columns to a large number of internal data lines provided on the memory block, so that the number of column selection lines can be reduced, and an increase in the area of the region between the memory blocks can be suppressed. .

Further, by constituting a plurality of banks and reading data on internal data lines in advance, at the time of data writing / reading, only the write / read circuit provided on the internal data lines is driven. It is not necessary to access the inside of the memory block, and high-speed access can be realized, and high-speed data transfer can be realized.

[0053]

[First Embodiment] FIG. 1 schematically shows a structure of an array portion of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, memory array MRY includes a plurality of memory sub-blocks MSB arranged in a row and a column. The memory sub-blocks MSB arranged in the row direction constitute a row block R # i (i = 0 to n), and the memory sub-blocks MSB arranged in the column direction are column blocks. C♯j (j = 0 to m). Each of the memory sub-blocks MSB has a plurality of memory cells arranged in a matrix.

Areas AR0 and ARn + outside memory array
1 and main column selection lines SGa and SGb for transmitting a column selection signal from a column decoder (not shown) are provided in regions AR1 to ARm between memory blocks. These column selection lines SGa and SGb are arranged extending in the column direction, and are shared by the memory sub-blocks of the corresponding column block.

Local column select lines LSGa and LSGb are provided for each of memory sub-blocks MSB. These local column select lines LSGa and LSGb are arranged extending only in the corresponding memory sub-block arrangement region along the row direction. Local column select lines LSGa and LSGb are connected to an out-of-array area AR0.
And ARn + 1 and the inter-memory block areas AR1 to AR1
It is connected to corresponding main column selection lines SGa and SGb via a decoder DEC provided in ARm.

In each of column blocks C # 0-C # m, main I / O line pair group MIOG0-MIOG extends over memory sub-block MSB and extends in the column direction.
m is provided. A plurality of columns (sense amplifiers) simultaneously selected by local column select lines LSGa and LSGb are connected to a corresponding main I / O line pair group.

The main column selection lines SGa and SGb are connected only to the decoder DEC, and are not connected to an IO gate for selecting a memory cell column. Therefore, since the load capacity is small, the column selection signal can be transmitted to the farthest end of the memory array MRY at high speed.

By arranging the main I / O line pairs extending over the memory sub-blocks, a required number of main I / O line pairs can be arranged without increasing the area occupied by memory array MRY. And the number of data bits can be increased.

FIG. 2 is a diagram schematically showing the configuration of the inter-memory block area AR. FIG. 2 representatively shows an inter-block area AR between two memory sub-blocks MSBa and MSBb. Memory sub-block MSB
In each of a and MSBb, memory cells MC are arranged in a matrix. Word lines WL are provided corresponding to each row of the memory cells, and bit lines BL (and / BL) are provided corresponding to the columns of the memory cells. In the configuration shown in FIG. 2, word line WL is arranged commonly to memory sub-blocks included in a row block. Memory cell M
C is a capacitor MQ for storing information in the form of electric charges, and a capacitor MQ in response to a signal potential on a corresponding word line WL.
Access transistor MT for connecting Q to corresponding bit line BL (or / BL). The gate of access transistor MT is connected to word line WL (usually,
The first polysilicon layer forming the word line WL is a control electrode of the access transistor MT.)

In parallel with the word line WL, a low-resistance conductor line LRL is arranged above the word line WL. This low-resistance conductor wiring LRL is electrically connected to a word line WL via a contact CT in the inter-memory block area AR. Thereby, the resistance of the word line WL is reduced equivalently. This inter-memory block area AR is usually
This is called a word line shunt region. The word line shunt region is a region where the low resistance conductor wiring LRL and the word line WL are electrically connected, and the memory cell MC does not exist. Therefore, main column select lines SGa and SGb and decoder DEC can be arranged with a relatively large margin.

FIG. 3 is a diagram showing another configuration of the area between memory blocks. FIG. 3 representatively shows two memory sub-blocks MSBa and MSBb. Memory sub-blocks MSBa aligned in the row direction
And MSBb, a main word line MWL is arranged in common. This main word line MWL is provided commonly to memory sub-blocks included in the same row block. In each of memory sub blocks MSBa and MSBb, sub word lines SWL0 to SWL3 are arranged corresponding to main word line MWL. One row of memory cells MC in the corresponding memory sub-block is connected to each of these sub-word lines SWL0 to SWL3.

These sub-word lines SWL0-SWL3
Sub word line drivers DR0 to DR3 receiving signals on main word line MWL and group selection signals φ0 to φ3 are provided correspondingly. When the main word line MWL is selected, four sub word lines SWL0 to SWL
WL3 is designated, and these four sub-word lines SWL
One subword line of 0 to SWL3 is selected by group selection signals φ0 to φ3. The sub-word line drivers DR0 to DR3 are connected to the memory sub-block MSBa
And in regions ARa and ARb outside of MSBb. In regions ARa and ARb, main column selection lines are arranged along the column direction. Decoder DEC for connecting main column select line and local column select line
Is arranged at a portion where an area between memory blocks adjacent in the column direction (sense amplifier band area) and an inter-block area AR intersect. In this area, no sub-word line driver is provided, so
A decoder DEC can be arranged.

In the array arrangement shown in FIG. 3, sub word line drivers are provided on both sides of the memory sub block.
A configuration arranged alternately may be used. One sub-word line is arranged corresponding to one main word line MWL in each memory sub-block, and the corresponding sub-word line is driven to a selected state by a sub-word line driver having no decoding function. Configurations may be used.

The inter-memory block regions AR1 to ARm and the out-of-array regions AR0 and ARn + 1 may be any of the word line shunt region shown in FIG. 2 and the sub word line driver arrangement region shown in FIG. In the following description, the area between memory blocks (or the area between blocks)
When it is referred to, both of these areas are indicated.

FIG. 4 is a diagram schematically showing a configuration of a portion related to one memory sub-block. In FIG. 4, sense amplifiers SA are arranged corresponding to bit line pairs BLP of memory sub-block MSB. The sense amplifiers SA are divided into four groups, and adjacent sense amplifiers SA1 to SA4 form one set. One set of sense amplifiers includes sense amplifiers SA1 to SA4 belonging to different groups. Main I / O line pairs MI / O1, ZMI / O1-M corresponding to the sense amplifier set
I / O128 and ZMI / O128 are arranged. Main I / O line pairs MI / Oi and ZMI / Oi transmit mutually complementary data.

In the configuration shown in FIG. 4, 512 sense amplifiers are provided. In order to select a group of sense amplifiers, in the inter-block area ARa, a decode circuit DEC receives a column select signal S2 on the main column select line SG2 and a row block select signal φrb to generate a local column select signal LS2. A circuit 1b and a decode circuit 1d receiving a row block selection signal φrb and a column selection signal S4 on a main column selection line SG4 to generate a local column selection signal LS4 are provided. In the inter-memory block area ARb, the decode circuit DEC receives the column select signal S1 on the main column select line SG1 and the row block select signal φrb as the decode circuit DEC, and the column select signal S3 on the main column select line SG3 and the row. And a decode circuit 1c that receives block select signal φrb and generates local column select signal LS4. Row block selection signal φrb
Is a signal for selecting a row block, and is commonly applied to memory sub-blocks included in one row block.

Each of sense amplifiers SA1 to SA4 conducts in response to local column select signal LS1, and connects I / O select gate N1 connecting corresponding sense amplifier SA1 to a corresponding main I / O line pair. Is turned on in response to a local column selection signal LS2, and turned on in response to a local column selection signal LS3 and an I / O selection gate N2 connecting the corresponding sense amplifier SA2 to the corresponding main I / O line pair. The corresponding sense amplifier SA3 is connected to the corresponding main I
An I / O select gate N3 connected to the / O line pair and an I / O select gate N4 which conducts in response to the local column select signal LS4 and connects the corresponding sense amplifier SA4 to the main I / O line pair are provided. Can be

One of a set of sense amplifiers SA1 to SA4 is selected according to a local column selection signal from decode circuits 1a to 1d, and 128 main I / O line pairs MI / O1, ZMI / O1-MI /
O128 and ZMI / O128. In one column block, 128-bit memory cells can be simultaneously selected and connected to the main I / O line pair. Main I / O line pair MI / O1, ZMI / O1 to MI / O12
8, ZMI / O128 is arranged extending in the column direction,
It is connected to a preamplifier and a write driver provided outside the array.

One memory sub-block is divided into four, and only four main column selection lines are required for one memory sub-block. Lines can be arranged.

In the structure shown in FIG. 4, memory sub-block MSB is divided into four groups, and one group is selected. However, the number of divisions of this one memory sub-block may be appropriately determined according to the number of data bits, and may be divided into eight, sixteen or two.

[Modification] FIG. 5 shows a structure of a modification of the semiconductor memory device according to the first embodiment of the present invention. FIG. 5 shows a configuration of a portion related to two memory sub-blocks MSBa and MSBb. In the configuration shown in FIG. 5, main column selection lines SG1 to SG4
Are provided commonly to two memory sub-blocks. Decode circuit 1e generates local column select signal LS1 according to a column select signal on main column select line SG1 and row block select signal φrb, and decode circuit 1f
Generates a local column selection signal LS2 according to the column selection signal on the main column selection line SG2 and the row block selection signal φrb. Decoding circuit 1g generates a local column selection signal LS3 according to a column selection signal on main column selection line SG3 and a row block selection signal φrb, and decoding circuit 1h generates a main column selection line SG3.
4 generates a local column selection signal LS4 according to a column selection signal and a row block selection signal φrb. These local column select signals LS1 to LS4 are commonly applied to two memory sub-blocks MSBa and MSBb. In FIG. 5, a decode circuit 1i for generating a local column selection signal LS4 for an adjacent memory sub-block (not shown) and a local column selection signal LS
1 is also shown.

In the case of the configuration shown in FIG. 5, decode circuits 1e to 1h need to drive local column select signal lines provided along the row direction for two memory sub-blocks MSBa and MSBb. . However, according to this configuration, the number of decoding circuits can be reduced by half. Also, the number of main column selection lines can be halved. This can suppress an increase in the area occupied by the array.

Incidentally, in the configuration shown in FIG.
The arrangement of the / O line pair group, the sense amplifier and the I / O select gate is the same as the arrangement shown in FIG.

As described above, according to the first embodiment of the present invention, a main I / O line pair is arranged on a memory sub-block, and a main column selection line is arranged in a region between blocks. With this configuration, data having an arbitrary bit width can be generated without increasing the array area.

Since the column selection of the memory sub-block is performed in accordance with the result of decoding the column selection line and the row block selection signal, the main column selection line has an I / O
The selection gate is not connected, the load capacity is reduced, and the main column selection line can be driven to the selected state at high speed.

[Second Embodiment] FIG. 6 schematically shows a structure of a main part of a semiconductor memory device according to a second embodiment of the present invention. FIG. 6 shows a configuration of a portion related to one memory sub-block. In the configuration shown in FIG. 6, the sense amplifier group includes memory sub-block MSB
Are alternately arranged on both sides in the column direction. That is, sense amplifiers SA1 and SA3 are arranged below memory sub-block MSB in the column direction, and sense amplifiers SA2 and SA4 are arranged in memory sub-block MSB.
B is arranged on the upper side in the column direction. One set of sense amplifiers includes sense amplifiers SA1 to SA4. Main I / O line pair M corresponding to each set of sense amplifiers
I / O0, ZMI / O0 to MI / O128, 0MI / O
128 are provided.

In response to the alternate arrangement of the sense amplifiers,
Decoding circuits 1a to 1d are also arranged in a distributed manner. In other words, in the inter-block region ARa, the decode circuit 1b which receives the row block selection signal φrb and the column selection signal on the main column selection line SG2 and generates the local column selection signal LS2 is connected to the upper side in the column direction of the memory sub-block MSB. A decode circuit receiving local row select signal φrb and column select signal S3 on main column select line SG3 to generate local column select signal LS3 below memory sub block MSB in the column direction. 1c is provided.

In the inter-block area ARb, on the upper side in the column direction of the memory sub-block MSB,
A decode circuit 1d is provided which receives column select signal S4 on main column select line SG4 and row block select signal φrb to generate local column select signal LS4, and provides a row at the lower side in the column direction of memory sub-block MSB. A decode circuit 1a is provided which receives block select signal φrb and column select signal S1 on main column select line SG1 to generate local column select signal LS1.

By arranging decode circuits 1a to 1d in a distributed manner, one memory sub-block MSB
The pitch of the decoding circuit in the column direction is the size of one memory sub-block MSB in the column direction, and the decoding circuit can be provided with room between the inter-block regions ARa and ARa.
b.

FIG. 7 is a diagram showing a configuration of a portion related to memory sub-blocks arranged in two rows and two columns. In FIG. 7, memory sub-block MSBa has sense amplifier group SAGal, I / O selection gate group (N1) NG1a, and I / O selection gate group (N3) NG3a on the lower side in the column direction. On the upper side in the column direction, the sense amplifier group SAGau, the I / O selection gate group (N2) NG2a, and the I / O selection gate group (N4)
NG4a. I / O select gate group NG1a to NG4
Decoding circuits 1a to 1d are provided corresponding to the respective "a".

For memory sub-block MSBb adjacent to memory sub-block MSBa in the column direction,
The sense amplifier group SAGb is provided below the column direction.
1, I / O select gate group (N1) NG1b, and I / O
An O select gate group (N3) NG3b is provided, and the sense amplifier groups SAGbu, I /
An O select gate group (N2) NG2b and an I / O select gate group (N4) NG4b are provided.

Memory sub-block MSBc aligned with memory sub-block MSBa along the column direction has sense amplifier groups SAGc, I / O
Select gate group (N1) NG1c and I / O select gate group (N3) NG3c are provided. Memory sub-block MSBd aligned with memory sub-block MSBc along the row direction has sense amplifier group SAGd and I / O selection gate group (N
1) NG1d and I / O select gate group (N3) NG
3d is provided. These memory sub-blocks MSBb
To MSBd, the I / O select gate group N
Decoding circuit 1a corresponding to each of G1b to NG4d
To 1d.

In inter-block region AR, decode circuits 1a and 1d are alternately arranged in the column direction, and decode circuits 1c and 1b are alternately arranged in the column direction. A sense amplifier group and an I / O select gate group are provided in a region between memory sub blocks aligned in the column direction (hereinafter, referred to as a sense amplifier band region).

A decode circuit is provided corresponding to the I / O select gate group. The length of the I / O select gate group in the column direction is determined by the pitch condition of the decode circuit. Therefore, as shown in FIG. 7, by alternately arranging the decode circuits in the column direction and distributing them on both sides of the memory sub-block,
The pitch of the decoding circuit can be made sufficiently large.
Particularly, in memory sub-blocks MSBc and MSBd, a decode circuit is provided between one I / O select gate group. However, in the sense amplifier band region, the decoding circuit has a sufficient margin compared to the case where a total of four decoding circuits are arranged two by two for two memory sub-blocks arranged in the column direction. Can be arranged.

As a result, it is possible to prevent the area occupied by the sense amplifier band region from increasing, and to prevent the array area from increasing.

As described above, according to the second embodiment of the present invention, since the decode circuits for generating the column select signals are dispersedly arranged in the memory sub-block, the pitch condition of the decode circuits is relaxed. Thus, the decoding circuit can be arranged with a margin. In particular, when the number of divisions of the memory sub-block increases, the effect of relaxing the pitch condition becomes more remarkable.

In the structure shown in FIGS. 7 and 6, the decode circuit generates only a local column select signal for one memory sub-block. However, this decoding circuit can obtain the same effect even in a configuration shared by two memory sub-blocks adjacent in the row direction.

FIG. 8 is a diagram schematically showing an arrangement of decode circuits for memory block MSB according to a modification of the second embodiment of the present invention. In the arrangement shown in FIG. 8, sense amplifiers SA1-SA4 are arranged in a so-called alternating arrangement type shared sense amplifier configuration. That is, sense amplifiers SA2 and SA4 are connected to memory block MSB and memory block MSB in the column direction.
, And the sense amplifiers SA1 and SA3 are shared by the memory block MSB and the lower adjacent memory block in the column direction.

I provided for sense amplifier SA1
/ O select gate N1 receives an output signal of decode circuit 1a. The decoding circuit 1a includes an inter-block area ARb
And receives row block select signal φrb0 and a column select signal on main column select line SG1.

I provided for sense amplifier SA3
/ O select gate N3 receives an output signal of decode circuit 1c. This decoding circuit 1c includes an inter-block area AR
a, and receives row block selection signal φrb0 and column selection signal S3 on main column selection line SG3. I / O select gate N2 provided for sense amplifier SA2 receives an output signal of decode circuit 1b.
Decode circuit 1b is arranged above inter-block region ARa, and receives row block select signal φrb1 and column select signal S2 on main column select line SG2.

I provided for sense amplifier SA4
/ O select gate N4 receives an output signal of decode circuit 1d. Decoding circuit 1d is arranged above inter-block region ARb, and receives row block selection signal φrb1 and column selection signal S4 on main column selection line SG4.

Main column select lines SG2 and SG3 are arranged extending in the column direction in inter-block region ARa, and main column select lines SG1 and SG4 are arranged extending in the column direction in inter-block region ARb.

Row block select signal φrb0 is activated when a memory block MSB or a memory block adjacent to the lower side in the column direction is selected, and row block select signal φrb1 is set to the state of memory block MSB or the upper adjacent memory block. Activated when selected.
Since the sense amplifiers SA1 to SA4 are shared between adjacent memory blocks in the column direction, the area occupied by the sense amplifiers is reduced.

FIG. 9 shows an array arrangement according to a modification of the second embodiment of the present invention. In FIG. 9, memory sub blocks MSBa-MSBc are arranged aligned in the column direction, and memory sub blocks MSBd-MSBf are also arranged aligned in the column direction. Sense amplifier group SA
Gab and I / O gate group NG1a and NG3a
Are arranged between memory sub blocks MSBa and MSBb, and sense amplifier group SAGac and I / O gate groups NG2a and NG4b are connected to memory sub block MSB.
It is located between Bb and MSBc. Memory sub-block MSBa also has an I / O on the lower side in the column direction.
Coupled to sense amplifier group SAGaa via O gate groups NG2a and NG4a.

Decoding circuits 1ba, 1ca and 1bb
Is the I / O gate group NG2 in the inter-block region ARa.
a, NG3a and NG2b, and in the inter-block area ARb, the decoding circuit 1
da, 1aa, and 1db are arranged corresponding to I / O gate groups NG4a, NG1a, and NG4b, respectively.

Sense amplifier group SAGbb and I / O
Gate groups NG3b and NG1b are arranged between memory sub-blocks MSBd and MSBe, and sense amplifier group SAGbc and I / O gate groups NG2d and N
G4d is arranged between memory sub-blocks MSBd and MSBe. For memory sub-block MSBb, sense amplifier group SAGba and I / O gate groups NG2c and N
G4c is provided.

In inter-block region ARb, decode circuits 1bc, 1cb and 1bd are arranged corresponding to I / O gate groups NG2c, NG3b and NG2d, respectively. In inter-block region ARc, decode circuits 1dc, 1ab and 1dd are provided. Is I / O gate group NG
4c, NG1b, and NG4d.

Decode circuits 1ba, 1da, 1bc and 1dc are activated when row block select signal φrbA is activated to select memory sub-blocks MSBa and MSBb or to select a lower adjacent memory sub-block. . Decoding circuits 1ca, 1aa, 1cb
And 1ab are activated when row block select signal φrbB is activated to select memory sub-blocks MSBa and MSBd or memory sub-blocks MSBb and MSBe. Decoding circuits 1bb, 1db,
1bd and 1dd are supplied to memory sub-blocks MSBb and MSB when row block select signal φrbC is activated.
e or activated when selecting memory sub-blocks MSBc and MSBf.

I / O gate groups NG1a and NG1b include I / O select gate N1, and I / O gate group NG2
a, NG2b, NG2c and NG2d include an I / O select gate N2, and I / O gate groups NG3a and NG
3b includes an I / O selection gate N3. I / O gate groups NG4a, NG4b, NG4c and NG4d
Includes O select gate N4.

In the arrangement shown in FIG. 9, the sense amplifier is shared by adjacent memory blocks, and the area occupied by the memory array is reduced.

Further, in the arrangement shown in FIG.
When memory sub blocks MSBb and MSBe include a selected word line, row block select signals φrbB and φrbC are activated, and decode circuits 1ca, 1aa,
1cb, 1ab, 1bb, 1db, 1bd and 1dd
Is activated. Sense amplifier group SAGab, SAGa
Data latched by c, SAGbb and SAGbc are selected and read.

Memory sub-blocks MSBa and MSB
When d is selected, the row block selection signal φrbA
And φrbB are activated, and decode circuits 1ba, 1ba,
da, 1bc, 1dc, 1ca, 1aa, 1cb and 1ab are activated to perform the decoding operation. In this case, the sense amplifier groups SAGaa, SAGba, SAG
Data latched by ba, SAGab and SAGbb are selected and read.

FIG. 10 is a diagram showing the arrangement shown in FIG. 9 in more detail. FIG. 10 representatively shows memory sub-blocks MSBa and MSBb, but a similar configuration is provided between other memory sub-blocks.

In FIG. 10, a bit line isolation gate group BILGa including a bit line isolation gate is replaced with an I / O gate group N
G3a and the memory sub-block MSBa,
Bit line isolation gate group BILGb is arranged between memory sub-block MSBb and sense amplifier group SAGab. Bit line isolation gates included in bit line isolation gate group BILGa are provided for every other bit line pair in memory sub-block MSBa, and bit line isolation gates in bit line isolation gate group BILGb are connected to memory sub-block MSBb. Are arranged on every other bit line pair. As a result, an alternate arrangement type shared sense amplifier is realized. Bit line isolation gate groups BILGa and BILG
b includes a sense amplifier group S
It is arranged corresponding to each of the sense amplifiers included in AGab.

Bit line isolation gate group BILGc is arranged between sense amplifier group SAGac and memory sub-block MSBb, provided corresponding to every other bit line pair of memory sub-block MSBb, and provided with sense amplifier group SAGac. And bit line isolation gates provided corresponding to the sense amplifiers included in. Bit line isolation gate group BILGd is arranged between I / O gate group NG4b and adjacent memory sub-block MSBc (not shown in FIG. 10) and corresponds to every other bit line pair of memory sub-block MSBc. And a bit line isolation gate arranged corresponding to the sense amplifier included in sense amplifier group SAGac.

In the standby state, bit line isolation control signals φbiga, φbigb, φbigc and φbit
bigd is kept inactive, bit line isolation gate group BILGa-BILGb is kept conductive, and memory sub-block MSBb is connected to sense amplifier group SA.
Gac and SAGab, and memory sub-block MSBa is coupled to sense amplifier group SAGab and a sense amplifier group (not shown).

In an active cycle in which memory cell selection is performed, for example, memory sub-block MSBb
Is selected, the bit line isolation control signal φbig
b and φbigc are kept inactive, while bit line isolation control signals φbiga and φbigd are activated. Accordingly, bit line isolation gate group BILG
a and BILGb are turned off, and memory sub-block MSBa is connected to sense amplifier groups SAGab and IAGab.
/ O gate groups NG1a and NG3a are separated from each other, and memory sub-block MSBc (not shown) includes sense amplifier group SAGac and I / O gate groups NG2b and N
Disconnected from G4b. Memory sub-block MSBb
Are coupled to sense amplifier groups SAGac and SAGab.

Sense amplifier groups SAGab and SAGa
When activated, c detects, amplifies, and latches data in the selected memory cell of the memory sub-block MSBb. Next, a decode circuit performs a decode operation in response to row block select signals φrbB and φrbC and a column select signal, and I / O gate groups NG1a, NG3a, NG2b and NG4b are selectively turned on according to the output signals of the decode circuit. And sense amplifier groups SAGab and SA
Gac is selected and the main I /
Coupled to the O line pair. Therefore, the data of the selected memory cell can be accurately read without adversely affecting the unselected adjacent memory sub-block.

FIG. 11 shows an arrangement for sense amplifiers SAj shared by memory sub-blocks MSB1 and MSB2. In FIG. 11, the sense amplifier S
Aj is coupled to bit line pair BLP1 included in memory sub-block MSB1 via bit line isolation gate BIG1, and bit line pair BLP2 included in memory sub-block MSB2 via bit line isolation gate BIG2.
Is combined with Bit line isolation gates BIG1 and BI
G2 has a bit line isolation control signal φb
ig1 and φbig2.

Sense amplifier SAj further receives I / O lines MI / O and ZMI / via I / O select gate Nj.
It is coupled to main I / O line pair MIO including O. This I
/ O selection gate Nj is connected to row block selection signal φrb12.
And conduct in response to the logical product of column select signal Sj. Row block selection signal φrb12 is applied to memory sub-block M
Activated when one of SB1 and MSB2 is selected.

When memory sub-block MSB1 is selected, bit line isolation control signal φbig2 is activated and bit line isolation gate BIG2 is rendered non-conductive.
On the other hand, bit line isolation gate BIG1 maintains a conductive state. Therefore, sense amplifier SAj is connected to bit line pair B
LP1 and disconnected from bit line pair BLP2. Signal φrb12 · S provided from decode circuit
j is activated, the I / O select gate Nj is turned on, and the data latched by the sense amplifier SAj is read out to the main I / O line pair MIO.

FIG. 12 shows a structure of a control circuit for controlling connection between the memory sub-block and the sense amplifier group shown in FIG. In FIG. 12, the control circuit inverts row block designating signal φrb2 designating a row block including memory sub-block MSB2 to generate bit line isolation control signal φbig1.
G1 and an inverter VG that inverts a row block designating signal φrb1 designating a row block including memory sub-block MSB1 to generate bit line isolation control signal φbig2.
2 and an OR circuit OG receiving row block designating signals φrb1 and φrb2 to generate row block designating signal φrb12. The decode circuit is activated by a row block designating signal φrb12 from OR circuit OG, and selects an I / O line according to a column select signal.

In the arrangement shown in FIG. 12, when row block designating signal φrb1 is activated (H level),
Bit line isolation control signal φbig2 is activated, and memory sub-block MSB2 is disconnected from sense amplifier SAj. Row block designating signal φrb12 is also activated to activate the decode circuit and select an I / O line according to the column select signal. Since row block designating signal φrb2 is held in an inactive state, bit line isolation control signal φbig1 holds an inactive state and continuously couples bit line pair BLP1 to sense amplifier SAj. When memory sub block MSB2 is selected, row block designating signal φrb2 is activated, and row block designating signal φrb12 and bit line isolation control signal φbig1 are activated.
Is activated, while bit line isolation control signal φbig 2
Are kept inactive.

Memory sub-blocks MSB1 and MSB
2 is a memory sub-block MSBc-MSB shown in FIG.
The representative memory sub-block f is representatively shown. Therefore, even in the configuration in which the shared sense amplifiers are alternately arranged, the area occupied by the array can be reduced by distributing the decode circuits.

[Third Embodiment] FIG. 13 schematically shows a structure of a main portion of a semiconductor memory device according to a third embodiment of the present invention. FIG. 13 representatively shows memory sub blocks MSBaa to MSBac and MSBba to MSBbc arranged in two rows and three columns. In a region between memory sub-blocks, main column select line SG (multiple bits) is arranged to extend in the column direction. A decoder receiving a row block selection signal and a column selection signal on a column selection line is provided commonly to two memory sub-blocks.

A decode circuit DECa0 is provided for memory sub-block MSBaa, and a decode circuit DECa1 is provided for memory sub-blocks MSBab and MSBac. Memory sub-block MSBb
a and the MSBbb, a decoding circuit DECb0
Is provided. Decode circuits DE for memory sub-block MSBbc and a memory sub-block (not shown)
Cb1 is provided. Local column select signal LSaa output from decode circuit DECa0 is applied to memory sub-block MSBaa and a memory sub-block (not shown). The local column selection signal LSab output from the decode circuit DECa1 is the memory sub-block MSBa
b and MSBac. Decode circuit DEC
Local column select signal LSba output from b0 is applied to memory sub-blocks MSBba and MSBbb. The local column selection signal LSbb output from the decode circuit DECb1 is output from the memory sub-block MSBac
And a memory sub-block (not shown).

Decode circuits DECa0, DECa1, D
ECb0 and DECb1 each generate a column select signal of a plurality of bits. In the column extending direction, a decode circuit is provided for every two memory sub-blocks. Row block selection signals φrba and φrbb select memory sub-blocks of the corresponding row block, respectively. By arranging the decoding circuits in common for the two memory sub-blocks, the number of decoding circuits can be reduced, and the area occupied by the decoding circuits can be reduced. By arranging the decode circuits in every other sense amplifier band area and every other block area, the layout pitch of the decode circuits in the row direction and the column direction can be relaxed (in the row direction and the column direction, The decoders of the decoding circuit can be distributed).

[First Modification] FIG. 14 schematically shows a structure of a first modification of the third embodiment of the present invention. FIG.
4 representatively shows three memory sub-blocks MSBa to MSBb arranged in a row. In the inter-block region ARa, the row block selection signal φr
b, a decoder 1ba for receiving the column selection signal on the main column selection line SG2 to generate a local column selection signal LS2 for the memory sub-block, and receiving a row block selection signal φrb and a column selection signal on the main column selection line SG3. Decoder 1ca for generating local column select signal LS3 to apply to memory sub-block MSBa and a memory sub-block (not shown).

In inter-block region ARb, a decoder 1aa receiving a column select signal on main column select line SG1 and a row block select signal φrb to generate local column select signal LS1 for memory sub-blocks MSBa and MSBb, and a row block Decoder 1d receiving selection signal φrb and a column selection signal on main column selection line SG4 to generate local column selection signal LS4 for memory sub-blocks MSBa and MSBb.
a is provided.

In inter-block region ARc, a decoder 1bb for receiving a column select signal on main column select line SG2 and a row block select signal φrb to generate local column select signal LS2 for memory sub-blocks MSBb and MSBc, Block selection signal φrb
And a column selection signal on main column selection line SG3 to generate a local column selection signal LS3 for memory sub-blocks MSBb and MSBc.
cb is provided. Local column select signals LS1 and LS4 from a decoder (not shown) are applied to memory sub-block MSBc.

As shown in FIG. 14, by selecting different memory sub-blocks in accordance with a set of local column selection signals, inter-memory block area AR
The number of decoders arranged in (ARa to ARc) can be reduced, the pitch condition of the decoder can be relaxed, and the decoder can be easily arranged.

When row block select signal φrb is driven to the selected state, a column select operation is performed in memory sub blocks MSBa to MSBc. Therefore, the combination of memory sub blocks to which the local column select signal output from the decoder is transmitted is different. Also in this case, a set of sense amplifiers specified in each memory sub-block is selected, and connection to the main I / O line pair is performed accurately.

[Modification 2] FIG. 15 schematically shows a structure of a modification 2 of the embodiment 3 of the invention. FIG.
0, the memory sub-blocks MSBa to MSBc
The decoders 1ba, 1da and 1bb are arranged on the upper side in the column direction. Excluding this distributed arrangement, FIG.
The arrangement shown in FIG. 5 is the same as the arrangement shown in FIG. 14, and corresponding parts are denoted by the same reference numerals.

In the arrangement shown in FIG. 15, decoders are dispersedly arranged in both the upper and lower regions in the column direction of the memory sub-block. Therefore, the pitch condition of the decoder can be further relaxed, and the decoder can be arranged with a margin. This can suppress an increase in the size of the sense amplifier band region along the column direction, and can suppress an increase in the array area.

Needless to say, the memory sub-block may be divided into two, eight or sixteen divisions instead of being divided into four. The number of decoders also changes according to the number of divisions. Even if the number of decoders increases, the arrangement shown in FIG. 14 or 15 allows the decoders to be arranged with a sufficient margin.

[Modification 3] FIG. 16 schematically shows an arrangement of a decoding circuit according to a modification 3 of the embodiment 3 of the invention. In FIG. 16, the memory sub-block M
SBa-MSBc are arranged in the row direction, and memory sub-blocks MSBd-MSBf are arranged in the row direction. Memory sub-blocks MSBa and MSBd
Between the sense amplifiers SA
Gad is arranged, and a sense amplifier group SAGbe is arranged between memory sub-blocks MSBb and MSBe so as to be shared between them.
A sense amplifier group SAGcf is arranged between and MSBf so as to be shared by them. That is, the sense amplifier groups SAGab, SAGbe and SAGcf have an alternately arranged shared sense amplifier configuration as shown in FIGS.

Inter-block areas ARa, ARb and AR
c, the memory sub-blocks MSBa, M
A decoding circuit 1 is provided above the SBb and MSBc in the column direction.
ba, 1da and 1bb are arranged. When selected, decode circuit 1ba generates local column select signal LS2 for memory sub-block MSBa and a memory sub-block (not shown) adjacent in the row and column directions. When selected, the decode circuit 1da activates the memory sub-block MS
Local column select signal L for Ba, MSBb and memory sub-blocks adjacent thereto in the column direction.
Generate S4. When selected, decode circuit 1bb generates a local column select signal LS2 for memory sub-blocks MSBb and MSBc and a memory sub-block (not shown) adjacent thereto in the column direction.

Inter-block areas ARa, ARb and AR
c, the memory sub-blocks MSBa-M
Decoding circuits 1ca, 1aa and 1cb are arranged between SBc and memory sub-blocks MSBd-MSBf. Decoding circuit 1ca provides local column select signal L for memory sub-blocks MSBa and MSBd at the time of selection and memory sub-blocks adjacent in the row direction.
Generate S3. When selected, decode circuit 1aa generates a local column select signal LS1 for memory sub-blocks MSBa, MSBd, MSBb, and MSBe. When selected, decode circuit 1cb generates local column select signal LS3 for memory sub-blocks MSBb, MSBc, MSBe and MSBf. The sense amplifiers included in sense amplifier groups SAGab, SAGbe and SAGcf are provided with decode circuits 1ca, 1ca,
aa and 1cb.

Further, memory sub-blocks MSBd, M
For SBe and MSBf, the inter-block area AR
a, ARb and ARc are provided with decode circuits 1bb, 1db and 1bc, respectively. Decoder circuit 1bb generates local column select signal LS2 for memory sub-block MSBd and a memory sub-block adjacent thereto in the row direction. When selected, the decode circuit 1db operates at the memory sub-blocks MSBd and MSBd.
A local column selection signal LS4 for Be is generated,
When the decode circuit 1bc is selected, the memory sub-block M
A local column select signal LS2 for SBe and MSBf is generated. Decoding circuits 1bb, 1db and 1bc provide memory sub-blocks MSBd-MSBf
A sense amplifier is selected from a sense amplifier group shared by memory sub-blocks adjacent in the column direction.

When a row block including memory sub-blocks MSBa-MSBc is selected, decode circuit 1
ba, 1da, 1bb, 1ca, 1aa and 1cb are activated. Memory sub-block MSBb-MSBf
Are selected, decode circuits 1ca, 1aa, 1cb, 1bb, 1db and 1bc
Is activated.

In the structure shown in FIG. 16 as well, sense amplifiers are shared by memory sub-blocks adjacent in the column direction, and the area occupied by the sense amplifier band can be reduced.

As described above, according to the third embodiment of the present invention, the decoder for generating the local column select signal is shared by the adjacent memory sub-blocks. As a result, the decoder included in the decoding circuit can be arranged with a margin.

[Fourth Embodiment] FIG. 17 schematically shows an entire configuration of a semiconductor memory device according to a fourth embodiment of the present invention. Referring to FIG. 17, the semiconductor memory device includes a plurality of banks B # 0 each including a plurality of row blocks.
~ B♯3. Row decoder / driver 5 and column decoder 6 are provided commonly to banks B # 0-B # 3. Banks B # 0-B # 3 can each independently drive a word line to a selected / non-selected state. Main column select lines from column decoder 6 are arranged extending in the column direction, and are provided in banks B # 0-B # 3.
Are provided in common to Also, the main I / O line pair MIO
Also extends in the column direction, and these banks B # 0
~ B # 3. Therefore, when a plurality of banks are driven to the selected state, the bank is selected,
It is necessary to perform a column selecting operation on a row block included in the bank.

FIG. 18A schematically shows a structure of a row block selection signal generating portion. In FIG. 18A, a row block selection signal generating section decodes an externally applied bank address BA to output bank designation signal φb
a, a block decoder 11 that decodes an externally applied block address BCA to generate a block specifying signal φbb, a bank specifying signal φba from the bank decoder 10, and a block specifying signal from the block decoder 11. decode circuit 1 generating row block select signal φrb in accordance with φbb
2 inclusive. This decode circuit 12 is formed of, for example, an AND circuit.

FIG. 18 (B) is a diagram showing the address application mode shown in FIG. 18 (A). This semiconductor storage device
As shown in FIG. 18B, in synchronization with clock signal CLK, an externally applied signal is taken in to execute an internal operation. At the rising edge of clock signal CLK, externally applied command extCM is set to a predetermined state, and a column access command (command for designating data read or write) is applied. At this time, the bank address BA and the block address BC
A and a column selection address YA are provided.

Addresses BA, BCA and YA are taken in at the rising edge of clock signal CLK.
Bank address BA is applied to bank decoder 10 shown in FIG. 18A, and block address BCA is
8 (A). Y
Address YA is applied to column decoder 6 shown in FIG. Therefore, even when the memory array is divided into a plurality of banks and each bank includes a plurality of row blocks, the row block in the activated bank can be provided by simultaneously providing the bank and the block address at the time of column access. You can choose.
A column is specified by a block address BCA and a column selection address.

Although not specifically described in the first to third embodiments, the first to third embodiments do not have a bank configuration and have an ordinary one.
In the case of the bank configuration, since a row block including a selected word line is accessed, the row block selection signal may be applied together with a row address. A row block selection signal already activated before column selection is applied to the selected row block, and a high-speed column selection operation is performed according to a column selection signal driven to an active selection state when a column is selected. Can be.

In the first to third embodiments, the row block selection signal may also be generated from the column address. That is, the column address may include an address specifying a row block and an address specifying a column. Further, a block address may be given at the time of row and column access.

As described above, according to the fourth embodiment of the present invention, when a bank includes a plurality of row blocks in a semiconductor memory device having a plurality of banks, row block selection is performed based on the bank address and the block address. Since the signals are generated, only the row blocks that are exactly required can be connected to the main I / O line pair.

When one bank is composed of one row block, it is not necessary to generate a row block selection signal according to the bank designation signal and the block designation signal. It is sufficient to simply generate the row block selection signal according to the bank designation signal provided together with the column access command.

[Modification] FIG. 19 shows a bank configuration of a modification of the fourth embodiment of the present invention. In FIG. 19, bank B # includes a plurality of row blocks # 1- # n each including a plurality of word lines. In the memory array, a plurality of banks B # shown in FIG. 19 are arranged in the column direction.

Latch L corresponding to row block # 1- # n
H1-LHn and gate circuits GTT1-GTTn are provided. Latches LH1-LHn are connected to bank decoder B
Latches row block designating signals φbrf1-φbrfn (φrf) from row block decoder RBDEC in response to row bank selection signal φbar from ADER. Row block decoder RBDEC decodes block address signal BKAD when an active command designating row access is applied. Bank decoder BADER is activated in response to a row access instruction signal RACC activated when an active command is applied, and decodes bank address signal BA.

Gate circuits GTT1-GTTn respectively output signal φ of corresponding latch LH (LH1-LHn).
brl (φbrl1-φbrln) and bank decoder B
Receiving bank instruction signal φbac from ADEC, it generates a row block selection signal φbr (φbr1-φbrn) for the corresponding row block # (# 1- # n). Row block # may have a shared sense amplifier configuration, and a sense amplifier may be provided corresponding to each row block.

Bank decoder BADEC is activated in response to column access designating signal CACC, and decodes bank address signal BA to generate bank designating signal φbac. Column access instruction signal CACC is activated when a write / read command (access command) for instructing data writing or reading is applied. Next, the operation of the configuration shown in FIG. 19 will be described with reference to the timing chart shown in FIG.

When an external command expCM is set to a predetermined state and applied as an active command at the rising edge of the clock signal, bank address signal BA, row block address signal BKAD and row address Signal R
Address signal AD including A is taken in, row block decoder RBDEC and bank decoder BADER are activated, and decode these address signals BKAD and RA. In response, row block instruction signal φbrf for the addressed row block is activated. Latches LH1-LHn are respectively connected to bank decoder BA
In response to activation of bank instruction signal φbar from DER, row block instruction signals φbrf1-φbrfn are taken in and latched. When bank instructing signal φbar is deactivated, latches LH1-LHn enter the latched state.
Even if an active command for another bank is given,
Since bank designating signal φbar for bank B # is inactive, latches LH1-LHn are held in the latched state, and the latch latches the row block designating signal in another bank.

When a read or write command is applied and column access is instructed, bank address signal BA and address signal AD are taken in. The row block is specified by the row system block address signal BKAD,
In this column access instruction cycle, no block address signal for specifying a row block is supplied. Bank decoder BADEC is activated in response to the column access instruction to generate (activate) bank instruction signal φbac. Accordingly, gate circuits GTT1-GTT
n is activated and row block instruction signal φb is latched in accordance with the row block instruction signal latched by latches LH1-LHn.
r (φbr1−φbrn) is generated, and a row block in the bank B # is specified. A column decoder (not shown) decodes the column address signal CA and generates a column selection signal on a main column selection line. Thereby, a column in the memory sub-block is selected in the specified row block. Even if a row block is specified by a row-related address signal given at the same time as the active command, by latching the row block instruction signal by the latch circuit,
A column selecting operation can be accurately performed in a column access cycle.

FIG. 21 shows an example of the configuration of latch LH shown in FIG. In FIG. 21, the latch LH
Transfer buffer TXF, which conducts in response to bank designating signal φbar to pass output signal φbrf from row block decoder, and buffers a signal applied via transfer gate TXF to latch row block designating signal φb.
rl generating two stages of cascaded inverters VG3
And VG4, and an inverter VG5 forming an inverter latch circuit with the inverter VG3.

In the structure shown in FIG. 21, when bank designating signal .phi.bar is activated to attain an H level, latch LH takes in row block designating signal .phi.brf and sets bank designating signal .phi.bar to an inactive state of L level. Then, a latch state is set. Latch LH receives a row block instruction signal from a row block decoder when a corresponding bank is designated, so that a state in which a plurality of row blocks are designated simultaneously in one bank is prevented. When bank instructing signal φbar is activated, bank instructing signal φbac is inactive and gate circuits GTT1-GTTn are inactive.

FIG. 22 shows a row and column access designating signal R
Command decoder CM for generating ACC and CACC
It is a figure showing DEC. This command decoder CMDE
C decodes internal command CM (generated from external command expCM) given at the rising edge of clock signal CLK. When command CM is an active command, row access instruction signal RACC is activated, and when command CM is a read or write command, column access instruction signal CACC is activated.

In the structure shown in FIG. 19, bank decoders BADER and BADEC may be shared by one bank decoder. In this case, a selector for distributing bank designating signals φbar and φbac is provided at the output of the common bank decoder.

[Fifth Embodiment] FIG. 23 schematically shows an entire configuration of a semiconductor memory device according to a fifth embodiment of the invention. In FIG. 23, this semiconductor memory device includes a plurality of memory sub-blocks MS arranged in a row and a column in the same manner as in the first to fourth embodiments.
B. Column block C of memory sub-block MSB
0, C # 1, C # 2, and C # 3, respectively, corresponding to main I / O line pair groups MIOGa and MIOGb,
MIOGc and MIOGd are provided. These main I / O line pair groups MIOGa to MIOGd are arranged extending in the column direction over memory sub-blocks MSB included in corresponding column blocks C # 0 to C # 3.

In each of the inter-block regions ARa to ARe, main column selection lines SG are arranged extending in the column direction. These main column selection lines SG are provided for each column block. Therefore, a local column selection signal is applied to each of memory sub-blocks MSB in accordance with a signal on a main column selection line in an inter-block region provided on both sides in the row direction.

A row decoder / driver 5 for driving main word line MWL (or word line WL) to a selected state is provided on one side of the memory array. The row selection line commonly arranged in the row block is the main word line MW
Whether it is L or word line WL is determined according to the array configuration of the semiconductor memory device.

For each of column blocks C # 0-C # 3, corresponding main I / O line pair group MIOGa-MIOG
main amplifier groups 8a to 8d for amplifying the data on d.
Is arranged. Column decode circuits 6a to 6h are arranged corresponding to inter-block regions ARa to ARe so as to sandwich these main amplifier groups 8a to 8d. Main column select line SG transmits a main column select signal to a decode circuit provided in the vicinity of each memory sub-block. In this memory sub-block MSB,
Only decoding operations such as 1/4, 1/8, and 1/16 are performed.
The number is about 8 or 16. Therefore, these column decode circuits 6a to 6h are small in scale, so that
With sufficient margin, these inter-block areas ARa to A
Re.

FIG. 24 is a diagram schematically showing a configuration of the main amplifier group shown in FIG. In FIG. 24, main amplifier group 8 (8a to 8d) includes a main I / O line pair MIO.
It includes a main amplifier circuit 18a and a write driver 18b provided corresponding to each. Main amplifier circuit 18
a is activated at the time of data reading, and main I / O line pair MI
Amplify the data on O. Write driver 18b is activated at the time of data writing, and transmits write data onto main I / O line pair MIO.

As described above, according to the fifth embodiment of the present invention, by arranging the column decode circuit in the inter-block region and arranging the main amplifier group for each of the column blocks, these can be efficiently performed. A main amplifier group and a column decoder can be arranged. Further, the connection path between the main column selection line and the main I / O line and the column decoder and the main amplifier group is linear, and the wiring length can be minimized.

[Sixth Embodiment] FIG. 25 schematically shows an entire configuration of a semiconductor memory device according to a sixth embodiment of the present invention. In the configuration of the semiconductor memory device shown in FIG. 25, column decode circuits 6a to 6h and main amplifier groups 8a to 8d are selectively activated according to column block designating signal φcb. That is, only the main amplifier group and the column decode circuit provided corresponding to the column block designated by column block designating signal φcb are activated, and perform the column selecting operation and the data read / write operation. FIG. 25 shows an example in which main amplifier group 8b and column decode circuits 6c and 6d are selected. The other configuration is the same as the configuration shown in FIG.

As the memory capacity increases, the size of the memory mat also increases. In this case, the number of sense amplifiers operating at one time increases, and the number of bits of data latched by the sense amplifiers increases. For example, 256M
In a bit DRAM, 4K bits of data are latched by a sense amplifier in a single row access (row selection). Even if 1/4 selection is performed by the decoding circuit, 1K-bit data is selected. In the case of 1K-bit data (128-byte words), if the number of data is too large, the column decode circuit and the main amplifier group are activated in column block units according to the required data bit width. By connecting the main amplifier groups 8a to 8d to the global data bus 10 in common, data having an optimum bit width can be transferred. This makes it possible to optimize the scale of a register circuit for prefetching data and reduce current consumption by optimizing the number of main amplifiers and register circuits that operate simultaneously.

FIG. 26 schematically shows a structure of a row block selection signal and column block designating signal generation unit.
In FIG. 26, a block designating signal generating section decodes a given address signal Adr in response to activation of a column access activating signal φ, and applies a row block selecting signal φr
b, and a column block decoder 14 for decoding a given address signal Adc and generating a column block designating signal φcb in response to activation of a column access activation signal φ. Column access activation signal φ is activated when a column access command instructing data writing or reading is applied.

Column block designating signal φcb from column block decoder 14 is applied to column decoder 6. A column decode circuit included in column decoder 6 receives a given address signal Ady when column block designating signal φcb is activated to designate a corresponding column block.
And generates a column selection signal on the corresponding main column selection line.

Column selection is performed in units of column blocks, and main I / Os provided for unselected column blocks are provided.
The line pairs are kept in a standby state. Therefore, no current flows during reading data, so that current consumption is reduced.

Preamplifier group 8 (8a-8d) receives a control signal via gate circuit 15 receiving main amplifier activation signal PAE and column block designating signal φcb. When the output signal of gate circuit 15 is in an active state, main amplifier group 8 executes an operation of amplifying data on a corresponding main I / O line pair group.

Row block select signal φrb from row block decoder 12 is applied to a decode circuit provided in each memory sub-block. This row block selection signal φ
row and column block designating signal φ designated by rb
Data access is performed to a memory sub-block arranged corresponding to the intersection of the column block designated by cb.

In the structure shown in FIG. 25, column decode circuits 6a-6b and main amplifier groups 8a-8d are activated in column block units. Alternatively, as shown in FIG. 27, a selector SELR responding to column block instruction signal φcb may be provided between main amplifier groups 8a-8d and global data bus 10. Main I
All / O line pair groups MIOGa-MIOGd receive the data of the memory cells selected by the output signals of column decode circuits 6a-6h and transmit the data to main amplifier groups 8a-8d, but these main amplifier groups 8a-8d Are selected in column block units by the selector SELR and are coupled to the global data bus 10. Therefore, the width of global data bus 10 can be modified in units of column block size. If the selector SELR has a function of changing the connection path between the main amplifier groups 8a-8d and the global data bus 10 according to the data bit width transferred to the global data bus 10,
The global data bus 10 can support a plurality of types of data bit widths.

As described above, according to the sixth embodiment of the present invention, column selection and data access are performed in a predetermined number of column blocks out of a plurality of column blocks. Data can be transferred, and the optimization of the internal circuit scale and the optimization of the current consumption can be realized.

[Seventh Embodiment] FIG. 28 schematically shows a whole structure of a semiconductor memory device according to a seventh embodiment of the present invention. In the configuration shown in FIG. 28, a decode circuit (block decode circuit) provided in each memory sub-block drives the same local column select signal line from both sides in the row direction. As a result, even when the number of divisions of the memory sub-block is reduced or the capacity of the memory sub-block is increased and the size in the row direction is increased, the local column selection line is driven to the selected state at high speed. can do. The other configuration is the same as the configuration shown in FIG.

FIG. 29 shows a structure of a portion related to one memory sub-block. In FIG. 29, sets of main column select lines SGa and SGb are arranged on both sides of the memory sub-block MSB along the row direction. In a lower region of the memory sub-block MSB in the column direction, a decode circuit 20aa receiving a column selection signal and a row block selection signal φrb on a main column selection line SGa, and a main column provided in an inter-block region AR # b Decoding circuit 20ab receiving selection signal on selection line SGa and row block selection signal φrb is provided. These decoding circuits 20aa and 20aa
ab commonly generates a local column selection signal LSa.

In the upper region in the column direction of memory sub-block MSB, decode circuit 20 receiving a column selection signal on main column selection line SGb and a row block selection signal φrb provided in inter-block region AR # a.
decode circuit 20bb receiving ba and a column selection signal on main column selection line SGb and row block selection signal φrb provided in inter-block region AR # b. These decoding circuits 20ba and 20bb are
A local column selection signal LSb is commonly generated.

The size of memory sub-block MSB in the row direction increases, and local column select signal LS
Even when the length of the local column select line transmitting a and LSb becomes long, the local column select line is driven by the decode circuits on both sides, so that local column select signals LSa and LSb are brought into the selected state at high speed. Can be driven.

In the structure shown in FIG. 29, main column select signals SGa and SGb may each be a multi-bit signal line.

In the structure shown in FIG.
A selector as shown in FIG. 7 may be provided.

As described above, according to the seventh embodiment of the present invention, since the common local column select lines are driven from both sides of the memory sub-block, the size of the memory sub-block is increased. In this case, the local column selection line can be driven at high speed.

In this case, the number of main column select lines provided in each inter-block area is doubled. However, if the main column select lines are shared by adjacent memory sub-blocks, the signal line Expansion is prevented.

[Eighth Embodiment] FIG. 30 schematically shows a whole structure of a semiconductor memory device according to an eighth embodiment of the invention. In FIG. 30, the main amplifier group 8a
To 8d are the left main amplifier groups 8al to 8d
1 and the right main amplifier group 8ar to 8dr. The column decode circuit selects the left column group or the right column group of the corresponding column block, respectively. That is, column decode circuit 6a selects a column in the left area of column block C # 0 in the row direction, and column decode circuit 6b selects a right column group of column block C # 0. Similarly, in the remaining column decode circuits 6c to 6h, at the time of selection, the corresponding column blocks C # 1 to C # 3 perform the selecting operation on the left or right half column.

In order to select a half column in this memory sub-block, a left / right selection signal φrl is applied to column decode circuits 6a-6h and main amplifier groups 8a-8d. In a column block specified by column block specifying signal φcb, a column decode circuit and a main amplifier group provided for an area specified by left / right specifying signal φrl are activated. Even when the size of the memory sub-block in the row direction increases, a necessary number of data bits are selected. As a result, the number of main amplifiers operating simultaneously in the main amplifier groups 8a to 8d is reduced, and the occurrence of power supply noise due to local current consumption concentration caused by the operation of the main amplifiers that are locally arranged is suppressed.

FIG. 31 schematically shows a structure of a portion corresponding to one memory sub-block. In FIG. 31, the memory sub-block MSB is divided into a left memory sub-block MSB1 and a right memory sub-block MSBr. At the time of row selection operation, memory cells in one row are simultaneously selected in memory sub-block MSB,
One row of data is latched by a sense amplifier (not shown).

In the region on the left side of the memory sub-block MSB in the row direction, a decode circuit 25aa receiving a column select signal on main column select line SGa and a row block select signal φrb, a row block select signal φrb, and a main column select line SGb A decode circuit 25ba receiving the upper column select signal is provided. These decode circuits 25aa and 25ba are connected to memory sub-block MS
Column selection signal LSal for the left region MSBl of B
And LSbl.

In the inter-block region AR # b on the right side of the memory sub-block MSB in the row direction, a decode circuit 25ab receiving a column select signal on main column select line SGa and a row block select signal φrb, and a main column select line A decode circuit 25bb for receiving a column selection signal and a row block selection signal φrb on SGb is provided. Column select signals LSa and LSbr from decode circuits 25ab and 25bb are applied to right block MSBbr of memory sub block MSB.

Main column select lines SGa and SGb in inter-block region AR # a and inter-block region AR #
b, the main column selection lines SGa and SGb
It is selectively driven to an active state according to left / right designation signal φrl shown in FIG. Thereby, one column of blocks MSBl and MSBr in memory sub-block MSB is selected and connected to a main I / O line pair (not shown).

In the structure shown in FIGS. 30 and 31, memory sub-blocks are divided into two along the row direction.
Is divided into two blocks. However, the memory sub-block may be divided into four. Accordingly, the column decode circuit and the main amplifier group are simply divided into four groups.

Further, a selector as shown in FIG. 27 may be provided.

As described above, according to the eighth embodiment of the present invention, the memory sub-block is divided into a plurality of groups, and the column decoder and the main amplifier group are activated in each group. Therefore, it is possible to reduce the number of main amplifier groups that operate simultaneously, suppress generation of power supply noise due to local concentration of current consumption, and realize a stable data reading operation. Further, by operating the main amplifier group according to the necessary minimum number of data bits, current consumption can be reduced, and data having a required bit width according to the internal configuration can be selected.

[Ninth Embodiment] FIG. 32 schematically shows a whole structure of a semiconductor memory device according to a ninth embodiment of the invention. In FIG. 32, the main amplifier group 8a
Latch groups 30a to 30d for latching applied data are provided corresponding to the respective. For these latch groups 30a to 30d, a column group selection circuit 32 for selecting a predetermined number of bits of data in accordance with a column group selection signal (data bit selection signal) YB and connecting to a global data bus 35 is further provided. The other configuration is the same as the configuration shown in FIG.

In the structure shown in FIG. 32, FIG.
Data is read from all the memory sub-blocks in the row block, as in the configuration shown in FIG. Therefore, in this case, for example, 1K-bit data is read out in parallel, transmitted to main amplifier groups 8a to 8d, and amplified. The data amplified by these main amplifier groups 8a to 8d are latched by the latches included in corresponding latch groups 30a to 30d. The column group selection circuit 32 controls the global data bus 3 according to the column group selection signal YB.
The data corresponding to the bit width of 5 is selected. Therefore,
By sequentially transferring 1-Kbit data in accordance with the bus width of the internal global data bus 35, it is possible to internally perform data transfer in a pipelined manner.
High-speed data transfer can be realized, and since a large number of data are latched simultaneously, there is no need to sequentially transfer data from the sense amplifier, and the transfer speed can be further increased. Also, at the time of column selection, it is only necessary to select data latched in the latch group, and there is no need to transfer data from the sense amplifier to the global data bus via the main amplifier group, thereby realizing high-speed column access. You.

FIG. 33A schematically shows a structure of one bit of the main amplifier group and the latch group shown in FIG. In FIG. 33A, the main amplifier 18a
Is provided with a latch 37a at an output portion thereof, and a latch 37b is provided at an input portion of the write driver 18b. These latches 37a and 37b are commonly coupled to column group selection circuit 32. In the configuration shown in FIG. 33A, latches 3 included in latch groups 30a to 30d
7a and 37b can be used as register circuits for data prefetch.

FIG. 33B shows another structure of the main amplifier group and the latch group. In the configuration shown in FIG. 33B, a latch 38a is provided at the input of the main amplifier 18a, and a latch 38b is provided at the input of the write driver 18b. Latch 38a latches data on main I / O line pair MIO, and latch 38b
Latch internal write data transferred at the time of data writing.

By setting latches 38a and 38b shown in FIG.
At the time of writing, the sense amplifier of the memory array can be separated from the main amplifier group and the latch group. At the time of data reading / writing, the main I / O line pair is driven to exchange data with the sense amplifier. High-speed writing / reading can be realized without having to consider the time for performing.

In the configuration shown in FIG. 32, FIG.
Any of the configurations shown in (B) and (B) may be used.

FIG. 34 schematically shows a structure of a read section corresponding to one memory sub-block. In FIG. 34, a main I / O line pair MIO included in a main I / O line pair group MIOG provided corresponding to one memory sub-block MSB corresponds to FIG. 33A or FIG. There are provided amplifiers and latches 40a to 40w including a main amplifier, a write driver and a latch as shown. On both sides of these amplifier latches 40a-40w,
Column decoders 6u and 6v are arranged, respectively.
Data selection gates 32a and 32b which are turned on corresponding to column group selection signals YB0 and YB1 are provided between amplifier / latches 40a-40w and global data bus 35. These data selection gates 32
Each of a to 32b transmits the data latched by the corresponding amplifier / latch during conduction to the corresponding bus line of global data bus 35 (at the time of data reading). The number of column group selection signals YB0,..., YB1 applied to memory sub-block MSB
May be determined appropriately in accordance with the bit width of.

Also, simultaneously in a plurality of column blocks,
A configuration may be used in which the data selection gates are turned on and the corresponding amplifier / latch is connected to the global data bus in parallel.

Further, an amplifier / latch may be connected to a global data bus only in one column block. Therefore, the number of amplifiers and latches connected to global data bus 35 is the same as in the first embodiment.
It is appropriately determined by using any one of the configurations from (1) to (8). From an amplifier / latch provided corresponding to one memory sub-block, a column group selection signal YB
Any configuration may be used as long as selection is performed according to 0 to YB1 and connected to the global data bus 35.

Each of amplifier / latches 40a-40w has the structure shown in FIG. 33 (A) or FIG. 33 (B).

FIG. 35 schematically shows a structure of a column related selection signal generating portion. In FIG. 35, row block address Adr is decoded and row block selection signal φr
A row block decoder 45 for generating b and a group decoder 46 for decoding a group address signal Adg to generate a data group selection signal YB are provided. In the configuration of generating the selection signal shown in FIG. 35, one row block is selected by row block decoder 45, and
One row of memory cell data included in this row block is transferred to the main amplifier group. According to the group selection signal YB from the group decoder 46, the data bits of the group selected by the group selection signal YB are selected from the memory cell data of one row. In this case, one block of data bits may be selected from one column block, or a configuration in which data bits are selected from one row of memory cell data and distributed over a plurality of column blocks may be used.

FIG. 36 shows another structure of the control signal generator for selecting data bits. In FIG. 36, row block decoder 45 decodes row block address Adr to generate row block selection signal φrb.
And a group decoder 46 for decoding a group address Adg to generate a group specifying signal, and a column block decoder 47 for decoding a column block specifying address Adc to generate a column block specifying signal φcb. Column block designating signal φcb from column block decoder 47 is applied to a column decoder and a group of main amplifiers. A group selection signal YB is output from an AND circuit 48 which receives and decodes the column block designation signal φcb and the group identification signal from the group decoder 46.

In the structure shown in FIG. 36, among the data bits read from the column block selected by column block designating signal φcb, the data bits of the group designated by the group specifying signal from group decoder 46 are further selected. Is done. The column decoder and main amplifier group provided for the non-selected column block maintain a non-selected state (inactive state). This FIG. 35 and FIG.
6 may be used.

The structure of a path for transferring internal data from global data bus 35 and outputting the data to the outside of the semiconductor memory device via an output buffer is appropriately determined according to the pipeline structure inside the semiconductor memory device. It only has to be determined. Further, a register may be further provided in this pipeline configuration, and a plurality of words of data stored in this register may be sequentially selected. In any case, data is latched by a latch group, and when accessing data, it is only necessary to access this latch group, and there is no need to drive a main I / O line, thereby realizing high-speed data transfer. , And a high-speed data transfer can be realized.

[Tenth Embodiment] FIG. 37 schematically shows a whole structure of a semiconductor memory device according to a tenth embodiment of the present invention. In FIG. 37, semiconductor memory device 50 includes memory mats MTa to MTh arranged in alignment with one side of central region 52 arranged in the row direction at the center of the chip along the column direction. , This central area 5
2 includes memory mats MTi to MTp arranged in alignment with each other in the row direction. These memory mats M
The configuration of Ta to MTp will be described later,
It has a plurality of memory cells arranged in a matrix.

In central region 52, main control circuit 58 is arranged at the center in the row direction, and peripheral pad groups 57a and 57b receiving external address signals and control signals are arranged on both sides thereof. . Address signals and control signals applied to peripheral pad groups 57a and 57b are applied to main control circuit 58, and access operation to memory mats MTa to MTp is performed by main control circuit 5
8 is performed.

In central region 52, a pad (DQ pad) for data input / output and a DQ pad group including an input / output buffer circuit for data input / output are provided outside peripheral pad groups 57a and 57b. 5
5a and 55b are arranged. This peripheral pad group 57
DQ pad groups 55a and 55
The configuration in which b is arranged is called “ODIC (outer DQ / inner clock) configuration”. By arranging the peripheral pad groups 57a and 57b near the main control circuit 58, the distance between the buffer for receiving an external address signal and a clock signal (control signal) and the main control circuit 58 is shortened, and the speed is increased. , These external signals can be transmitted. Also, DQ pad groups 55a and 55b
By arranging them in an area outside the central area 52, the distance between the memory mat and the DQ pad group is shortened, and high-speed data transfer is achieved. Here, the DQ pad part is
It includes a DQ pad for inputting / outputting data and a data input / output buffer for buffering signals.

In central region 52, a global data bus 60a is provided extending in the row direction and shared by memory mats MTa to MTd.
Global data bus 60b is arranged commonly to MTl. These global data buses 60a and 60b
Are coupled to a DQ pad group 55a. DQ pad group 5
5b, a global data bus 6 provided in common to memory mats MTe to MTh and extending in the row direction.
0c and a global data bus 60d provided in common to memory mats MTm to MTp and extending in the row direction. Global data buses 60c and 60d are coupled to DQ pad group 55b.

In data access, DQ pad group 55a and DQ pad group 55b perform data input / output operations in parallel. The number of memory mats driven simultaneously to the selected state is arbitrary. Memory mat MTa
To MTd and MTi to MTl are simultaneously selected to input / output data to / from DQ pad group 55a. Further, a predetermined number of memory mats are selected from memory mats MTe to MTh and MTm to MTp to input / output data to / from DQ pad group 55b.

FIG. 38 schematically shows a structure of a portion related to one memory mat of the semiconductor memory device shown in FIG. 38, memory mat MT includes a plurality of memory row blocks RB # 0-RB # 31 and sense amplifier bands SB # 0-SB # 31 provided corresponding to memory row blocks RB # 0-RB # 31, respectively. including.
Memory row block RB # i (i = 0 to 31) and sense amplifier band SB # i (i = 0 to 31) are included in one bank BK #
i. In the configuration shown in FIG. 38, memory mat MT is divided into 32 banks BK # 0 to BK # 31. These banks BK # 0 to BK # 31 can independently drive a memory cell row (word line) to a selected state and can drive a memory cell row (word line) to a non-selected state.

Banks BK # 0-BK # 31 further have
It is divided into a plurality of subbanks, and data access is performed in subbank units. In the configuration of this subbank, as in the configurations of the first to ninth embodiments, each of sense amplifier bands SB # 0 to SB # 31 has
It is divided into a plurality of groups, and each group forms a subbank.

A main I / O line pair group MIOG is arranged extending in the column direction over sense amplifier bands SB # 0-SB # 31 and memory row blocks RB # 1-RB # 31.

Sub bank selecting circuits SBS0 to SBS corresponding to sense amplifier bands SB # 0 to SB # 31, respectively.
31 are provided. These sub-bank selection circuits SBS
0 to SBS31 are banks / mats for specifying banks / mats.
Mat designation signal BK / MT and sub-bank designation signal SB
According to K, one sub-bank is driven to the selected state in the corresponding bank. Sense amplifier band SB # 0-SB
# 31 each has a corresponding one of sub-bank selection circuits SBS0-SBS0.
The sense amplifier included in the sub-bank selected by the SBS 31 is connected to the main I / O line pair included in the main I / O line pair group MIOG.

Main I / O line pair group MIOG is coupled to write / read circuit 62 provided at one end of the memory mat. Write / read circuit 62 includes main I / O line pair group MIO.
G includes a set of a main amplifier and a write driver provided corresponding to each main I / O line pair included in G.

Data bit selection circuit 64 couples a main amplifier / write driver set included in write / read circuit 62 to global data bus 60 in accordance with a Y selection signal from Y decoder 66. The number of bits simultaneously selected by data bit selection circuit 64 is appropriately determined according to the number of memory mats connected to global data bus 60 and the bit width of a transfer circuit used in global data bus 60.

In memory mat MT, a plurality of banks can be simultaneously driven to a selected state, and data can be latched in a corresponding sense amplifier band. Of the plurality of banks, the sub-bank selection circuit selects 1
Select one sub-bank and select main I / O line pair group MIOG
To perform data access. By sequentially switching banks, data access can be performed at high speed without the overhead of switching pages.

FIG. 39 shows the structure of the memory mat shown in FIG. 38 in more detail. 39, bank BK # 0 and bank BK # 31 and write / read circuit 6
2 is shown. In row block RB # 0 included in bank BK # 0, main word line M
WL is arranged, and a plurality of bit line pairs BLP are arranged in the column direction. Main word line MWL is connected to a sub word line via a sub word line driver in an inter-block region (not shown). For example, 4K bit line pairs BLP are provided. A sense amplifier SA is provided for each bit line pair BLP. A sub-bank selection gate SSG for a set of four adjacent sense amplifiers SA
Is arranged.

In sense amplifier band SB # 0, a sense amplifier SA and a sub-bank selection gate SSG arranged in a line are provided. A main I / O line pair MIO corresponds to each of the subbank selection gates SSG.
0 to MIO1023 are provided. Sub bank select gate SSG includes I / O select gates N1, N2, N3 and N4 respectively coupled to different sense amplifiers.
I / O select gates N1 to N4 included in one subbank select gate SSG are coupled to the same main I / O line pair MIO.

In order to selectively drive these I / O select gates N1 to N4 to the conductive state, four decode circuits G1 and G are provided in corresponding subbank select circuit SBS0.
2 and G3, and G4 are provided. These decode circuits G1 to G4 provide a bank / mat designation signal BK /
MT and a sub-bank designation signal SBK are received. bank/
In the bank specified by mat specifying signal BK / MT,
The I / O select gate provided corresponding to the sub-bank designated by sub-bank designation signal SBK is driven to a conductive state.

Bank BK # 31 has a similar structure. Sub bank select gate SSG arranged in line along the column direction is formed of a common main I / O line pair M
Connected to IO. Sub-bank selection circuit SBS31 provided for bank BK # 31 also has sub-bank decode circuits G1, G2, G3 and G receiving bank / mat designation signal BK / MT and sub-bank designation signal SBK.
4 inclusive. Sub bank selection circuits SBS0 to SBS31 have different bank / mat address signals. The 4-bit sub-bank designating signal SBK is applied to sub-bank selecting circuits SBS0 to SBS0 of banks BK # 0 to BK # 31.
It is provided commonly to each of the SBSs 31.

Write / read circuit 62 includes a set of main amplifier 62p and write driver 62w provided corresponding to each of main I / O line pairs MIO0-MIO1023. One of main amplifier 62p and write driver 62w is activated according to the data write / read mode.

Data bit selection circuit 64 includes data selection gates 64a to 64x for simultaneously selecting a predetermined number of sets of the main amplifier / write driver. In FIG. 28, four main I / O line pairs are simultaneously selected and connected to global data bus 60. The number of main I / O line pairs selected at the same time depends on the global data bus 60.
And the number of memory mats selected at the same time.

The data selection gates 64a to 64x
Corresponding to each, the data bit selection address YS
Y decode circuit 6 for decoding (predecode signal)
6a to 66x are provided. A predetermined number of sets of main amplifiers and write drivers 62w are selected by the data bit selection address (predecode signal) YS and connected to the global data bus 60.

In each of banks BK # 0-BK # 31, sense amplifier SA and sub-bank selection gate S
An SG is provided. Therefore, banks BK # 0-BK
In each of # 31, a row of memory cells can be driven to a selected state via main word line MWL independently of each other. At the time of data access, the bank / mat address and sub-bank address determine
Mat designating signal BK / MT and sub-bank designating signal S
BK to generate the sense amplifiers SA of the sub-banks in the selected bank and to the main I / O line pairs MIO0 to MIO.
Connect to IO1023. Next, the write / read circuit 62
Amplifier 62p or write driver 62
w is activated, and data read / write is performed. Then, according to the output signals of Y decode circuits 66a to 66x, one of data bit select gates 64a to 64x conducts, and a main amplifier / write driver pair is coupled to global data bus 60. Next, FIG.
The operation of the semiconductor memory device shown in FIG. 39 will be described with reference to a timing chart shown in FIG.

This semiconductor memory device is a clock synchronous type semiconductor memory device which fetches an external control signal (command CMD) in synchronization with an externally applied clock signal CLK, fetches write data, and outputs data. is there.

In FIG. 40, first, in clock cycle # 0, a bank active command BAACT for driving a bank to a selected state is applied. At the same time as the bank active command BAACT, a bank / mat address B for designating a bank and a memory mat is provided.
AMD is applied, and a row address R for designating a word line in the bank is applied. According to bank active command BAACT and addresses BA and R, a corresponding word line is selected in a designated bank, and data of a memory cell arranged corresponding to the selected word line (main word line and sub word line) is sensed. It is detected, amplified, and latched by the amplifier SA. According to the bank active command, a row selecting operation is performed in the bank of the mat specified by bank / mat address BAMD. The row selection operation of the memory cells in the designated bank does not affect the state of the other banks.

In clock cycle # 1, subbank active command SBACT is applied. Subbank active command SBACT is applied simultaneously with bank / mat address BAMD and subbank address SBAD. When subbank active command SBACT is applied, bank / mat address B
According to bank / mat address BA given as AMD and sub-bank address SBA given as sub-bank address SBAD, bank / mat address shown in FIG.
Mat designating signal BK / MT and sub-bank designating signal S
One of each BK is driven to a selected state. As a result, in response to the sub-bank active command SBACT, the sub-bank selection gate SSG is selectively turned on in the sub-bank of the designated bank, and the sense amplifier SA of the sub-bank included in the designated bank is connected to the main I / O.
/ O line pairs MIO0 to MIO1023. Thereby, main I / O line pairs MIO0-MIO1023
, The voltage level thereof changes from a predetermined precharged state by a sense amplifier of a designated sub-bank. This main I / O line pair MIO0-MIO1023
Are connected to a main amplifier 62p and a write driver 62w of the write / read circuit 62.

At this time, even if another bank is in the selected state, all of the gates N1 to N4 included in the corresponding sub-bank selection gate SSG are non-conductive, and no data collision occurs.

In clock cycle # 2, a write command instructing data writing is applied as external command CMD. At the same time as this write command,
A Y address is applied as the address signal Add.
At this time and simultaneously, write data is externally applied. At the time of data writing, external clock signal CLK
Data is taken in synchronism with the rising edge and falling edge of. This write data is transmitted to global data bus 60 (GIO) shown in FIG.
At the time of this data writing, the Y address given in clock cycle # 2 is used as the head address, and the Y address is automatically generated internally to generate data bit selection signal Y
S is generated. At the time of data writing, after two data (data written at rising and falling edges of a clock signal) are sequentially stored in a register described later, clock signal C of the next clock cycle is stored.
At the rising edge of LK, the global data bus 60 (G
IO).

In clock cycle # 3, data bit select signal YS is driven to the selected state according to address Y, and any of bit select gates 64a to 64x included in corresponding data bit select circuit 64 is driven to the selected state. You. When writing data, the write driver 62
w is activated, and the corresponding main I /
The O line pair is driven. In the operation shown in FIG. 40, the burst length is 4, four data D11 to D14 are sequentially captured at the rising edge and the falling edge of clock signal CLK, and the clock of the next cycle of the captured clock cycle is output. At the rising edge of signal CLK, it is transmitted to main I / O line pair MIO via global data bus and data bit selection circuit. In data writing, write driver 62w is simply driven to the selected state, and data is merely transmitted to the corresponding main I / O line pair.

After write data is transmitted to the main I / O line pair in clock cycle # 3 to clock cycle # 6, command C in clock cycle # 7
As MD, a read command indicating data reading is provided together with the Y address. When this read command is applied, the potential of main I / O line pair MIO only changes according to the write data, and corresponding sense amplifier SA needs to complete the latch of the write data. There is no. It is sufficient that the voltage level of main I / O line pair MIO changes in accordance with the write data.

Therefore, there is no need to wait for data reading until the latch data of the sense amplifier is stabilized at a state corresponding to the write data.
After writing the burst length data, a read command can be given immediately.

When this read command is applied, a data bit selection signal YS is generated according to the Y address applied at the same time, the selected bit selection gate (any of gates 66a to 66x) is turned on, and the main bit is turned on. Amplifier 62p is connected to global data bus (GIO) 60. When activated in accordance with the read command, the main amplifier 62p activates the main I / O which is already in a stable state.
The data on the O line pair is amplified and transmitted on the global data bus (GIO) 60. The data on the global data bus (GIO) 60 is stored in a latch circuit (or register) (not shown), and then stored in a clock signal CL.
It is sequentially output in synchronization with the rising and falling edges of K. According to the read command applied to clock cycle # 7, data Q11-Q11 of burst length (4)
Q14 is read.

When a read command and a Y address are supplied again in clock cycle # 9, data bits are selected by gates 66a to 66x using this Y address as a start address, and the output of corresponding main amplifier 62p is Bit select gates (64a to 64
x) to the global data bus, the next burst length data Q21 to Q24 are selected and output in synchronization with the rising and falling edges of clock signal CLK.

In the time chart shown in FIG. 40, when the reading of the burst length data is completed internally in clock cycle # 10, as indicated by the broken line, sub-bank designating signal SBK is driven to a non-selected state, and A structure in which / O line pair MIO is precharged to a predetermined potential may be used.

FIG. 41 schematically shows data propagation of a main I / O line pair. FIG. 41 shows data propagation to the sense amplifier arranged in bank BK # 0 farthest from write / read circuit 62.

When a sub-bank active command is applied at time t0, data latched by this sense amplifier is transmitted to main I / O line pair MIO via sub-bank selection gate SSG. The main I / O line pair is
The potential of the portion closest to the sense amplifier (the end farthest from the write / read circuit) changes in accordance with the latch data of the sense amplifier, and after a lapse of time Td, the end (MIO) closest to the write / read circuit. At the time t
At 1, the data reaching the write drive and the preamplifier is determined. At time t1, data writing / reading can be actually performed.

When a write command is applied at time t2, the potential of the most recent end of the main I / O line pair is changed by the write driver in accordance with write data WD, and the data of the main I / O line pair is changed to the main I / O line. The signal is transmitted via the O line pair and is transmitted to the farthest end of the main I / O line pair.
This time is a delay time Td. The data transmitted to the farthest end of the main I / O line pair is transmitted to the sense amplifier via the sub-bank selection gate SSG, and the latch data of the sense amplifier changes.

In this case, before time t4 when the latch data of the sense amplifier is inverted, data can be read out at time t3 when the signal potential at the most end of the main I / O line pair is determined. Therefore, data can be read before the latch data of the sense amplifier is determined (a read command can be given), and high-speed data reading can be performed. In particular, data can be read at high speed at the time of transition from the data write operation to the data read operation for the same subbank. Simply Main I
This is because only the signal charges held in the / O line pair are read, and no time is required until the state of the latch data of the sense amplifier in the memory sub-block is determined.

FIG. 42 schematically shows a structure of a data input / output unit. In FIG. 42, latches 70ra and 70rb for latching data on sub-global data buses GIOa and GIOb of an arbitrary bit width included in global data bus 60 in response to latch instruction signal φr, and latch in accordance with transfer instruction signal φrt 70r
a transfer gate 72ra for transferring the latch data of a to the output circuit 73, and the latch 7 in response to the transfer instruction signal zφrt.
A transfer gate 70rb for transferring data latched at 0rb to output circuit 73 is provided. Transfer instruction signal φr
t and zφrt are clock signals complementary to each other. Transfer instruction signals φrt and zφrt are activated at the time of data reading in synchronization with clock signal CLK. Therefore, transfer gates 72ra and 72rb alternately perform transfer operations, so that output circuit 73 is synchronized with the rising and falling edges of clock signal CLK.
Data can be output via the.

The data input / output unit further includes an input circuit 74 for inputting external data at the time of data writing, a latch circuit 70wa for latching data from the input circuit 74 in response to a latch instruction signal φw, Latch instruction signal zφr
and a transfer gate 72wa for transferring the data latched by the latches 70wa and 70wb to the sub-global data buses GIOa and GIOb in response to the transfer instruction signal φwt. And 72wb.

In the configuration of the data input / output portion shown in FIG. 42, at the time of data reading, two data transferred onto global data bus 60 are latched by latches 70ra and 70rb, and then transferred to transfer gates 72ra and 72rb. , And are alternately transferred in synchronization with the edge of the clock signal. On the other hand, at the time of data writing, internal write data from input circuit 74 is alternately latched by latches 70wa and 70wb, and then transferred onto global data bus 60 in parallel by transfer gates 72wa and 72wb. Thereby, data input / output can be performed in synchronization with the rising edge and falling edge of clock signal CLK, and the internal circuit operation can be performed in response to one edge (rising edge) of clock signal CLK.

FIG. 43 schematically shows a structure of the selection signal generating portion shown in FIGS. 38 and 39. Referring to FIG. Referring to FIG. 43, a selection signal generator fetches and decodes an external command CMD in synchronization with clock signal CLK, and generates a designated operation mode instruction signal, and a bank activation from command decoder 80. Bank activation control circuit 81 activated in response to an instruction signal to generate a control signal for driving a bank to an active state
And a bank address latch 82 for latching an external bank / mat address BAMD in response to a bank activation instruction signal and a sub-bank activation instruction signal from command decoder 80, and decodes an output signal of bank address latch 82. Bank / mat designation signal BK /
Bank decode latch 8 for generating and latching MT
3 and an external sub-bank address SBA in response to a sub-bank activation instruction signal from command decoder 80.
Sub-bank address latch 84 for taking in and latching D
And decodes the sub-bank address latched by the sub-bank address latch 84 to generate a sub-bank designation signal S
A subbank decode / latch 85 for generating BK, an address latch 86 for latching an external address signal Add in response to a subbank activation instruction signal or a data write / read instruction signal from the command decoder 80,
In response to a read / write instruction signal from the command decoder 80, a burst address counter 87 which takes in the address of the address latch 86 as a head address and sequentially changes the address taken in a predetermined sequence, and an output of the burst address counter 87 An address decoder 88 for decoding an address to generate a data bit selection signal YS is included.

Burst address counter 87 and address decoder 88 operate in synchronization with clock signal CLK under the control of read / write control circuit 89 activated in response to a read / write instruction signal from command decoder 80. I do. This read / write control circuit 89
The burst address counter 87 and the address decoder 88 are activated in synchronization with the clock signal CLK. The read / write control circuit 89 also
In order to write / read data, control of activation / inactivation of a main amplifier and a write driver included in a write / read circuit and operation of a transfer unit shown in FIG. 42 are controlled.

In the structure shown in FIG. 43, data bit select signal YS from address decoder 88 is applied to each memory mat, and is logically ANDed with the memory mat address. Is performed. This is the same as the control operation performed by read / write control circuit 89 in which the main amplifier and the write driver are activated / deactivated only for the memory mat including the selected sub-bank / bank.

According to the structure shown in FIG. 43, sub-bank designating signal SBK is generated according to the signal waveform diagram shown in FIG.
After the sub-bank address command SBACT is applied, the active state is maintained. This sub-bank designation signal SB
K may be set to a reset state after a lapse of a long burst period when a write command or a read command is applied, and a configuration may be provided in which the main I / O line pair is precharged to a predetermined potential level.

In the timing chart shown in FIG. 40, if the write command and the read command are commands having an auto precharge function,
After writing / reading the burst length data, precharging main I / O line pair to a predetermined potential and bank designating signal SBK
May be used to drive to the non-selected state. In this case, when a write command or a read command is applied every burst period, the auto precharge is reset, and the precharge of the main I / O line pair to the predetermined potential level is not performed.

The timing when this read / write command has an auto precharge function is shown in FIG. 40 by referring to the main I / O line pair and the subbank designating signal SBK.
Are indicated by broken lines.

[Modification] FIG. 44 shows an operation sequence of a modification of the tenth embodiment of the present invention. FIG.
In 4, the command CMD from the outside includes a sub-bank active command SBACT and a sub-bank precharge command SBPRG. When subactive command SBACT is applied, subbank designating signal SBK is driven to a selected state for a predetermined period, and data latched by the sense amplifier of the subbank designated by subbank active command SBACT is transmitted to main I / O line pair MIO. Is done. When the predetermined period elapses and the sub-bank selection signal SBK enters a non-selected state, the main I / O
O line pair MIO is in a floating state, and holds data transmitted from the selected sub-bank. In this state, data writing / reading is performed. Writing data /
In reading, since the memory array portion is cut off, only data writing / reading with respect to the main amplifier and the write driver is performed, and via the main I / O line pair and the sense amplifier having the longest signal propagation delay. Since a path for writing / reading data to / from a memory cell is omitted, data writing / reading can be performed at high speed.

When data writing / reading is completed and access to the subbank is completed, subbank precharge command SBPRG is applied. In accordance with sub-bank precharge command SBPRG, sub-bank designating signal SBK is again driven to the selected state of H level for a predetermined period, the main I / O line pair and the sense amplifier of the specified sub-bank are connected for a predetermined period, and the sense of the sub-bank is Data is written back to the amplifier. This is because, at the time of data writing, write data is transferred to and held on the main I / O line pair, and this write data is not transferred to the sense amplifier. After sub-bank precharge command SBPRG is applied and sub-bank designating signal BSK is driven to the selected state for a predetermined period,
Main I / O line pair MIO is precharged to a predetermined potential level.

At the time of sub-bank switching, it is necessary to apply sub-bank precharge command SBPRG, and one clock cycle is required at the time of sub-bank switching. However, if sub-bank switching is performed by switching memory mats, the overhead due to the sub-bank precharge command does not affect external access. Further, the bank maintains the selected state, and the sub-bank select gate is only activated / deactivated, which is different from the bank precharge command which normally switches the word line from the selected state to the non-selected state. Therefore, the time required for this precharge operation is short, shorter than the time required for bank deactivation by a normal bank precharge command, and the overhead at the time of sub-bank switching is sufficiently smaller than the overhead at the time of bank switching. Is not impaired (when access is performed continuously in the same mat).

The structure for driving subbank designating signal SBK to the active state for a predetermined period in response to subbank active command SBACT and subbank precharge command SBRPG shown in FIG. 44 is different from the structure shown in FIG. 85,
A configuration in which the main I / O line pair precharge circuit is activated for a predetermined period in accordance with an output signal from command decoder 80 may be used. When the charge command SBPRG is given,
A configuration that is activated after a predetermined time has elapsed may be used.

FIG. 45 schematically shows a structure for one main I / O line pair at the time of data writing / reading in the structure of the modification of the tenth embodiment of the present invention. FIG.
5, a parasitic capacitance Cp exists in the main I / O line pair MIOi. A main amplifier 62p and a write driver 62w are provided for the main I / O line pair MIOi. The main amplifier 62p and the write driver 62w are connected to a global data bus line 60a via a selection gate 64ij included in the data bit selection circuit 60. Select gate 64ij receives select signal φys generated by decoding data bit select signal YS at its gate.

When subbank active command SBACT is applied as shown in FIG. 44, subbank selection signal SBK is activated for a predetermined period, and main I / O line pair MI
Data is transmitted to Oi, and data from the sense amplifier of the corresponding subbank is stored in the parasitic capacitance Cp. When the sub-bank selection signal SBK is driven to a non-selected state,
This main I / O line pair MIOi is in a floating state. When a write / read command is given, the write driver 62w or the main amplifier 62p is activated. In this state, at the time of data reading, data simply stored in the parasitic capacitance Cp is amplified by the main amplifier 62p and transmitted to the global data bus line 60a via the selection gate 64ij. At the time of data writing, write data on global data bus line 60a is applied to write driver 62w via select gate 64ij.
The write driver 62w amplifies the given write data and stores it in the parasitic capacitance Cp. Therefore, this main I / O line pair MIOi is driven to the farthest end,
There is no need to exchange data with the corresponding sense amplifier,
High-speed data access becomes possible.

When the data access is completed, the main I / O line pair MIOi is connected to the sub-bank again to write data, and after the completion, is precharged to a predetermined potential.

FIG. 46 schematically shows a structure of a precharge circuit provided for one main I / O line pair and a control portion thereof. In FIG. 46, the main I /
O line pair precharge control circuit is set / reset flip-flop 90 which is set in response to sub-bank activation instructing signal φsbact and reset in response to sub-bank precharge instructing signal φsbprg, and set / reset flip-flop 90 And an OR circuit for receiving a signal from output Q of sub-bank and sub-bank selection signals SBK0 to SBK3 included in the sub-bank designation signal. Precharge circuit 92 is formed of a p-channel MOS transistor, and precharges each I / O line of main I / O line pair MIO to power supply voltage Vcc level.

Sub-bank activation instructing signal φsbact
Is driven to an active state for a predetermined period when subbank active command SBACT is applied. Subbank precharge instructing signal φsbprg is driven to an active state for a predetermined time when subbank precharge command SBPRG is applied. Therefore, when subbank active command SBACT is applied, set / reset flip-flop 90 is set, and the precharge instruction signal from OR circuit 91 attains an H level,
Accordingly, precharge circuit 92 is deactivated. On the other hand, when sub-bank precharge instructing signal φsbprg is activated, set / reset flip-flop 9
0 is reset. Subbank selection signal SBK0-S
When all BK3 are inactive at L level, the output signal of OR circuit 91 is activated at L level, precharge circuit 92 is activated, and main I / O line pair MIO is activated.
Are precharged to the power supply potential Vcc level.

Therefore, after the sub-bank active command is applied and before the sub-bank precharge command SBPRG is applied, each I / O line of the main I / O line pair is in a floating state, and the parasitic capacitance Cp
(See FIG. 45), data access is performed.

As described above, the tenth embodiment of the present invention is described.
According to this, in a plurality of banks and sub-banks sharing a main I / O line pair, data of a selected sub-bank is transferred to a write / read circuit by using a sub-bank active command, and thereafter, by using a write / read command. Since data writing / reading is performed, data writing / reading is performed by a write / read including a main amplifier and a write driver.
It only needs to be performed for the read circuit, and there is no need to drive the main I / O line pair and the sense amplifier. The delay time in the signal propagation path between them can be eliminated, and high-speed access can be performed. In particular, at the time of accessing the same sub-bank, switching from the write operation to the read operation only requires driving the main amplifier, and there is no need to wait until write data is written to the sense amplifier.
It is possible to switch from a write operation to a read operation at a high speed.

[Eleventh Embodiment] FIG. 47 schematically shows a structure of a main portion of a semiconductor memory device according to an eleventh embodiment of the present invention. In FIG. 47, bank BK #
0 to BK # 31, the main I / O line pair MI
O0 to MIO1023 are provided. These main I
In a write / read circuit for transmitting and receiving data to / O line pairs MIO0-MIO1023, a latch circuit 95a is provided before the main amplifier 62p, and a latch circuit 95b is provided before the write driver 62w. The other configuration is the same as the configuration shown in FIG. 39, and corresponding portions are denoted by the same reference numerals. Here, in FIG.
Data bit selection circuits 64a to 64x are shown to include selection gates TG0 to TG3, respectively.

Latch circuit 95a takes in and latches data read onto main I / O line pairs MIO0-MIO1023 when the subbank is activated. At the time of data reading, after data is taken into latch 95a, main I / O line pairs MIO0-MIO1023 can be returned to the precharge state. On the other hand, at the time of data writing, the main I / O line pair MIO0-MIO1
023 can be held in the precharge state, and the write data can be latched by the latch circuit 95b. Thereafter, the sub-bank is selected, and the data written in the latch circuit 95b is written via the write driver 62w. When exchanging data with the outside, latch circuits 95a and 9a
Data transfer is performed between 5b and a data input / output circuit (not shown) (see FIG. 42). Therefore, at the time of data transfer with this external device, the main I / O line pair MIO0-MIO1023 requiring the longest time for signal propagation.
The data transfer can be performed by separating the data transfer between the memory and the sense amplifier, and high-speed data access is realized.

FIG. 48 shows an example of the structure of a portion corresponding to the 1-bit main I / O line pair MIO of the write / read circuit shown in FIG. In FIG. 48, latch circuit 95a is rendered conductive when sub-bank selection instructing signal φsbk is activated to transmit a signal potential on main I / O line pair MIO, and a signal applied via transfer gate 95aa. And an inverter 95ac that inverts an output signal of the inverter 95ab and transmits the inverted signal to an input portion of the inverter 95ab. Inverters 95ab and 95a
c constitutes an inverter latch. This latch circuit 9
The latch data of 5a is applied to the main amplifier 62p.

Main amplifier 62p is activated when main amplifier activation signal PAE is activated.
Amplify the data provided from 5a.

Latch circuit 95b is rendered conductive in response to a write activation instruction signal φwr activated at the time of data writing.
Global data bus line 60a via select gate TG
(GIO), a transfer gate 95ba for transferring data given thereto, and the transfer gate 95ba.
Inverter 95b for latching data transmitted by
b and 95bc. The latch data of latch circuit 95b is applied to write driver 62w activated in response to write driver enable signal WDE.

Therefore, global data bus 60
At the time of data access to an external device via the (bus line 60a), the main I / O line pair MIO is disconnected from the global data bus 60 (bus line 60a), and the latch circuit 95a or 95b is connected to the global data bus 60 (bus line 60a). Data can be exchanged with the bus line 60a),
High-speed data access becomes possible. Next, FIG.
The operation of the semiconductor memory device shown in FIG. 48 will be described with reference to a timing chart shown in FIG.

In clock cycle # 0, bank active command BACT is applied. According to bank active command BAACT, a row selecting operation is performed in the bank specified by address BAa given as bank / mat address BAMD.

Then, in clock cycle # 1, a write command indicating data writing is applied. When this write command is applied, address BAa is applied as bank / mat address BAMD, and address Y applied at that time specifies data bit group Ya. When a write command is applied, sub-bank address SBAD is not required. Figure 47
This is because data is written to latch circuit 95b shown in FIG. Along with this write command, write data D
11, D12, D13 and D14 are applied in synchronization with the rising and falling edges of clock signal CLK, respectively. A column selection operation is internally performed using address Ya as a start address. Write data is transferred to the internal global data bus every clock cycle in two data units. In clock cycle # 2, data bit select signal φys is driven to the selected state in accordance with address Ya, and global data bus G
Data on the IO (bus 60) is stored in a latch 95b provided in a stage preceding the selected write driver. In this write operation, write activation instructing signal φwr is activated, and data applied via transfer gate TG (FIG. 48) is taken into latch circuit 95b.

In clock cycle # 3, data bit select signal φys is again driven to the selected state in accordance with the burst address, and global data bus 60
The data on (GIO) is transferred to and latched by latch circuit 95b included in the newly selected data bit selection circuit.

In clock cycle # 3, at the same time, as a command CMD,
Write back command WBACK is provided. When this write-back command WBACK is applied, the bank / mat address BAa and the sub-bank S specified by the sub-bank address SBAD simultaneously supplied at the time are
BAa is driven to the selected state, and the sense amplifiers of the sub-banks included in the designated bank are connected to main I / O line pairs MIO0 to MIO1023. At this time,
The write driver 62w is activated in response to the write driver enable signal WDE, and the latch circuit 95b
Is transmitted to the main I / O line pair. Therefore, the transfer data from the write driver 62w is transferred to the sense amplifier of the selected sub-bank via the main I / O line pair and latched.

When this data transfer operation is completed, sub-bank designating signal SBK is driven to non-selection, and main I / O
The line pair is again precharged to a predetermined potential. In FIG. 49, main I / O line pair MI / O is shown to be precharged to the intermediate potential level, but may be precharged to power supply voltage Vcc level as shown in FIG.

In clock cycle # 4, a write command is applied again, and the bank / mat according to address BAa given as bank / mat address BAMD and address Yb given as Y address at that time.
A mat and column selection operation is performed. In accordance with this write command, data D21, D22, D23 and D24 are again transferred to latch circuit 95b and latched in accordance with data bit selection signal φys generated in accordance with a burst address starting from address Yb.

In clock cycle # 6, bank /
Address BAa is provided as mat address BAMD, and sub-bank address SBAb is provided as sub-bank address SBAD. In this case, different subbanks are selected in the same bank / mat. Therefore, newly written data D21 to D24
However, data is transferred from the write driver to the sense amplifier of the sub-bank SBAb via the main I / O line pair and latched.

In clock cycle # 7, sub bank active command SBACT is applied. When subbank active command SBACT is applied, a bank and a subbank are selected according to bank / mat address BAb and subbank address SBAc at that time, and the sense amplifier of the selected subbank is connected to main I / O line pair MI / O. The main I /
The data on the O line pair changes according to the data transferred from the sense amplifier. At this time, sub bank selection activation signal φsbk is activated again, and latch circuit 95a takes in and latches the data transferred onto the corresponding main I / O line pair MIO.

Then, in clock cycle # 8, a read command instructing data reading is applied, and data bits are selected according to bank / mat address BAb and bit group address Yc at that time, and corresponding main amplifier 62p outputs Is transmitted onto the global data bus line pair. Thereafter, data is sequentially selected with this address Yc as the leading address, and the data Q11 to Q14 selected in clock cycles # 8 and # 9 are sequentially output in synchronization with the rising and falling edges of clock signal CLK. Is done.

Subbank active command SBACT
Is applied and only during a predetermined period, the sub-bank selecting operation activating signal φsbk and the sub-bank designating signal SBK
Is driven to the selected state. After the data is transferred from the sense amplifier to the latch circuit 95a, the selected sub-bank is
Disconnected from the main I / O line pair. Therefore, after data is latched by latch circuit 95a, main I / O line pair M
I / O0 to MI / O1023 can be precharged to a predetermined voltage level.

As in the operation sequence shown in FIG. 49, at the time of data writing, write back command W
It is necessary to write data to the sub-bank by BACK. However, at the time of data reading, by applying subbank active command SBACT,
Data can be read continuously. Data transfer performed via the global data bus line pair is simply performed between latch circuits 95a and 95b and an input / output circuit. The main I / O line pair which has the longest time for signal propagation and the sense amplifier are separated during this internal data transfer (write / read operation). Therefore, high-speed data access can be performed from the outside.

When changing from data writing to data reading, a write-back command WBACK and a sub-bank active command SBACT are required. However, when the mode is switched to the main amplifier, by switching the mat, the write-back operation and the data read operation can be hidden. Also, at the time of bank switching at the time of data writing, the period required for this write-back operation can be hidden by switching the mat. Similarly, in the data read operation, when it is necessary to apply subbank active command SBACT, by accessing another memory mat, the period in which subbank active command SBACT is applied can be hidden from external access. With this configuration, the memory array, which requires the longest time for data transfer, and the main amplifier and the write driver are separated at the time of internal data transfer and writing / reading of external data, so that the clock cycle can be shortened. ,
High-speed access becomes possible accordingly.

FIG. 50 schematically shows a structure of the write / read circuit control unit. 50, a one-shot pulse generating circuit 102 for generating a one-shot pulse signal having a predetermined time width in response to a subbank activation instruction signal φ1 from command decoder 100, and a write operation mode from command decoder 100 A pulse generation circuit 103 generates a one-shot pulse signal in each clock cycle for a burst long period after a lapse of one clock cycle after a write command is applied in response to instruction signal φ2. This pulse generation circuit 103 includes a burst length counter (not shown),
00, a write operation mode instruction signal φ2 is applied.
A pulse signal .phi.wr having a predetermined time width is generated in response to the rise of clock signal CLK for a long burst period from the next clock cycle. As the configuration of the portion that generates each of the selection signals φys and SBK according to the address signal, the configuration shown in the tenth embodiment with reference to FIG. 43 can be used. Since the types of commands have increased (write-back commands), the configuration of the command decoder is only slightly different. The overall configuration is the same.

FIG. 51 schematically shows a structure of a precharge circuit for a main I / O line pair according to an eleventh embodiment of the present invention. In the configuration shown in FIG.
A structure in which a main I / O line pair is precharged to the level of power supply voltage Vcc is shown. In FIG. 51, the main I
Precharge circuit 1 for precharging / O line pair MIO
06 is controlled by the output signal of the OR circuit 105 receiving the sub-bank selection signals SBK0 to SBK3. OR circuit 105 outputs an H level signal to drive precharge circuit 106 to an inactive state when any of sub bank selection signals SBK0 to SBK3 is at an H level selected state, and outputs main I / O line The MIO is set to a floating state. On the other hand, sub-bank selection signals SBK0 to SBK
When all BK3s are inactive at L level, OR
The output signal of circuit 105 goes low, precharge circuit 106 is activated, and each I / O line of main I / O line pair MIO is precharged to power supply voltage Vcc level.

In the precharge circuit, an equalizing circuit may be further provided.
The / O line pair may be precharged to an intermediate voltage level.

In the tenth and eleventh embodiments, the structure of a so-called "2-bit prefetch" type synchronous semiconductor memory device is shown. That is, 2-bit data is prefetched for each data input / output terminal, and is sequentially transferred every clock cycle.
However, this means that an arbitrary number of data is prefetched simultaneously, as shown in the first to ninth embodiments,
A configuration in which data is sequentially transferred in synchronization with a clock signal may be used.

In the tenth and eleventh embodiments, the configuration of a 256 Mbit DRAM is shown as an example. However, the storage capacity of the semiconductor storage device may be another storage capacity. It is sufficient that one memory mat is divided into a plurality of banks, and a main I / O line pair is arranged to extend over the memory array in common for each bank. In this case, the bank may be different for each memory mat.

In the structure shown in FIGS. 38 and 39, a bank / mat address and a sub-bank selection signal are transmitted along one side of the outside of the memory array. However, in this configuration, as shown in the first to ninth embodiments, a decoder is arranged for each memory sub-block, and in each sub-block, a sense amplifier is selected by a corresponding decoding circuit. May be used.

The structures of Embodiments 10 and 11 can be used in an appropriate combination with the structures of Embodiments 1 to 9.

[0277]

As described above, according to the present invention, a decode circuit is provided for each memory sub-block, and a sense amplifier is selected in each memory sub-block, and an array is arranged extending in a matrix direction. Since the connection is made to the main I / O line pair, an arbitrary number of data bits can be simultaneously selected without increasing the area occupied by the array. Further, a decode circuit is provided for each memory sub-block, so that a propagation delay of a data bit selection signal (column selection signal) can be reduced, and a delay in column access can be prevented.

Further, when the memory array is divided into a plurality of banks, the structure is such that the transfer of the memory array and the transfer of the internal data are separated at the time of data access, so that high-speed data access is possible. .

That is, according to the invention of claim 1,
The memory array is divided into a plurality of memory sub-blocks in the row and column directions, internal data lines are arranged over the memory array, and columns of the corresponding memory sub-blocks are responded to column select signals corresponding to the respective memory sub-blocks. And a decode circuit that connects to the corresponding data line is provided.
Data having an arbitrary bit width can be selected without increasing column access without decreasing column access.

According to the second aspect of the present invention, since a decoding circuit for generating a column block selection signal and selecting a column of a corresponding memory block is arranged in a region between memory blocks, an empty area can be efficiently used. Thus, the decoding circuit can be arranged by utilizing the data, and an increase in the area occupied by the array can be suppressed.

According to the third aspect of the present invention, each of the block decode circuits arranged in the inter-memory block area is shared by the memory blocks arranged on both sides of the corresponding area in the row direction. Can be reduced, and the circuit occupied area can be reduced.

According to the invention of claim 4, since the memory block decode circuits are dispersedly arranged on both sides of the corresponding memory block in the column direction, the pitch condition of the decode circuits along the column direction is relaxed. Therefore, the block decoding circuit can be arranged with a margin.

According to the fifth aspect of the present invention, the column selecting circuit is configured to perform the column selecting operation in accordance with the bank designating signal. Therefore, even when the blocks arranged in the row direction constitute a bank, there is no problem. Data access can be performed without data collision on the internal data line.

According to the invention of claim 6, since a plurality of column decode circuits are arranged corresponding to the inter-memory block area, the column selection lines extend in the inter-block area along the column direction. Column decoding circuits can be efficiently arranged.

According to the seventh aspect of the present invention, since each of the plurality of column decode circuits is selectively activated in accordance with a block specifying signal for specifying a corresponding column block, when data having a small bit width is selected, Unnecessary circuit operation can be stopped, power consumption can be reduced, and data having a desired bit width can be selected.

According to the invention of claim 8, since the configuration is such that the column selection signals are transmitted in opposite directions from both sides in the row direction of the memory sub-block, the layout pitch of the decode circuit is relaxed. The decoding circuit can be arranged with a margin.

According to the ninth aspect of the present invention, since a plurality of decoders are configured to drive the same column selection line, even if the size of the memory block increases in the row direction, high speed operation is possible. Can drive the column select line,
It is possible to prevent the column access speed from decreasing.

According to the tenth aspect of the present invention, the memory sub-block is divided into a plurality of groups along the row direction and the decoding circuit is provided corresponding to each group. In this case, the decoding circuits can be dispersedly arranged, the pitch condition in the column direction of the decoding circuits is relaxed, and the decoding circuits can be arranged with a margin. Further, the number of data bits can be reduced to a desired number.

According to the eleventh aspect of the present invention, each of the block decode circuits is arranged along the column direction for every predetermined number of memory blocks, and the arrangement of the block decode circuits differs in the region between adjacent memory blocks. With this configuration, the pitch condition in the column direction of the block decoder is relaxed, and the block decoding circuit can be arranged with a margin.

According to the twelfth aspect of the present invention, a read circuit is provided corresponding to each column group, and a group specified by a read circuit provided for each internal data line included in the read circuit is further specified. Since data is read to another global data bus in accordance with a signal, data having a desired bit width can be internally transferred.

According to the thirteenth aspect, the read amplifier / write driver provided corresponding to each of the internal data lines can be selectively connected to the global data bus as the internal data bus and the data by the data group specifying signal. Since the transmission and reception are performed, data having a desired bit width can be transferred at the time of data writing and reading, and efficient transfer of internal data can be realized.

According to the fourteenth aspect of the present invention, an internal data line is provided over a memory array, each memory row block is divided into a plurality of sub-banks, and the connection between the internal data line and the sense amplifier is made in sub-bank units. In addition, a write / read circuit is provided for each internal data line, and these write / read circuits are selectively connected to a global data bus in accordance with a data bit select signal. Can be transferred even in a bank configuration. When data transfer via the global data bus is performed between the write / read circuit and the input / output circuit, the data transfer is performed by separating the memory array from the write / read circuit. Only high-speed access is realized between the circuit and the internal input / output circuit.

According to the fifteenth aspect of the present invention, since the latch circuit for latching the data applied to each of the write / read circuits is provided, the connection between the latch circuit and the internal input / output circuit is ensured. It is only necessary to perform data transfer, and it is not necessary to consider data transfer between the sense amplifier and the write / read circuit having the longest propagation delay at the time of internal data write / read, and high-speed access is realized.

According to the sixteenth aspect of the invention, since the columns of the sub-bank are connected to the internal data lines only for a predetermined period in accordance with the sub-bank specifying signal, the memory array can be read / written during data access. The circuit can be separated, and high-speed data access is realized.

According to the seventeenth aspect, at the time of data writing, a write circuit included in a write / read circuit is activated to rewrite data to a subbank designated by a subbank specifying signal. Therefore, when writing data, it is sufficient to simply write data to the latch circuit.
The data latched in the latch circuit need only be rewritten in response to the write instruction signal. During this period, the data can be hidden by accessing another bank (another memory mat), thereby realizing high-speed access. Is done.

According to the eighteenth aspect, in response to the subbank activation signal, the precharge of the internal data line is stopped until the subbank coupled to the internal data line returns to the inactive state. Configuration,
It is possible to prevent the data in the selected sub-bank from being destroyed by the precharge.

According to the nineteenth aspect, since the sense amplifier is configured to be shared by the memory sub-blocks adjacent in the column direction, the area occupied by the sense amplifier can be reduced, and accordingly, the chip area can be reduced. Can be reduced.

[Brief description of the drawings]

FIG. 1 schematically shows a structure of an array portion of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing a configuration of a region between memory blocks shown in FIG. 1;

FIG. 3 is a diagram schematically showing another configuration of the inter-block area shown in FIG. 1;

FIG. 4 is a diagram more specifically showing a configuration of one memory sub-block of the semiconductor memory device shown in FIG. 1;

5 is a diagram schematically showing a configuration of two sub blocks of the memory sub block shown in FIG. 4;

FIG. 6 schematically shows a structure of a main part of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 7 schematically shows a structure of a portion related to four memory sub-blocks of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a modification of the second embodiment of the present invention.

9 is a diagram showing a configuration in which six memory sub blocks are arranged according to the configuration shown in FIG. 8;

FIG. 10 is a diagram showing the configuration shown in FIG. 9 in more detail;

11 is a diagram showing a configuration of a portion related to a sense amplifier in the configuration shown in FIG. 10;

12 is a diagram illustrating an example of a configuration of a control circuit that generates a control signal illustrated in FIG. 11;

FIG. 13 schematically shows a structure of a main part of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 14 schematically shows a configuration of a modification of the semiconductor memory device according to the third embodiment of the present invention.

FIG. 15 schematically shows a configuration of a second modification of the semiconductor memory device according to the third embodiment of the present invention.

FIG. 16 is a diagram showing a modification of the configuration shown in FIG.

FIG. 17 schematically shows an entire configuration of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 18A schematically shows a configuration of a row block selection signal generator of the semiconductor memory device shown in FIG.
FIG. 3B is a timing chart illustrating the operation of the circuit illustrated in FIG.

FIG. 19 is a diagram showing a modification of the fourth embodiment of the present invention.

20 is a timing chart showing the operation of the configuration shown in FIG.

21 is a diagram illustrating a specific configuration example of the latch illustrated in FIG. 19;

FIG. 22 schematically shows a command decoder that generates a row and column access instruction signal.

FIG. 23 schematically shows a structure of a main part of a semiconductor memory device according to a fifth embodiment of the present invention.

24 is a diagram schematically showing a configuration of a portion related to one bit of the main amplifier group shown in FIG. 23;

FIG. 25 schematically shows an entire configuration of a semiconductor memory device according to a sixth embodiment of the present invention.

26 is a diagram schematically showing a configuration of a control signal generator of the semiconductor memory device shown in FIG. 25;

FIG. 27 is a diagram showing a modification of the configuration shown in FIG. 25.

FIG. 28 schematically shows an entire configuration of a semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 29 is a drawing illustrating roughly configuration of a portion related to one memory sub-block of the semiconductor memory device illustrated in FIG. 28;

FIG. 30 schematically shows an entire configuration of a semiconductor memory device according to an eighth embodiment of the present invention.

FIG. 31 is a drawing illustrating roughly configuration of a portion related to one memory sub-block of the semiconductor memory device illustrated in FIG. 30;

FIG. 32 schematically shows an entire configuration of a semiconductor memory device according to a ninth embodiment of the present invention.

33A schematically shows a configuration of a portion related to one bit of the main amplifier group and the latch group shown in FIG. 32, and FIG. 33B shows a configuration of the main amplifier group and the latch group shown in FIG. FIG. 10 is a drawing schematically showing another configuration of a related portion of one bit.

FIG. 34 schematically shows a structure of a main part of a semiconductor memory device according to a modification of the ninth embodiment of the present invention.

FIG. 35 is a drawing illustrating roughly configuration of a row block selection signal and a data bit selection signal generation unit of the semiconductor memory device illustrated in FIG. 34;

36 is a diagram schematically showing another configuration of a row block, a column block, and a data bit block selection signal generator of the semiconductor memory device shown in FIG. 34.

FIG. 37 schematically shows an entire configuration of a semiconductor memory device according to a tenth embodiment of the present invention.

FIG. 38 is a drawing illustrating roughly configuration of a portion related to one memory mat of the semiconductor memory device illustrated in FIG. 37;

39 is a diagram more specifically showing a configuration of a main part of the semiconductor memory device shown in FIG. 38;

FIG. 40 is a timing chart showing an operation of the semiconductor memory device shown in FIGS. 38 and 39.

FIG. 41 is a diagram illustrating an effect of the semiconductor memory device shown in FIGS. 38 and 39;

FIG. 42 is a drawing illustrating roughly configuration of an internal data transfer unit of the semiconductor memory device illustrated in FIGS. 38 and 39;

FIG. 43 schematically shows a structure of an internal selection signal generator of a semiconductor memory device according to a tenth embodiment of the present invention.

FIG. 44 schematically shows a structure of a modification of the tenth embodiment of the present invention.

FIG. 45 is a diagram illustrating an operation in a modification of the tenth embodiment of the present invention.

FIG. 46 schematically shows a structure of a main I / O line pair precharge unit in a modification of the semiconductor memory device according to the tenth embodiment of the present invention.

FIG. 47 schematically shows an entire configuration of a semiconductor memory device according to an eleventh embodiment of the present invention.

48 is a diagram illustrating an example of a configuration of a latch circuit illustrated in FIG. 47;

FIG. 49 is a timing chart showing an operation of the semiconductor memory device according to the eleventh embodiment of the present invention.

FIG. 50 schematically shows a structure of an internal control signal generator of a semiconductor memory device according to an eleventh embodiment of the present invention.

FIG. 51 schematically shows a structure of a main I / O line pair precharge unit of a semiconductor memory device according to an eleventh embodiment of the present invention.

FIG. 52 schematically shows an array arrangement of a conventional semiconductor memory device.

FIG. 53 is a drawing illustrating roughly a more detailed configuration of one memory mat of the semiconductor memory device illustrated in FIG. 52;

FIG. 54 schematically shows an arrangement of internal data lines of the memory mat shown in FIG. 53.

FIG. 55 schematically shows another array arrangement of the conventional semiconductor memory device.

FIG. 56 is a drawing illustrating roughly configuration of an internal data transfer unit of the semiconductor memory device illustrated in FIG. 55;

FIG. 57 is a view illustrating a problem of the semiconductor memory device shown in FIG. 56;

[Explanation of symbols]

AR0-ARm + 1 Inter-block area, MSB memory sub-block, BDC block decode circuit, SDa,
SDb column select line, R # 0-R # n row block,
C # 0-C # m Column block, 1a-1c block decode circuit, SA1-SA4, SA sense amplifier circuit, SG1-SG4 Column select line, LS1-LS4
Local column select signal, MIOG main I / O line pair group, 1e-1j column block decode circuit, N1-N4
I / O select gate, MI / O0 to MI / O1028,
ZMI / O0 to ZMI / O1028 main I / O line,
MI / O0 to MI / O1028, ZMI / O0 to ZMI
/ O1028 Main I / O line, MIO0-MIO10
23 Main IO line pair, ARa, ARb area between blocks, BLP bit line pair, MSBaa to MSBbc, M
SBa-MSBf memory sub block, DECa0-D
ECb1 Block decode circuit, 1aa-1dd block decode circuit, B # 0-B # 3, BK # 0-BK
# 31 banks, SAGac-SAGbc sense amplifier group, NG1a-NG4b I / O gate group, BILG
a-BILGb Bit line isolation gate group, SAj sense amplifier, RBDEC row block decoder, BADE
R, BADEC bank decoder, LH1-LHn latch, GTT1-GTTn gate circuit, # 1- # n row block, SELR selector, 6 column decoder,
6a-6h Column decode circuit, 8a-8d Main amplifier group, MIOGa-MIOGd Main I / O line pair group, LSa, LSb Local column select signal, 8a
1, 8ar, 8bl, 8br, 8cl, 8cr, 8d
l, 8dr Main amplifier group, LSal, Lsar, L
Sbl, LSbr Local column select signal, 25a
a, 25ab, 25ba, 25bb block decode circuit, 30a-30d latch group, 32 column group selection circuit, 35 global data bus, 37a, 37
b, 38a, 38b latch, 18a main amplifier,
18b write driver, 32a, 32b column group selection circuit, MTa to MTb memory mat, SBS0 to SBS0
SBS31 Sub-bank selection circuit, 62 write / read circuit, 64 data bit selection circuit, 60 global data bus, 66 Y decoder, SB # 0 to SB # 31
Sense amplifier band, SSG sub-block selection gate, 6
2p main amplifier, 62w write driver, 64a
~ 64x Data bit select gate, 66a ~ 66x
Y decode circuit, G1 to G4 sub block select decode circuit, SSG sub block select gate, 95a to 9
5b Latch circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8242 G11C 11/34 371K H01L 27/10 681E

Claims (19)

[Claims] 1. A memory array having a plurality of memory cells each arranged in a matrix and having a plurality of memory blocks arranged in a row and column direction, an external region of the memory array and between memory blocks A plurality of column select lines arranged in each of the regions extending along the column direction and transmitting a column select signal; arranged in the column direction over the memory block, and arranged in the column direction of the memory block; A plurality of internal data lines grouped corresponding to a column block constituted by memory blocks arranged in line, and arranged according to the memory block, each according to a column selection signal on the column selection line A semiconductor memory device, comprising: a column selection circuit for selecting a column of a corresponding memory block and connecting to a corresponding group of internal data lines. 2. Each of the column selection circuits is arranged in an area outside the memory array or an area between memory blocks,
A decoding circuit for generating a column selection signal for a corresponding memory block in accordance with a row block designating signal designating a memory block arranged in a row direction and a column selection signal on a column selection line arranged in a corresponding region , Claim 1
13. The semiconductor memory device according to claim 1. 3. The decoding circuit according to claim 2, wherein each of the decoding circuits is shared by a column selection circuit provided for memory blocks arranged on both sides along a row direction of a corresponding region.
13. The semiconductor memory device according to claim 1. 4. The semiconductor memory device according to claim 1, wherein each of said column selection circuits is distributed on both sides in a column direction of a corresponding memory block. 5. The memory block arranged at least along the row direction constitutes a bank, and each bank can drive a row of memory cells to a selected state independently of each other; 2. The semiconductor memory device according to claim 1, wherein said selection circuit performs a column selection operation when an activation of a bank designation signal for specifying a bank is performed. 6. A memory cell array which is arranged on one side in a column direction of the memory array so as to correspond to the external area of the memory array and the area between memory blocks, and activates a column selection signal in accordance with a given column address signal to thereby activate a corresponding column. 2. The semiconductor memory device according to claim 1, further comprising a plurality of column decode circuits generated on a selection line. 7. The plurality of column decode circuits are grouped corresponding to a column block, and each of the plurality of column decode circuits is activated according to a column block designating signal for specifying a column block from the plurality of column blocks. 7. The semiconductor memory device according to claim 6, wherein a given address signal is decoded to generate a column selection signal. 8. Each of the decoding circuits includes a plurality of decoders provided on both sides along a row direction of a corresponding memory block and transmitting column selection signals in directions opposite to each other.
The semiconductor memory device according to claim 2. 9. The semiconductor memory device according to claim 8, wherein said plurality of decoders drive a common column selection line for a corresponding memory block. 10. The memory block is divided into a plurality of groups in a row direction, and the plurality of decoders are provided corresponding to each of the plurality of groups and transmit a column selection signal to the corresponding group. The semiconductor memory device according to claim 8. 11. The decoding circuit is arranged for every predetermined number of memory blocks in the region between the memory blocks in the column direction, and the arrangement position of the decoding circuit is different in the region between adjacent memory blocks.
13. The semiconductor memory device according to claim 1. 12. A device provided corresponding to the column block,
A plurality of read circuits for amplifying data on internal data lines provided corresponding to a corresponding column block at the time of activation, wherein each of the read circuits corresponds to an internal data line of a corresponding internal data line group A plurality of read amplifiers provided, and in response to a data group specifying signal specifying a group of the internal data lines, read data of the read amplifier provided for the group specified by the data group specifying signal. 2. The semiconductor memory device according to claim 1, further comprising a data selection circuit for reading data onto a global data bus provided separately from the data lines. 13. A device provided corresponding to the column block,
A plurality of write / read circuits for transmitting / receiving data to / from internal data lines provided corresponding to a corresponding column block at the time of activation are provided. Each of the write / read circuits is connected to an internal data line of a corresponding group. A plurality of read amplifiers provided correspondingly and a write driver for transmitting write data are provided. In response to a data group specifying signal for specifying a group of internal data lines, a data group specified by the data group specifying signal is provided. 2. A data selection circuit according to claim 1, further comprising a data selection circuit for activating data transfer between a write / read circuit provided for the group and a global data bus provided separately from said internal data line. Semiconductor storage device. 14. A plurality of banks each having a plurality of memory cells arranged in a matrix and capable of independently selecting and driving a memory cell row to a non-selected state. Is divided into a plurality of sub-banks, a plurality of internal data lines arranged extending along the column direction over the plurality of banks, a bank addressed according to a bank / sub-bank address signal specifying the bank and the sub-bank Sub-bank selection circuit for connecting the memory cell columns of the sub-banks to the plurality of internal data lines in parallel, and an internal circuit provided corresponding to each of the plurality of internal data lines and divided into a plurality of groups, A plurality of write / read circuits for exchanging data with data lines and a plurality of the plurality of write / read circuits in accordance with a group address signal; From write / read circuit includes a data selection circuit connected to the global data bus by selecting a write / read circuit of the designated group, the semiconductor memory device. 15. Each of the plurality of write / read circuits includes:
15. The semiconductor memory device according to claim 14, further comprising a latch circuit for latching applied data. 16. The semiconductor memory device according to claim 14, wherein said sub-bank selection circuit connects a column of a specified sub-bank to an internal data line for a predetermined period in response to a sub-bank specifying signal. 17. In response to a data write instruction provided together with a subbank specifying signal, a write circuit included in the write / read circuit is activated to switch to a subbank specified by the subbank specifying signal. 15. The semiconductor memory device according to claim 14, further comprising control means for writing data via the memory. 18. A control device for responding to a subbank activation signal, further comprising control means for stopping precharging of the internal data line until a subbank coupled to the internal data line returns to an inactive state. 15. The semiconductor memory device according to 14. 19. A plurality of sense amplifier groups each including a plurality of sense amplifiers provided corresponding to the column and arranged at least between adjacent memory blocks in the column direction and shared between the adjacent memory blocks. The semiconductor memory device according to claim 3, further comprising: