JPH02249195A - Dynamic semiconductor memory - Google Patents

Abstract

PURPOSE:To perform the readout and the write of data simultaneously and in parallel by providing plural sense amplifiers for write, and a column decoder for write which issues output to control a transfer gate for write. CONSTITUTION:A sense amplifier 2 for readout is provided at a terminal part on one side of bit line arrangement in a memory cell array 1, and the sense amplifier 4 for write is provided at the terminal part on the other side. In a data line, output data lines OL and the inverse of OL connected to the sense amplifier 2 for readout and input data lines IL and the inverse of IL connected to the sense amplifier 4 for write are provided separately. Furthermore, the column decoder 3 for readout which controls the transfer gate between the sense amplifier 2 for readout and the output data lines OL and the inverse of OL, and the column decoder 5 for write which controls the transfer gates Q2 and Q3 between the sense amplifier 4 for write and the input data lines IL and the inverse of IL are provided. In such a way, it is possible to perform the readout and the write of the data simultaneously and in parallel.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a dynamic semiconductor memory device (DR) using a memory cell consisting of a transistor/capacitor.
Regarding AM).

(Prior Art) Among MOS type semiconductor memory devices, DRAMs are becoming more highly integrated and faster. Improvement in the switching speed of transistors due to miniaturization has greatly contributed to increasing the speed of DRAMs. Taking advantage of the high speed of these fine transistors, not only the access time but also the cycle time of DRAM has continued to be shortened. There is almost no doubt that it will happen.

As shown in FIGS. 6(a) and 6(b), the cycle time that determines the operating frequency of a DRAM is determined by the cycle time during 1-bit random access, that is, during a read cycle or a write cycle. Its minimum value is specified. This value is t RC
(Random Read or Write Cycle
e Till1e). Apart from this, the DRAM is capable of a read/write mode (read or modify write mode) in which reading and writing are performed in one cycle, as shown in FIG. 6(C). In this case, the cycle time t RWC (Read-Wri
te Cycle Time) is longer than the above-mentioned tRC. The reason for this will be explained below with reference to FIGS. 4 and 5.

Figure 4 shows the core circuit and read/write circuit in a conventional DRAM.
The main part of the intermediate buffer that controls writing is shown. Each bit line pair of the memory cell array is connected to column selection signal lines C3Lo, C3L+, . . . which are output lines of the column decoder.
Transfer gate Q 1+ where ... is input to the gate
It is connected to input/output lines DQ and DQ shared by each column via Q 21 . An intermediate buffer 1 for controlling reading/writing is connected to the ends of these input/output lines DQ and DQ, which run long on the chip in parallel with the word line WL. The read data is stored in this intermediate buffer 1.
1 to the read data lines RD, RD, and then output to the outside via an output buffer (not shown). Here, a CMOS flip-flop type sense amplifier 13 is shown as a read data amplifier within the intermediate buffer 11. Also, input/output line DQ.

A DQ precharge circuit 12 is also shown.

Input data input to a write buffer (not shown) is transferred to write data lines WD, WD, logically summed with a write control signal WGT, and transferred to input/output lines DQ, DQ. .

FIG. 5 is a timing diagram of the circuit of FIG. 4 during a read/write cycle. It is assumed that the data read from the memory cell is "0" and the data written to the memory cell is "11".

When external control signal RAS falls and a row address is taken into the chip, one word line is selected accordingly. Continue to use sense amplifier activation signal SAN
, S, AP are activated, and the memory cell data is amplified by the sense amplifier and then latched. Next, as the external control signal CAS falls, a column address is taken into the chip, one column selection signal line C5L is selected according to this, and the data latched by the sense amplifier is transferred to the input/output lines DQ and DQ. be transferred. Human output line DQ,
After sufficient data has been transferred to DQ, the activation signal DQS of the intermediate buffer 11 rises, and the intermediate buffer 11 amplifies and latches the data. At the same time, input/output lines DQ, DQ and read data line RD are connected by transfer gates Q, ,Q.

RD and write data lines WD, WD are separated. After this, if the write operation has been activated by the fall of the external control signal WE, the write control signal WGT of the intermediate buffer 11 falls, the write data is transferred to the input/output lines DQ, DQ of the core circuit, and the bit Writing is done to the memory cell via the line.

As mentioned above, from the read/write cycle,
In other words, the sum of the time T1 from when the column selection signal line C8L is selected until the intermediate buffer 1 is activated and the time T2 until the intermediate buffer 11 completely latches the read data is activated over T, +T. It will be necessary to delay. This is the reason why tRWc>tRC.

(Problems to be Solved by the Invention) As described above, in current DRAMs, the cycle time (tRWC) in read/write mode is equal to the cycle time (tRWC) in random read/write mode.
RC), and is usually about 1.25 (a).Therefore, when the read/write mode is frequently used, there is a problem in that the performance of the entire system is significantly degraded.

An object of the present invention is to provide a DRAM which solves these problems and reduces the cycle time in read/write mode.

[Configuration of the Invention (Means for Solving the Problems)] A DRAM according to the present invention has a sense amplifier for reading at one end of a bit line arrangement of a memory cell array, and a sense amplifier for writing at the other end. A sense amplifier is provided. A switching MO3 transistor is arranged between the read sense amplifier and the bit line. The data lines are separately provided as an output data line connected to a read sense amplifier and an input data line connected to a write sense amplifier. Furthermore, a read column decoder that controls a transfer gate between a read sense amplifier and an output data line, and a write column decoder that controls a transfer gate between a write sense amplifier and an input data line are provided.

(Function) According to the configuration of the present invention, data reading and writing can be performed simultaneously and in parallel in the read/write mode. In other words, after the selected word line is turned on and the data of the memory cell is transferred to the bit line, the switching M, 08I-transistor between the read sense amplifier and the bit line is activated at any time before the sense amplifier is activated. Turn off.

Thereafter, the read sense amplifier is activated and data in the selected column can be read out via the output data line. At this time, the read sense amplifier is disconnected from the bit line, so at the same time, data is sent via the input data line, new data is written to the selected column using the write sense amplifier, and the remaining It is possible to rewrite in the column.

Therefore, according to the present invention, the cycle time in read/write mode can be made the same as the cycle time in random read/write mode.
M is obtained.

(Example) The present invention will be explained in detail below.

FIG. 1 is an equivalent circuit showing the main part configuration of DRA M of one embodiment. Multiple word lines WL and multiple bit line pairs B
A memory cell array 1 configured by arranging memory cells of one transistor/one capacitor at the intersection of L and BL is no different from the conventional one. At the right end of this memory cell array 1, there are switching MO3 transistors Q, (Qll, Q12) for dividing the bit line into two at a certain time.
．． Q13Q14. ), and a read sense amplifier 2 connected to the bit line pair via this MOS transistor is provided. This read sense amplifier 2 has a transfer gate Q 2 (Q 21 + Q 22 + Q
23°Q24. ...) through the output data lines OL, O
Connected to L. An intermediate buffer 6 for amplifying and latching the data read out from the output data lines OL and OL is provided, and the output of the intermediate buffer 6 is sent to the output buffer 7.
It is designed to be output externally via .

A write sense amplifier 4 connected to the bit line pair is provided on the left side of the memory cell array 1. This write sense amplifier 4 has a transfer gate Q 3 (Q 31 + Q 32 +
Q33. Q3. l+...) are connected to the human power data lines IL, IL. Input data line IL
, IL are configured such that data taken in from the outside by an input buffer array is transferred via a write buffer 8.

FIG. 2 shows a specific configuration example of a memory cell array and sense amplifier sections on both sides of the memory cell array for one column. The read sense amplifier 2 is a dynamic sense amplifier (so-called NM
OS sense amplifier). On the other hand, the write sense amplifier 4 consists of two n-channel MO8 transistors Q.
It is configured by combining an NMOS sense amplifier using 511Q52 and a PMOS sense amplifier using two p-channel MOS transistors Q6I and Q62. The read sense amplifier 2 is for read only and does not require amplification on the high level side, so it is only an NMOS sense amplifier.

The read/write mode operation of the DRAM thus configured will now be described with reference to FIG.

The external control signal RAS falls and a row address is taken into the chip, and one word line and a dummy word line are selected and rise accordingly at time tl. As a result, the data in the cell of the selected row address and the dummy cell Φ data are transferred to the bit line pair. Everything up to this point is the same as before. After this, in the conventional system, the sense amplifier is activated, but in this embodiment, before that, at time t2, the gate input of the switching MO8 transistor Q1 between the bit line pair BL of the memory cell array 1 and the read sense amplifier 2 is activated. The signal ψ9 becomes “L” level, and this MOS
The transistor turns off.

Thereafter, the read sense amplifier 2 and the write sense amplifier 4 start sensing operations in response to activation signals SAN and SAP. Then, as the external control signal CAS falls, the column address is taken in and the column system is activated. That is, the data of the column selected by the column selection signal line RC3L, which is the output line of the read column address decoder 3, is transferred from the read sense amplifier 2 to the intermediate buffer 6 via the output data lines OL and OL, and is amplified. and read out. At the same time, the column selection signal WC3, which is the output line of the write column address decoder 4,
For the column selected by L, the input buffer 9. Data transferred to the input data lines IL, IL via the write buffer is amplified by the write sense amplifier 4, and newly written to the memory cell via the corresponding bit line.

For the remaining columns, the write sense amplifier 4 and the input data lines IL are disconnected, and the read data is rewritten by the write sense amplifier 4. In this way, the read operation and the write operation are performed simultaneously and in parallel, and the read/write cycle is completed.

As described above, according to this embodiment, the cycle time t RWC in the read/write cycle can be made equal to the cycle time t RC in the random read/write cycle. Further, in this embodiment, only an NMOS sense amplifier is used as the read sense amplifier 2. This is because the read sense amplifier is not used for rewriting, which reduces the number of sense amplifier elements and minimizes the increase in chip area.

The present invention is not limited to the above embodiments. For example, a PMOS sense amplifier can be combined with the read sense amplifier. Further, DRAM is not limited to general-purpose applications, and can be similarly applied to field memories and video memories.

[Effects of the Invention] As described above, according to the present invention, a read/write system that can read and write data simultaneously and in parallel can be used.
A high performance DRAM having multiple modes can be provided.

[Brief explanation of drawings]

FIG. 1 shows a DRAM according to an embodiment of the present invention; FIG. 2 shows a specific configuration example of its memory cell array and sense amplifier section; and FIG. 3 shows an explanation of the read/write φ mode operation of the DRAM. Fig. 4 is a diagram showing the main part configuration of a conventional DRAM, Fig. 5 is a timing diagram for explaining the operation of the DRAM, and Figs. 6 (a) to (c) are diagrams of a conventional DRAM. It is an explanatory diagram of various operation cycles of. 1...Memory cell array, 2...Sense amplifier for reading, 3...Column decoder for reading, 4...Sense amplifier for writing, 5...Column decoder for writing, 6...Intermediate Buffer, 7... Output buffer, 8
...Write buffer, 9...Input buffer, Ql
(Q ll+ Q 12+ 013+ Q 14
+...)...Switching MO8 transistor,
Q2 (Q2., Q2□+ Q231Q24....
), Q, (Q31.Q32.Q=3.Q-4,...)
...transfer '-1, OL, OL...output data line, IL, IL...input data line. Figure 4 (a) Lee F cycle (b) Write cycle (C) Read/write capital

Claims (4)

[Claims] (1) Multiple dynamic memory cells are arranged in a matrix, with multiple pairs of bit lines that exchange signals with each memory cell, and multiple word lines that are arranged orthogonally to the bit lines and select memory cells. a plurality of read sense amplifiers connected via switching MOS transistors to one end of a bit line pair in each column of the memory cell array, and nodes of these read sense amplifiers connected to a read transfer transfer circuit. a data output line connected through a gate; a read column decoder that outputs an output to control the read transfer gate; and a plurality of read column decoders connected to the other end of the bit line pair of each column of the memory cell array. a write sense amplifier; an input data line to which the nodes of these write sense amplifiers are connected via a write transfer gate; and a write column decoder that outputs an output to control the write transfer gate. A dynamic semiconductor memory device comprising: (2) A switching MO at one end of a bit line pair of a memory cell array in which dynamic memory cells are arranged.
A read sense amplifier is provided through an S transistor, and a write sense amplifier is provided at the other end. The switching MOS transistors are connected to input data lines through transfer gates, and during active operation, after the data of the memory cell selected by the row address is transferred to the bit line pair, the switching MOS transistor is controlled to be off, and then the switching MOS transistor is turned off for reading. The read transfer gate and write transfer gate selected by the column address and write column address are turned on at the same time, and data reading and data writing are performed in parallel at the same time.
A dynamic semiconductor memory device having a write mode. (3) The read sense amplifier is constituted by a dynamic flip-flop formed by cross-connecting the drains and gates of two MOS transistors of the same conductivity type. The dynamic semiconductor memory device described above. (4) The write sense amplifier is a dynamic flip-flop formed by cross-connecting the drains and gates of two MOS transistors of the first conductivity type, and a dynamic flip-flop formed by cross-connecting the drains and gates of two MOS transistors of the second conductivity type. 3. The dynamic semiconductor memory device according to claim 1, wherein the dynamic semiconductor memory device comprises a dynamic flip-flop formed by connecting the dynamic flip-flops.