KR102339652B1 - Display Panel and Display Device having the Same - Google Patents

Abstract

A display panel according to the present invention includes a gate line, a first log wiring unit, a second log wiring unit, and a third log wiring unit. The gate lines are arranged in the display area. The first log wiring unit receives a gate timing control signal and a gate voltage for generating a gate pulse provided to the gate line, and is connected to an input pad of the flexible film on which the gate drive IC is mounted. The second log wiring is branched from the first log wiring and connected to the first pad of the flexible film. The third log wiring is branched from the second log wiring and connected to the second pad of the flexible film.

Description

A display panel and a display device including the same

The present invention relates to a display panel and a display device including the same.

A display device is applied to various information devices and office devices as a transmission medium of visual information. A cathode ray tube or a cathode ray tube, which is the most widely used display device, has problems in terms of weight and volume. Many types of flat panel displays that can overcome these limitations of cathode ray tubes are being developed. Flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), and organic light emitting diodes (OLEDs). etc.

In a flat panel display, data lines and gate lines are arranged to cross each other, and pixels are arranged in a matrix form. A video data voltage to be displayed is supplied to the data lines, and a gate pulse is sequentially supplied to the gate lines. A video data voltage is supplied to pixels of a display line to which a gate pulse is supplied, and video data is displayed while all display lines are sequentially scanned by the gate pulse.

The gate pulse is generated by the gate drive IC receiving gate signals such as a gate timing control signal, a gate high voltage, and a gate low voltage from a timing controller.

Gate drive ICs mounted on the display panel in the COG method are also interconnected by a line on glass (LOG) method in which signal lines are mounted on the display panel.

The gate signals passing through the log wirings are delayed due to the resistance of the log wirings, and the gate high voltage and the gate low voltage are also voltage drops. In particular, in recent years, as the size of the display panel increases, the length of the log lines increases, and accordingly, the gate signals passing through the log lines are also greatly affected by resistance. Since the gate drive ICs located between the log wirings are affected by different resistance values between the respective gate drive ICs, the gate low voltage of the gate pulse output from the gate drive ICs is different. Accordingly, there is a problem in that the luminance of each horizontal line of the display panel is distorted by gate low voltages of different magnitudes.

An object of the present invention is to provide a display panel having improved gate signal delay and gate voltage drop caused by resistance of log wiring, and a display device including the same.

A display panel according to the present invention includes a gate line, a first log wiring unit, a second log wiring unit, and a third log wiring unit. The gate lines are arranged in the display area. The first log wiring unit receives a gate timing control signal and a gate voltage for generating a gate pulse provided to the gate line, and is connected to an input pad of the flexible film on which the gate drive IC is mounted. The second log wiring is branched from the first log wiring and connected to the first pad of the flexible film. The third log wiring is branched from the second log wiring and connected to the second pad of the flexible film.

According to the present invention, the delay of the gate signal and the voltage drop of the gate voltage can be reduced by connecting the log wiring units that transmit the gate signal in parallel. Accordingly, it is possible to improve the occurrence of a dim phenomenon in the horizontal line direction due to the gate voltage difference.

1 is a view showing a display device according to the present invention.
2 is a diagram schematically illustrating a display device according to a comparative example;
3 is a diagram illustrating resistance values between log wirings according to positions of gate drive ICs according to Comparative Examples and Examples;
4 is a view showing the magnitude of a gate low voltage according to positions of gate drive ICs according to Comparative Examples and Examples;
5 is a diagram schematically illustrating log wiring resistance of a display device according to an embodiment of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a view showing a display device according to the present invention.

Referring to FIG. 1 , the display device according to the present invention includes a printed circuit board 101 , a data flexible film 200 , a gate flexible film 300 , and a display panel 400 .

The timing controller 100 is mounted on the printed circuit board 101 . The timing controller 100 receives timing signals such as vertical/horizontal synchronization signals (Vsync, Hsync), a data enable signal (DE), and a clock signal (CLK) to receive the data drive IC 210 , and the gate drive IC 310 . ) to generate control signals for controlling the operation timing. These control signals include a gate timing control signal and a data timing control signal. Also, the timing controller 200 supplies digital video data RGB to the data flexible film 210 .

The gate timing control signal generated by the timing controller 200 includes a gate start pulse GSP, a gate shift clock signal GSC, and a gate output enable signal GOE.

The gate start pulse GSP is applied to the gate drive IC 310 to indicate a start line from which a scan is started so that the first gate pulse is generated. The gate shift clock signal GSC is a clock signal for shifting the gate start pulse GSP. The shift register of the gate ICs 310 shifts the gate start pulse GSP at the rising edge of the gate shift clock signal GSC. The gate output enable signal GOE is commonly input to each gate drive IC 310 . The gate drive IC 310 outputs a gate pulse during the low logic period of the gate output enable signal GOE, that is, from immediately after the falling time of the pulse to immediately before the rising time of the next pulse.

The data timing control signal generated by the timing controller 100 includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal. (Source Output Enable, SOE), etc. The source start pulse SSP indicates a start pixel in a line on which data is to be displayed. The source sampling clock SSC instructs a latch operation of data in the data drive IC 210 based on a rising or falling edge.

A data drive IC 210 is mounted on the flexible data film 200 , and a data input line 211 and a data output line 231 are disposed. A gate signal input wiring group 221 is formed on any one of the data flexible films 200 , for example, the first data flexible film 200 .

The data drive IC 210 receives a data timing control signal and image data from the timing controller 100 through the data input line 211 . The data drive IC 210 generates a data voltage based on the image data and outputs the data voltage to the data line DL through the data output line 231 .

The gate signal input wiring group 221 transmits a gate timing control signal, a gate high voltage, a gate low voltage, and the like from the timing controller 100 to the first log wiring unit LOG1 .

A gate drive IC 31 is mounted on each gate flexible film 300 , and a gate signal wiring part 321 is formed.

The gate drive IC 310 receives a gate timing control signal, a gate high voltage VGH, and a gate low voltage VGL from the gate signal wiring unit 321 , and generates a gate pulse based thereon. The gate drive IC 310 outputs a gate pulse through a gate output pad.

The display panel 400 may be divided into a display area 401 in which pixels are arranged, and a non-display area 411 in which various signal lines are disposed when positioned outside the display area. Data pads extending from the data line DL and gate pads extending from the gate line GL are positioned in the non-display area 411 .

In the non-display area where the gate flexible film 300 is located, the first log wiring unit LOG1 to the third log wiring unit for providing the gate pulse generated by the gate drive IC 310 to the gate line GL of the display area (LOG3) is located. The first to third log wiring units LOG3 are wirings formed on the display panel in a line-on-glass method. The first to third log wirings LOG3 may include a plurality of log wirings, and each signal wiring transmits a gate timing control signal, a gate high voltage VGH, and a gate low voltage VGL. The gate timing control signal includes signals such as a gate start pulse GSP, a gate shift clock signal GSC, and a gate output enable signal GOE. The first to third log interconnections LOG1 to LOG3 may be formed of a gate metal layer in the same manner as the gate lines GL.

The first log wiring unit LOG1 is connected to the gate signal input wiring unit 221 , and is vertically formed along a side surface to which the gate flexible film 300 is bonded in the non-display area 411 .

In a region where the first log interconnection LOG1 and the gate lines GL intersect on a plane like region “A”, the first log interconnection part LOG1 is designed to be positioned on a different metal layer from the gate lines GL. can be Alternatively, the first log wiring part LOG1 is formed in a disconnected state where the gate lines GL are formed in the "A" region, and the disconnected first log wiring part LOG1 is formed in an insulating layer using a bridge formed in the insulating layer. can be connected As such, in the region “A”, the first log wiring unit LOG1 and the gate lines GL cross each other without being electrically connected by using a known technique.

Also, even when the first log wiring units LOG1 to the third log wiring units LOG3 intersect or each signal line intersects within the log wiring unit, the same structure as in area “A” may be used.

The second log wiring part LOG2 is branched from the first log wiring part LOG1 and is connected to the first pad 351 of the gate flexible film 310 . The third log wiring part LOG3 is branched from the first log wiring part LOG1 and is connected to the second pad 352 of the gate flexible film 310 . The first pad 351 and the second pad 352 are connected to the gate signal line 321 .

The gate timing control signal, the gate high voltage VGH, and the gate low voltage VGL provided from the timing controller 100 are respectively transmitted through the first log wiring units LOG1 to the third gate log wiring units LOG1 to LOG3 . of the gate drive IC 310 . Since the second log wiring unit LOG2 and the third log wiring unit LOG3 are branched from the first log wiring unit LOG1 and connected to the gate flexible film 300 , the first log wiring unit LOG1 to the second log wiring unit LOG1 . The three log wiring units LOG3 are connected to each gate flexible film 300 in a parallel structure. As described above, since the first log wiring unit LOG1 to the third log wiring unit LOG3 form a parallel structure, the voltage drop of the gate signals can be reduced.

Looking at this:

2 is a diagram illustrating resistances of log wirings in a display device according to a comparative example in which the first log wiring unit LOG1 is not present. In FIG. 2 , since the log wirings L1 and the gate signal wirings L2 formed on the gate flexible film 300 are connected in series with each other, a voltage drop occurs due to resistance of the gate signals. The gate resistive components are proportional to the lengths of the log wiring and the gate signal wiring. 2 shows the resistance value of the log wiring when the resistance of the log wiring to the first pad of the first gate drive IC (GIC1) is 50 and the resistance of the log wiring between each gate drive IC (GIC) is 100. It is shown in a schematic diagram. That is, the gate signal output from the data flexible film is affected by a resistance of 50 up to the gate drive IC (GIC1). And up to the second gate drive IC (GIC2) is affected by a resistance of 150, and up to the third gate drive IC (GIC3) is affected by a resistance of 250. As described above, in the comparative example, the gate signal passing through the gate drive IC (GIC) passes through the gate drive IC (GIC) and the log line L1, and is affected by resistance proportional to the signal path as shown in FIG. 3 . Therefore, as shown in FIG. 4 , the gate high voltage VGH and the gate low voltage VGL of the comparative example are greatly reduced while passing through the gate drive IC GIC.

In contrast, in the display device according to the embodiment of the present invention, the first path of the first log wiring LOG1 and the second path from the second log wiring unit LOG2 to the third log wiring unit LOG3 are parallel to each other. is connected to Accordingly, in the display device of the present invention, the gate signal receives less resistance than the comparative example through one path. For example, as shown in FIG. 5 , the resistance component between the gate flexible films 300 according to the embodiment of the present invention is reduced compared to the comparative example. The voltage level changes of the gate high voltage VGH and the gate low voltage VGL according to the resistive component and the resistive component between the gate flexible films 300 according to an embodiment of the present invention are as shown in FIGS. 3 and 4 . .

As described above, in the display device according to an embodiment of the present invention, the voltage drop of the gate signals can be reduced by configuring the paths for transmitting the gate signals in parallel. According to an embodiment of the present invention, deterioration of image quality displayed on a display panel may be improved by reducing a voltage drop of the gate signals.

This is explained as follows.

The gate low voltage VGL maintains the pixel voltage charged in the liquid crystal cell in the gate high voltage VGH section until the next pixel voltage is charged. When the gate low voltage VGL is distorted, the charged pixel voltage is changed. . As shown in FIG. 4 , when the voltage difference of the gate low voltage VGL between the gate flexible films 300 is large, the luminance difference of the pixels corresponding to the gate lines GL occurs according to the respective gate drive ICs. do.

In contrast, in the embodiment of the present invention, since the difference in resistance between the gate flexible films 300 is not large as shown in FIG. 4 , the block dim phenomenon appearing in the display panel 100 can be improved.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (5)

a gate line arranged in the display area;
a first log wiring unit connected to the gate signal input wiring unit and receiving a gate timing control signal and a gate voltage for generating a gate pulse provided to the gate line;
a second log wiring unit branched from the first log wiring and connected to a first pad of the flexible film on which the gate drive IC is mounted; and
and a third log wiring branched from the first log wiring and connected to the second pad of the flexible film,
a first path of the first log wiring unit and a second path from the second log wiring unit to the third log wiring unit are connected in parallel to each other;
The first log wiring unit, the second log wiring unit, and the third log wiring unit transmit the gate timing control signal and the gate voltage to the gate drive IC.
The method of claim 1,
The first to third log wiring portions include a gate high voltage line and a gate low voltage line.
a timing controller generating a gate timing control signal for generating a gate pulse;
a gate line receiving the gate pulse and providing the gate pulse to a pixel;
a first log wiring unit connected to the gate signal input wiring unit to receive a gate voltage and the gate timing control signal;
a second log wiring unit branched from the first log wiring and connected to a first pad of the flexible film on which the gate drive IC is mounted;
a third log wiring branched from the first log wiring and connected to the second pad of the flexible film;
the flexible film in which a gate signal wiring unit connecting the second log wiring unit and the third log wiring unit is arranged; and
and the gate drive IC mounted on the gate flexible film and configured to generate a gate pulse using the gate signal provided from the gate signal wiring unit;
a first path of the first log wiring unit and a second path from the second log wiring unit to the third log wiring unit are connected in parallel to each other;
The first log wiring unit, the second log wiring unit, and the third log wiring unit transfer the gate timing control signal and the gate voltage to the gate drive IC.
4. The method of claim 3,
The gate line and the first log wiring part are disposed on different layers.
4. The method of claim 3,
The flexible film includes a gate signal line connecting the second log wiring unit and the third log wiring unit, and the gate drive IC receives the gate signal from the gate signal line.

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