KR101308463B1 - Liquid Crystral Display Device - Google Patents

Abstract

In the liquid crystal display device, an object of the present invention is to solve the problem of deterioration in image quality and generation of an afterimage when the distribution of the common voltage is not uniform in the display panel.

In order to achieve the above object, the liquid crystal display device according to the present invention,

In addition to the first common line formed to be parallel to the gate line, a second common line electrically connected to the first common line and parallel to the data line, and a common voltage delay prevention part for preventing a delay of the common voltage are included. .

As described above, the liquid crystal display according to the present invention provides an effect of preventing the distribution of the common voltage from being uneven by the line resistance by applying a common voltage through the dummy terminal provided in the data driver IC to the second common line. do.

Common voltage, common line, resistance

Description

Liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device in which the display quality is improved by making the common voltage distribution in the display panel uniform.

With the development of the information society, it is required to develop a new image display device that improves disadvantages such as heavy weight and large volume of the conventional CRT (Cathode Ray Tube).

Accordingly, various flat panel displays, such as liquid crystal display devices (LCDs), organic light emitting diodes (OLEDs), plasma panel display devices (PDPs), surface-conduction electron-emitter display devices (SEDs), and the like. Devices are attracting attention.

Among them, a liquid crystal display device which is widely used from a large TV screen to a display screen of a small mobile phone is one of the most representative flat panel display devices.

A liquid crystal display device arranges a liquid crystal material having dielectric anisotropy and refractive index anisotropy between two electrodes, forms an electric field between the two electrodes, and then controls an amount of light transmitted by controlling the intensity of the electric field to display an image to be displayed. Implement

That is, the liquid crystal display device is not a self-luminous display device that emits light by itself, but is a light receiving type display device that implements an image by receiving light from a separately provided light source.

In general, the liquid crystal display receives white light from a separately provided light source, and implements colors using three colors of red, green, and blue.

As described above, two electrodes for driving a liquid crystal are generally composed of a pixel electrode connected to a thin film transistor and receiving a voltage corresponding to an image signal, and a common electrode supplied with a common voltage, and formed between the two electrodes. The liquid crystal is driven by the electric field.

However, in the conventional liquid crystal display device, since only one or two common voltage input terminals are provided to supply a common voltage to the display panel, when the size of the display panel is enlarged, the distribution of the common voltage in the display panel is uniform due to resistance or the like. There was a problem that did not go away.

As described above, when the distribution of the common voltage is not uniform in the display panel, there is a problem in that image quality deteriorates and afterimage occurs.

In order to solve such a problem, an object of the present invention is to provide a liquid crystal display device having a uniform distribution of common voltage in a display panel.

In order to achieve the above object, the liquid crystal display device according to an embodiment of the present invention,

A display panel having a display area and a non-display area surrounding the display area, a gate line and a data line intersecting each other on the display panel to define a plurality of pixel areas, and a first common line formed to be parallel to the gate line; A second common line parallel to the data line and intersecting the first common line, and a plurality of data pad portions formed by gathering pad lines including a data pad line and a common pad line in the non-display area; A first data driver IC connected to the remaining pad parts except for the data pad parts disposed at both ends of the data pad part, a second data driver IC connected to the data pad parts disposed at both ends of the data pad part; Is provided in at least one of the first data driver IC to the outside A first common voltage input terminal for supplying a common voltage to the second common line, and a plurality of delay prevention patterns for supplying a common voltage control signal to the first and second common lines to prevent a delay of the common voltage; And a common voltage delay prevention unit provided, wherein the plurality of delay prevention patterns have at least one resistor and a capacitor having different values, and the values of the resistors and capacitors included in the plurality of delay prevention patterns are the common voltage. The plurality of delay prevention patterns may separately supply the common voltage control signal generated in consideration of the delay amount of the common voltage to each of the first and second data driver ICs.

In addition, the liquid crystal display according to the exemplary embodiment of the present invention is configured such that the first common line and the second common line are electrically connected to each other.

As described above, the liquid crystal display according to the exemplary embodiment of the present invention supplies the common voltage through the second common line formed parallel to the data line in addition to the first common line formed parallel to the gate line, thereby providing a common voltage in the display panel. Make the distribution of.

In the liquid crystal display device according to the embodiment of the present invention,

As described above, the common voltage is provided not only through the common line formed to be parallel to the gate line but also through the common line formed to be parallel to the data line, thereby providing an effect of improving the non-uniformity of the common voltage in the display panel.

Next, specific embodiments will be described for the practice of the present invention.

1 is a plan view showing the configuration of a liquid crystal display according to a first embodiment of the present invention.

The liquid crystal display shown in FIG. 1 has a display panel 10 having a display area 12 and a non-display area 14 surrounding the display area 12 and the display panel 10 so as to cross each other. A thin film transistor (not shown) formed at an intersection of the gate line 22 and the data line 24 to define the plurality of pixel regions 20, and the gate line 22 and the data line 24. A pixel electrode connected to the transistor and formed in the pixel region 20, a first common line 30 formed in parallel with the gate line 22, and parallel to the data line 24, and in addition to the first common line; A plurality of data pads including a second common line 32 formed to cross the line 30 and pad lines including a data pad line 52 and a common pad line 54 in the non-display area 14. Arranged at both ends of the unit 50 and the data pad unit 50 A first data driver IC 60 connected to the remaining pad portions except for the data pad portion, a second data driver IC 62 connected to the data pad portions disposed at both ends of the data pad portion, and the first data driver. A first common voltage input terminal 64 provided at at least one of the ICs 60 to supply a common voltage to the second common line 32, a common voltage generator 102 generating the common voltage, It characterized in that it comprises a common voltage delay prevention unit 200 for preventing the delay of the common voltage.

For reference, hereinafter, the same reference numerals refer to the same components.

The display panel 10 is formed by bonding two transparent substrates to face each other, and a liquid crystal layer between the two substrates.

Scan signals input from the outside through the gate line 22 are sequentially supplied to the display panel 10.

The data line 24 is formed to intersect the gate line 22 and a gate insulating layer (not shown) to define a plurality of pixel regions 20, and is input from the outside through the data line 24. The data signal to be supplied is supplied to the display panel 10.

The display area 12 includes a plurality of pixel areas 20 arranged in a matrix form, and each pixel area is configured such that any one of red, green, and blue colors corresponds to each other.

The thin film transistor (21 in FIG. 2) includes a gate electrode (25 in FIG. 2) branched from the gate line 22, a semiconductor layer (23 in FIG. 2) formed on the gate electrode, and the data line. And a source electrode (27 in FIG. 2) branched and formed on an end of the semiconductor layer and a drain electrode (28 in FIG. 2) formed to face the source electrode, and connected to the drain electrode to form the pixel region ( A pixel electrode (29 of FIG. 2) formed on the substrate 20 may be further included.

For example, the pixel electrode may be formed of a transparent conductive layer such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The thin film transistor is controlled by a scan signal supplied through the gate line. When the thin film transistor is turned on, a data signal input through a source electrode is charged in the pixel electrode.

The common voltage generator 102 generates a common voltage and supplies the common voltage to the display panel 10. The common voltage from the common voltage generator 102 is supplied to and controlled by the common voltage delay prevention unit 200 to prevent a delay, and then is supplied to the display panel 10. The common voltage controlled by the common voltage delay prevention unit 200 is supplied to the first and second common lines 30 and 32 of the display panel 10 via the first and second data drivers 60 and 62. . In this case, the common voltage generator 102 and the common voltage delay prevention unit 200 may be mounted on a printed circuit board (PCB).

The common voltage delay prevention unit 200 includes a plurality of delay prevention patterns 2001 to 200n to prevent a delay of the common voltage. For example, the plurality of delay prevention patterns 2001 to 200n form first to nth delay prevention patterns 2001 to 200n to correspond to the first and second data driver ICs 60 and 62, respectively. The first to nth delay prevention patterns 2001 to 200n separately supply the common voltage control signal generated in consideration of the delay amount of the common voltage to each of the first and second data driver ICs 60 and 62. In other words, the first to n-th delay prevention patterns 2001 to 200n have a signal delay amount due to an increase in the area of the display panel 10 or a signal delay due to a length of a supply line connected to the common voltage generator 102. In consideration of the amount, a common voltage control signal is generated. To this end, each of the first to nth delay prevention patterns 2001 to 200n includes resistors R1 to Rn and capacitors C1 to Cn. That is, the first to nth delay prevention patterns 2001 to 200n may adjust the delay amount according to the values of the resistors R1 to Rn and the capacitors C1 to Cn included in the first to nth delay prevention patterns 2001 to 200n. In detail, each of the first to nth delay prevention patterns 2001 to 200n may include the resistors R1 to Rn and capacitors included in the first to nth delay prevention patterns 2001 to 200n. The value of (C1 to Cn) should be small. In other words, the values of the resistors R1 to Rn and the capacitors C1 to Cn included in the first to nth delay prevention patterns 2001 to 200n correspond to positions where the delay amount of the common voltage is large. The values of C1 to Cn and capacitors C1 to Cn become small. Equation 1 is as follows.

R1, C1> R2, C2> R3, C3 .........> Rn, Cn

As described above, each of the first to nth delay prevention patterns 2001 to 200n includes the resistors R1 to Rn and the capacitors C1 to Cn using the above equation. Accordingly, the first to n-th delay prevention patterns 2001 to 200n separately supply the common voltage control signals to the first and second data driver ICs 60 and 62 according to the delay amount of the common voltage. It is possible to supply a uniform common voltage to 10).

The first common line 30 is formed parallel to the gate line 22 and is formed of the same layer as the gate line 22.

In addition, a common voltage input from the outside through the first common line 30 is supplied to the display panel.

The second common line 32 is formed to be parallel to the data line 24, and a common voltage input from the outside is also supplied to the display panel through the second common line 32.

In the liquid crystal display according to the first exemplary embodiment of the present invention, the second common line 32 is formed of the same layer as the data line 24 so that the first common line 30 and the gate insulating layer (not shown). Is formed to intersect with each other.

In addition, the second common line 32 and the first common line 30 may be formed to be electrically connected to each other so that the common voltage is stably supplied over the entire display panel.

For example, patterning is performed to simultaneously cover the first contact hole 70 exposing a part of the first common line 30 and the second contact hole 71 exposing a part of the second common line 32. It will be possible to allow the first common line and the second common line to be electrically connected to each other through the first connection unit 80.

The first connector 80 may be formed of the same layer as the pixel electrode.

The data pad section 50 includes a plurality of data pad lines 52, one end of which is connected to the data line and supplies a data signal to the data line. In addition, the data pad part 50 may further include a common pad line 54 having one end electrically connected to the second common line 32 to supply a common voltage to the second common line.

The data pad line and the common pad line are both formed of the same layer as the data line.

That is, since the second common line 32 is formed of the same layer as the common pad line 54, the second common line 32 is formed as one line connected to each other.

The first data driver IC 60 is connected to the remaining data pad portions except for the data pad portions disposed at both ends of the data pad portion, and the second data driver IC 62 is connected to the data pad portions disposed at both ends.

At least one of the first data driver ICs 60 includes a first common voltage input terminal 64 for inputting a common voltage, and the first common voltage input terminal 64 includes a common pad line 54. Is connected to and inputs a common voltage to the second common line 32.

The first common voltage input terminal 64 may be formed using the dummy terminal 63 provided in the first data driver IC 60, as shown in FIG. 2.

At least one of the second data driver ICs 62 may also include a second common voltage input terminal 66 for inputting a common voltage.

The second common voltage input terminal 66 is provided in the second data driver IC 62 to be connected to the first common line connection pattern 90 that electrically connects the plurality of first common lines 30. do.

In addition, the first common line connection pattern 90 may be formed on the left side of the display panel as shown in FIG. 1, or may be formed on the right side of the display panel or simultaneously formed on the left side and the right side.

The first common line connection pattern 90 may be formed of the same layer as the data line. In this case, the contact hole 73 exposing a part of the first common line and a part of the first common line connection pattern are exposed. The first common line connection pattern and the first common line are electrically connected to each other through the second connection part 82 patterned to simultaneously cover the contact holes 74.

The second connection part is preferably formed of the same layer as the pixel electrode.

Although not shown, the first common line connection pattern 90 may be formed of the same layer as the gate line.

As described above, the liquid crystal display according to the first exemplary embodiment of the present invention supplies a common voltage through the second common line formed in a direction parallel to the data line, thereby supplying a more uniform common voltage to the entire display panel. It becomes possible.

3 is a diagram illustrating a pixel area of an in-plane switching mode liquid crystal display according to a first embodiment of the present invention.

In the in-plane switching mode liquid crystal display according to the first embodiment of the present invention, as shown in FIG. 3, the first contact hole 70 and the second common line 32 exposing a part of the first common line 30. And a first connection part 80 patterned to simultaneously cover the second contact hole 71 exposing a portion of the second contact hole 71.

In addition, the common electrode 31 is electrically connected to the common line branching portion 33 branched from the first common line 30 to the pixel region through the contact hole 72b and the second common line 32. It extends to cover the third contact hole 72a formed in the upper portion and is connected to the second common line 32 at the same time.

That is, it will be possible for the first common line 30 and the second common line 32 to be electrically connected to each other through the common electrode 31.

Next, a liquid crystal display according to a second exemplary embodiment of the present invention will be described.

In the liquid crystal display device according to the second embodiment of the present invention,

A display panel having a display area and a non-display area surrounding the display area, a gate line and a data line intersecting the display panel to define a plurality of pixel areas, and an intersection of the gate line and the data line. A thin film transistor formed on the substrate and a pixel electrode connected to the thin film transistor, a first common line formed to be parallel to the gate line, and parallel to the data line and intersecting the first common line. A plurality of data pad parts including a second common line, pad lines including a data pad line and a common pad line in the non-display area, and the remaining pad parts except for data pad parts disposed at both ends of the data pad parts. A first data driver IC connected to the data pad unit A second data driver IC connected to a data pad unit disposed at both ends thereof, a first common voltage input terminal provided in at least one of the first data driver ICs to supply a common voltage to the second common line, and A second common line connection pattern electrically connecting the common pad line and the second common line to each other, a common voltage generation unit generating the common voltage, and a common voltage delay preventing unit preventing a delay of the common voltage; .

4 is a plan view of main parts of a liquid crystal display according to a second exemplary embodiment of the present invention.

As shown in FIG. 4, the common voltage delay prevention unit 200 includes a plurality of delay prevention patterns 2001 to 200n, and forms first to nth delay prevention patterns 2001 to 200n, for example. The first to nth delay prevention patterns 2001 to 200n are individually connected to the first data driver IC 60 to supply a common voltage control signal to each of the first data driver ICs 60. Specifically, the common voltage control signal from the first to nth delay prevention patterns 2001 to 200n may include the first common voltage input terminal 64 and the first to nth terminals provided in each of the first data driver ICs 60. It is connected to the output line of the delay prevention patterns 2001-200n, respectively, and is supplied.

The common pad line 54 is formed of the same layer as the data line 24 and the second common line 32, and the second common line connection pattern 92 is formed of the same layer as the gate line.

The second common line 32 and the second common line connection pattern 92 may include a contact hole 79 exposing a portion of the second common line 32 and a contact exposing a portion of the second common line. It is electrically connected to each other through a third connection portion 83 patterned to cover the hole 76b at the same time.

The common pad line 54 and the second common line connection pattern 92 may include a contact hole 75 exposing a portion of the common pad line and a contact hole 76a exposing a portion of the second common line. It is electrically connected to each other via a fourth connection portion 84 patterned to cover at the same time.

The third connector 83 and the fourth connector 84 are preferably formed of the same layer as the pixel electrode.

In addition, when the second common line 32 is formed of the same layer as the data line, although not illustrated, in this case, the connection pattern formed to cover the second common line connection pattern 92 and the contact hole and the contact hole. It is possible to be electrically connected through.

In addition, in the liquid crystal display according to the second exemplary embodiment of the present invention, as shown in FIG. 4, one common common line connection pattern 92 is provided in each of the first common data driver ICs 60 adjacent to each other. It is characterized in that it is connected to the voltage input terminal 64 at the same time.

That is, one second common line connection pattern 92 may be shared by neighboring first data driver ICs.

Also, in the liquid crystal display according to the second exemplary embodiment of the present invention, in the region where the second common line connection pattern 92 and the data line 24 overlap, the data line 24 and the second line as shown in FIG. 5. It is preferable that the semiconductor layer 23 is interposed between the common line connection pattern 92.

5 is a cross-sectional view illustrating a region where a data line and a second common line connection pattern overlap.

For reference, reference numeral 26, which is not described, indicates a gate insulating film.

As such, when the floating semiconductor layer 23 is interposed between the data line and the second common line connection pattern, the semiconductor layer serves as an insulator and the second common line connection pattern 92 to which a common voltage is supplied. Since the parasitic capacitance formed between the data lines 24 to which the data signal is supplied is reduced, the phenomenon in which the distribution of the common voltage becomes uneven due to the delay phenomenon can be improved.

In addition, as shown in FIG. 5, when the data line 24 and the semiconductor layer 23 are simultaneously etched, the semiconductor layer 23 is exposed to a wider width according to the difference in the etching ratio, so that the data line 24 is exposed. It provides an effect that can be prevented from being disconnected by this sudden step change.

The semiconductor layer 23 is formed of the same layer as the semiconductor layer of the thin film transistor.

Also, in the liquid crystal display according to the second exemplary embodiment of the present invention, as illustrated in FIG. 6, the data line includes a first region having a first line width w1 and a second line width w2 smaller than the first line width. The first region may include a region in which the second common line connection pattern 92 and the data line overlap each other.

That is, since the region overlapping the second common line connection pattern in the data line is the most affected by the delay caused by parasitic capacitance, the data line is delayed by forming the data line so that the line width of the portion is larger than other portions. The phenomenon in which the distribution of the common voltage is uneven due to the delay phenomenon can be improved.

In the liquid crystal display according to the second exemplary embodiment of the present invention, parts except for the common pad line, the data line, and the second common line described above are the liquid crystal display according to the first exemplary embodiment of the present invention. Since it is the same as, it will be replaced by the above description.

Next, a liquid crystal display according to a third exemplary embodiment of the present invention will be described.

In the liquid crystal display according to the third embodiment of the present invention,

A display panel having a display area and a non-display area surrounding the display area, a gate line and a data line intersecting the display panel to define a plurality of pixel areas, and an intersection of the gate line and the data line. A thin film transistor formed on the substrate and a pixel electrode connected to the thin film transistor, a first common line formed to be parallel to the gate line, and parallel to the data line and intersecting the first common line. A plurality of data pad parts including a second common line, pad lines including a data pad line and a common pad line in the non-display area, and the remaining pad parts except for data pad parts disposed at both ends of the data pad parts. A first data driver IC connected to the data pad unit A second data driver IC connected to a data pad unit disposed at both ends thereof, a first common voltage input terminal provided in at least one of the first data driver ICs to supply a common voltage to the second common line, and A second common line connection pattern electrically connecting the common pad line and the second common line to each other, a common voltage generating unit generating the common voltage, and a common voltage delay preventing unit preventing the common voltage delay phenomenon; ,

The second common line connection pattern is electrically connected to at least one common pad line and the second common line, and is integrally formed.

7 is a plan view of main parts of a liquid crystal display according to a third exemplary embodiment of the present invention.

As shown in FIG. 7, the common voltage delay prevention unit 200 includes a plurality of delay prevention patterns 2001 to 200n, and forms first to nth delay prevention patterns 2001 to 200n, for example. The plurality of delay prevention patterns 2001 to 200n are connected to at least one delay prevention pattern to each of the first data drivers 60 to supply at least one common voltage control signal to each of the first data driver ICs 60.

In addition, the second common line connection pattern is formed integrally so that the difference between the minute common voltage input through each of the first common voltage input terminal 64 and the second common voltage input terminal 66 can be canceled. To provide.

In the liquid crystal display according to the third exemplary embodiment of the present invention, parts except for the second common line and the data line and the second common line connection pattern described above are according to the second exemplary embodiment of the present invention. Since it is the same as the liquid crystal display device, the above description will be replaced.

Next, a liquid crystal display according to a fourth exemplary embodiment of the present invention will be described.

In the liquid crystal display according to the fourth embodiment of the present invention,

A display panel having a display area and a non-display area surrounding the display area, a gate line and a data line intersecting the display panel to define a plurality of pixel areas, and an intersection of the gate line and the data line. A thin film transistor formed on the substrate and a pixel electrode connected to the thin film transistor, a first common line formed to be parallel to the gate line, and parallel to the data line and intersecting the first common line. A plurality of data pad parts including a second common line, pad lines including a data pad line and a common pad line in the non-display area, and the remaining pad parts except for data pad parts disposed at both ends of the data pad parts. A first data driver IC connected to the data pad unit A second data driver IC connected to a data pad unit disposed at both ends of the center, a first common voltage input terminal provided in at least one of the first data driver ICs to supply a common voltage to the second common line, and A second common line connection pattern electrically connecting the common pad line and the second common line to each other, and a common voltage delay prevention unit preventing the common voltage delay phenomenon;

The plurality of second common line connection patterns may be separated from each other, and each of the second common line connection patterns may be electrically connected to one or more common pad lines and the second common line.

8 is a plan view of main parts of a liquid crystal display according to a fourth exemplary embodiment of the present invention.

As shown in FIG. 8, the liquid crystal display according to the fourth exemplary embodiment of the present invention is formed by separating the plurality of second common line connection patterns, so that each first data driver IC can separately input the common voltage. Do. In this way, when the common voltages can be input individually, the circuit tuning can be performed more smoothly.

The common voltage delay prevention unit 200 includes a plurality of delay prevention patterns 2001 to 200n, for example, to form first to nth delay prevention patterns 2001 to 200n. The plurality of delay prevention patterns 2001 to 200n are connected to at least one delay prevention pattern to each of the first data drivers 60 to supply at least one common voltage control signal to each of the first data driver ICs 60.

In addition, in the liquid crystal display according to the fourth embodiment of the present invention, as shown in FIG. 9, the second common line 32 and the data line 24 may be alternately formed.

As such, when the data line 24 and the second common line 32 are alternately formed, the electric field is symmetrically formed in the display panel.

That is, the entire pattern is formed symmetrically so that the distribution of the electric field is more uniform over the entire display panel.

In the liquid crystal display according to the fourth embodiment of the present invention, portions except for the second common line and the data line and the second common line connection pattern described above are the second embodiment of the present invention. Since it is the same as the liquid crystal display according to the description, it will be replaced by the above description.

Next, a liquid crystal display according to a fifth exemplary embodiment of the present invention will be described.

In the liquid crystal display according to the fifth embodiment of the present invention,

A display panel having a display area and a non-display area surrounding the display area, a gate line and a data line intersecting the display panel to define a plurality of pixel areas, and an intersection of the gate line and the data line. A thin film transistor formed on the substrate and a pixel electrode connected to the thin film transistor, a first common line formed to be parallel to the gate line, and parallel to the data line and intersecting the first common line. A plurality of data pad parts including a second common line, pad lines including a data pad line and a common pad line in the non-display area, and the remaining pad parts except for data pad parts disposed at both ends of the data pad parts. A first data driver IC connected to the data pad unit A second data driver IC connected to a data pad unit disposed at both ends thereof, a first common voltage input terminal provided in at least one of the first data driver ICs to supply a common voltage to the second common line, and A metal pattern formed on the other side of the region where the data pad part is formed in the non-display area and electrically connecting the second common line to each other, a common voltage generator generating the common voltage, and a delay phenomenon of the common voltage; It characterized in that it comprises a common voltage delay prevention unit.

10A is a plan view illustrating an example of a liquid crystal display according to a fifth exemplary embodiment of the present invention.

As shown in FIG. 10A, the liquid crystal display according to the fifth exemplary embodiment of the present invention further includes a metal pattern formed on the other side of the region where the data pad part is formed in the non-display area to electrically connect the second common line to each other. This provides an effect of making the distribution of the common voltage more uniform in the display panel.

The metal pattern 94 may be formed of the same layer as the second common line 32.

In FIG. 10A, both the metal pattern and the second common line are formed of the same layer as the data line.

10B is a plan view illustrating another example of the liquid crystal display according to the fifth exemplary embodiment of the present invention.

As shown in FIG. 10B, a metal pattern formed on the other side of the region where the data pad part is formed and electrically connecting the second common line to each other and a first common line connection pattern provided on both left and right sides of the display panel are simultaneously included. It will be possible to make the distribution of the common voltage more uniform.

In addition, as shown in FIG. 11, the metal pattern may be formed in a multilayer structure having a first pattern 94a formed of the same layer as the data line and a second pattern 94b formed of the same layer as the gate line.

Although not shown, a passivation film made of an insulating layer is interposed between the first pattern 94a and the second pattern 94b.

The first pattern 94a and the second pattern 94b may include contact holes 77 exposing a portion of the first pattern 94a and contact holes 78 exposing a portion of the second pattern 94b. At the same time, they are electrically connected to each other through a fifth connection portion 86 patterned to cover.

The contact holes 77 and 78 and the fifth connection portion 86 may be formed in plural to be multi-contact.

As such, when the metal pattern is configured in the form of a multilayer, it may be possible to further reduce the resistance to make the distribution of the common voltage more uniform.

Next, a liquid crystal display according to a sixth embodiment of the present invention will be described.

In the liquid crystal display according to the sixth embodiment of the present invention,

A display panel having a display area and a non-display area surrounding the display area, a gate line and a data line intersecting the display panel to define a plurality of pixel areas, and an intersection of the gate line and the data line. A thin film transistor formed on the substrate and a pixel electrode connected to the thin film transistor, a first common line formed to be parallel to the gate line, and parallel to the data line and intersecting the first common line. A plurality of data pad parts including a second common line, pad lines including a data pad line and a common pad line in the non-display area, and the remaining pad parts except for data pad parts disposed at both ends of the data pad parts. A first data driver IC connected to the data pad unit A second data driver IC connected to a data pad unit disposed at both ends thereof, a first common voltage input terminal provided in at least one of the first data driver ICs to supply a common voltage to the second common line, and A metal pattern formed on the other side of the region where the data pad part is formed in the non-display area and electrically connecting the second common line to each other, a common voltage generator generating the common voltage, and a delay phenomenon of the common voltage; And a common voltage delay prevention unit, a gate driver IC for supplying a gate control signal to the gate line, and a LOG type signal line group for transmitting the gate control signals supplied to the gate driver IC.

12 is a plan view of a liquid crystal display according to a sixth embodiment of the present invention.

As shown in Fig. 12, in the liquid crystal display according to the sixth embodiment, the gate driver IC 302 and the LOG type signal line group 300 connected thereto are formed in the non-display area 14. The LOG signal line group 300 is composed of a gate metal layer similarly to the gate line 22. As described above, although the resistance value of the LOG signal line group 300 is proportional to the line length, the signal delay amount is generated as it moves away from the PCB. However, as shown in FIG. 13, the first and second data driver ICs 60 and 62 may be used. The display quality can be improved by forming a plurality of delay preventing patterns 2001 to 200n to correspond to each other and supplying a uniform common voltage. As described with reference to FIG. 1, the plurality of delay preventing patterns 2001 to 200n have the same function and the same effect, and thus description thereof will be omitted.

FIG. 13A illustrates a distribution of common voltages in a conventional display panel, and FIG. 13B illustrates distributions of common voltages in a liquid crystal display according to a first exemplary embodiment of the present invention.

As can be seen from FIGS. 13A and 13B, it can be seen that the distribution of the common voltage in the liquid crystal display according to the first exemplary embodiment of the present invention becomes more uniform than in the related art.

In particular, in the case of a wide panel having a 16: 9 aspect ratio for video, when the common voltage is supplied only through the first common line parallel to the gate line as the panel becomes longer in the gate line direction, a delay may occur. The uneven distribution of common voltage was severe.

In the liquid crystal display according to the exemplary embodiment of the present invention, the common voltage is supplied through the second common line formed parallel to the data line together with the first common line formed parallel to the gate line, thereby improving the distribution of the common voltage. Becomes remarkable.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those skilled in the art.

1 is a plan view of a liquid crystal display device according to a first embodiment of the present invention.

2 is a plan view of a data driver IC.

3 is a plan view of an in-plane switching mode liquid crystal display device according to a first embodiment of the present invention;

4 is a plan view showing an example of a liquid crystal display according to a second embodiment of the present invention.

5 is a cross-sectional view of a region in which a data line and a second common line connection pattern overlap in the liquid crystal display according to the second exemplary embodiment of the present invention.

6 is a plan view showing another example of the liquid crystal display according to the second embodiment of the present invention.

7 is a plan view of a liquid crystal display according to a third embodiment of the present invention.

8 is a plan view showing an example of a liquid crystal display according to a fourth embodiment of the present invention.

9 is a plan view showing another example of the liquid crystal display according to the fourth embodiment of the present invention.

10A is a plan view showing an example of a liquid crystal display according to a fifth embodiment of the present invention.

Fig. 10B is a plan view showing another example of the liquid crystal display device according to the fifth embodiment of the present invention.

Fig. 11 is a plan view showing a case where a metal pattern has a multilayer structure in the liquid crystal display according to the fifth embodiment of the present invention.

12 is a plan view showing another example of the liquid crystal display according to the sixth embodiment of the present invention.

Fig. 13A is a distribution chart of common voltages in a display panel in the conventional liquid crystal display device.

13B is a distribution diagram of a common voltage in a display panel in the liquid crystal display according to the first embodiment of the present invention.

≪ Brief Description of Drawings &

10: display panel 12: display area

14: non-display area 20: pixel area

22: gate line 24: data line

21 thin film transistor 23 semiconductor layer

25 gate electrode 26 gate insulating film

27 source electrode 28 drain electrode

29 pixel electrode 30 first common line

32: second common line 31: common electrode

50: data pad portion 52: data pad line

54: common pad line 60: first data driver IC

62: second data driver IC 64: first common voltage input terminal

66: second common voltage input terminal 80: first connection portion

70, 71, 72a, 72b, 73, 74, 75, 76a, 76b, 79: contact hole

82: second connecting portion 83: third connecting portion

84: fourth connection portion 86: fifth connection portion

90: first common line connection pattern 92: second common line connection pattern

300: LOG signal line group 302: gate driver IC

Claims (8)

A display panel having a display area and a non-display area surrounding the display area; Gate lines and data lines formed on the display panel to cross each other to define a plurality of pixel areas; A first common line formed to be parallel to the gate line; A second common line parallel to the data line and formed to intersect the first common line; A plurality of data pad units formed in the non-display area by pad lines including a data pad line and a common pad line; A first data driver IC connected to the remaining pad parts except for the data pad parts disposed at both ends of the display panel; Second data driver ICs connected to data pad units disposed at both ends of the display panel; A first common voltage input terminal provided in at least one of the first data driver ICs to supply a common voltage supplied from the outside to the second common line; It includes a common voltage delay prevention unit having a plurality of delay prevention patterns for supplying a common voltage control signal to the first and second common lines to prevent a delay of the common voltage, The plurality of delay prevention patterns have at least one resistor and a capacitor having different values, and the values of the resistors and capacitors included in the plurality of delay prevention patterns vary according to the delay amount of the common voltage. The plurality of delay prevention patterns may separately supply the common voltage control signal generated in consideration of the delay amount of the common voltage to each of the first and second data driver ICs. The method of claim 1, And a second common voltage input terminal provided in at least one of the second data driver ICs to supply a common voltage. delete delete delete The method of claim 1, The values of the resistors and the capacitors included in the plurality of delay prevention patterns correspond to the positions where the delay amount of the common voltage is large. delete The method of claim 6, The plurality of delay prevention patterns are connected to at least one delay prevention pattern to each of the first and second data driver ICs to supply at least one common voltage control signal to each of the first and second data driver ICs. Liquid crystal display.

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