KR102512962B1 - Display device and method for driving the same - Google Patents

Abstract

An exemplary embodiment of the present invention is a display panel including a plurality of pixel areas defined in a display area and at least one gate line corresponding to the pixel areas arranged in a horizontal direction among the plurality of pixel areas; first and second gate drivers disposed on both sides and sequentially supplying gate signals to a plurality of gate lines included in the display panel, and a gate control signal for controlling driving timing of the first and second gate drivers; A display device including a timing controller for supplying Here, each of the first and second gate drivers includes a shift register including a plurality of stages corresponding to the plurality of gate lines and sequentially connected to each other, a shift register corresponding to each gate line and corresponding to a gate signal of each gate line. A detection level shifter outputs a detection signal, and a detection buffer disposed between the detection level shifter and each stage and transmitting the detection signal to each stage based on a gate detection enable signal among the gate control signals. .

Description

Display device and its driving method {DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

The present invention relates to a display device including a gate driver for supplying a gate signal to a gate line of a display panel and a method for driving the same.

Display devices are applied to various electronic devices such as TVs, mobile phones, laptops, and tablets. Accordingly, research is being conducted to develop thinning, lightening, and low power consumption of display devices.

Representative examples of the display device include a liquid crystal display device (LCD), a plasma display panel device (PDP), a field emission display device (FED), and an electro luminescence display device. Display device: ELD), Electro-Wetting Display device (EWD), Organic Light Emitting Display device (OLED), and the like.

Such a display device generally includes a display panel including a display area on which an image is displayed, and a driving unit for driving the display panel.

The display panel includes a plurality of pixel areas corresponding to a plurality of pixel areas defined in the display area, and at least one horizontal signal line corresponding to each horizontal line of the pixel areas arranged in parallel in a horizontal direction among the plurality of pixel areas. and at least one vertical signal line corresponding to each vertical line made up of pixel areas arranged in parallel in a vertical direction among a plurality of pixel areas.

Here, the at least one vertical signal line may include a data line supplying a data signal to each pixel area.

The at least one horizontal signal line may include a gate line supplying a gate signal corresponding to an addressing period for supplying a data signal to each pixel area.

Alternatively, when the display panel includes a plurality of organic light emitting diodes corresponding to a plurality of pixel areas and includes a circuit for compensating the characteristics of each organic light emitting element or the characteristic of a driving thin film transistor connected to each organic light emitting element in series. , At least one horizontal signal line may include two or more gate lines corresponding to two or more different gate signals.

Exemplarily, the two or more gate lines include a first gate line supplying a gate signal corresponding to an addressing period, a second gate line supplying a gate signal corresponding to an initial period for initializing each pixel area, and each pixel area. A third gate line for supplying a gate signal corresponding to an emission period for supplying driving current to the organic light emitting device may be included.

The driving unit includes a gate driver supplying each gate signal to at least one gate line corresponding to each horizontal line, a data driver supplying data signals to each data line, and a timing controller controlling driving timing of the gate driver and the data driver. can include

On the other hand, since the resistance of each signal line increases as the area of the display device increases, signal distortion occurs due to the resistance of each signal line, and thus, there is a problem in that luminance deviation for each region may occur.

To prevent this, the gate driver may include first and second gate driver units disposed on both sides of the horizontal line and supplying gate signals to both sides of each gate line.

However, due to malfunction or damage of at least one of the first and second gate drivers, different signals may be supplied to both sides of each gate line. In this case, there are problems in that image quality may deteriorate due to difficulty in supplying data signals normally, and image display may be stopped due to occurrence of a short-circuit defect between power sources. As such, there is a problem in that secondary defects are caused due to malfunction or damage of at least one of the first and second gate driving units.

An object of the present invention is to provide a display device capable of preventing secondary defects due to malfunction or breakage of at least one of first and second gate driving units and a driving method thereof.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention not mentioned above can be understood by the following description and will be more clearly understood by the examples of the present invention. It will also be readily apparent that the objects and advantages of the present invention may be realized by means of the instrumentalities and combinations indicated in the claims.

An example of the present invention is a display panel including a plurality of pixel areas defined in a display area and at least one gate line corresponding to the pixel areas arranged in a horizontal direction among the plurality of pixel areas, and both sides of the gate line. first and second gate drivers arranged on the display panel and sequentially supplying gate signals to a plurality of gate lines included in the display panel, and supplying a gate control signal for controlling driving timing of the first and second gate drivers. A display device including a timing controller for Here, each of the first and second gate drivers includes a shift register including a plurality of stages corresponding to the plurality of gate lines and sequentially connected to each other, a shift register corresponding to each gate line and corresponding to a gate signal of each gate line. A detection level shifter outputs a detection signal, and a detection buffer disposed between the detection level shifter and each stage and transmitting the detection signal to each stage based on a gate detection enable signal among the gate control signals. .

When the detection signal is transmitted, the shift register sequentially shifts the detection start signal among the gate control signals to the plurality of stages. Further, the shift register transmits a response of the sensing start signal to the timing controller when the sensing start signal is shifted to the last stage among the plurality of stages. At this time, the timing controller corresponds to an abnormality detection mode for detecting whether or not the first and second gate driver have an abnormality, and the gate of the gate control signal to the supply-side gate driver, which is one of the first and second gate driver. supplying a start signal and at least one gate clock signal, supplying the sensing start signal to the other sensing-side gate driver, and receiving a response of the sensing start signal from the shift register of the sensing-side gate driver; If the period corresponding to the response time of the detection start signal is within a predetermined threshold period, the gate start signal and the at least one gate clock signal to the supply-side gate driver corresponding to a display mode for displaying an image on the display panel. supply

The shift registers of the first and second gate drivers sequentially output gate pulses by the plurality of stages based on a gate start signal and at least one gate clock signal among the gate control signals. Here, each of the first and second gate drivers correspond to the respective stages, and a supply level shifter outputting a gate signal based on the gate pulse of each stage, and disposed between the supply level shifter and each of the gate lines. and a supply buffer for transferring the gate signal to each of the gate lines based on a gate supply enable signal among the gate control signals.

Another example of the present invention is a display panel including a plurality of pixel areas defined in a display area and at least one gate line corresponding to the pixel areas arranged in a horizontal direction among the plurality of pixel areas, It includes first and second gate drivers disposed on both sides of the gate line and supplying gate signals to both sides of the gate line, and timing controllers supplying gate control signals for controlling driving timing of the first and second gate drivers. A method for driving a display device for The method of driving the display device may include setting an abnormality detection mode for detecting whether or not the first and second gate driving units are abnormal, and either one of the first and second gate driving units corresponding to the abnormality detection mode. supplying a gate start signal and at least one gate clock signal among the gate control signals to a gate driver on the phosphorus supply side, and supplying the sensing start signal to a gate driver on the sensing side, which is the other one; Receiving the response of the start signal, and determining that the supply-side gate driver is normal if the period corresponding to the response point of the detection start signal is within a predetermined threshold period; Correspondingly, supplying the gate start signal and the at least one gate clock signal to a gate driver determined to be normal among the first and second gate driver units.

The step of supplying the gate start signal and at least one gate clock signal to a supply-side gate driver, which is one of the first and second gate drivers, and the step of determining that the supply-side gate driver is normal are performed by the first gate driver It is performed for each case where the supply-side gate driver is selected and when the second gate driver is selected as the supply-side gate driver.

The method of driving the display device further includes transmitting, by the sensing-side gate driver, a response of the sensing start signal to the timing controller before receiving the sensing start signal response. Here, in the step of transmitting the response of the sensing start signal to the timing controller by the sensing-side gate driver, the sensing level shifter of the sensing-side gate driver corresponds to the gate signal of each gate line included in the display panel, and the outputting a sensing signal having a swing width smaller than that of the gate signal, wherein the sensing buffer of the sensing-side gate driver transmits the sensing signal to a shift register of the sensing-side gate driver based on a gate sensing enable signal among the gate control signals; Step, when the shift register of the sensing-side gate driver receives the sensing signal, sequentially shifting the sensing start signal to a plurality of stages corresponding to a plurality of gate lines included in the display panel, and the sensing start and transmitting a response of the detection start signal to the timing controller when the signal is shifted to the last stage among the plurality of stages.

The method of driving the display device further includes supplying the gate signal to each of the gate lines by the supply-side gate driver before outputting the detection signal. Here, in the step of supplying the gate signal to each gate line by the supply-side gate driver, the shift register of the supply-side gate driver operates by the plurality of stages based on the gate start signal and the at least one gate clock signal. Sequentially outputting gate pulses, outputting gate signals corresponding to the gate pulses of the respective stages by the supply level shifter of the supply-side gate driver and having a larger swing width than the gate pulses, and the supply buffer of the supply-side gate driver and supplying the gate signal to each of the gate lines based on a gate supply enable signal among the gate control signals.

The method of driving the display device includes determining the supply-side gate driver as abnormal when the sensing start signal is not received from the sensing-side gate driver within the threshold period, and the first and second display modes corresponding to the display mode. The method may further include supplying a buffer disable signal to the gate driver determined to be faulty among the gate driver units, and stopping driving of the supply buffer and the detection buffer of the supply side gate driver based on the buffer disable signal.

A display device according to an embodiment of the present invention includes first and second gate drivers supplying gate signals to both sides of each gate line included in a display panel, and each of the first and second gate drivers includes a plurality of gates. A shift register including a plurality of stages corresponding to a line, a detection level shifter outputting a detection signal corresponding to a gate signal of each gate line, and a gate detection enable signal by a timing controller to transmit a detection signal to each stage. Contains the detection buffer. Here, the shift register sequentially shifts a plurality of stages when the detection signal is transmitted to each stage based on the detection start signal by the timing controller, and transmits the detection start signal to the timing controller when shifted to the last stage.

Accordingly, one of the first and second gate drivers is driven as a supply-side gate driver for supplying gate signals to each gate line, and the other one controls the gate signals of each gate line using a sense level shifter and a sense buffer. By being driven by the detection-side gate driver, it is possible to detect whether or not the supply-side gate driver is abnormal.

That is, according to an exemplary embodiment of the present invention, at least one of the first and second gate driving units transmits a gate signal to each gate line by using a sensing level shifter and a sensing buffer provided in each of the first and second gate driving units. It is possible to detect a state in which normal supply is not possible, that is, malfunction or breakage of at least one of the first and second gate driving units. Corresponding to the display mode for displaying an image on the display panel, among the first and second gate driver units, the gate driver unit detected as being unable to supply the gate signal normally is excluded, and only the normal gate driver unit receives the gate control signal. can be supplied.

Accordingly, secondary defects due to malfunction or damage of at least one of the first and second gate driving units can be prevented. That is, deterioration in image quality and display defects due to malfunction or damage of at least one of the first and second gate driving units can be prevented.

1 is a diagram illustrating a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram illustrating a gate line, first and second gate drivers, and a timing controller of the display device of FIG. 1 .
FIG. 3 is a view showing one of the first and second gate driving units of FIG. 2 .
4 is a diagram illustrating a method of driving a display device according to an exemplary embodiment of the present invention.
FIG. 5 is a diagram illustrating an example of the display device of FIG. 1 .
FIG. 6 is a diagram illustrating an operation of a supply-side gate driver according to the driving method of FIG. 4 .
FIG. 7 is a diagram illustrating an operation of a sensing-side gate driver according to the driving method of FIG. 4 .

The above objects, features and advantages will be described later in detail with reference to the accompanying drawings, and accordingly, those skilled in the art to which the present invention belongs will be able to easily implement the technical spirit of the present invention. In describing the present invention, if it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same or similar components.

Hereinafter, a display device and a driving method thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a display device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 to 3 .

1 is a diagram illustrating a display device according to an exemplary embodiment of the present invention. FIG. 2 is a diagram illustrating a gate line, first and second gate drivers, and a timing controller of the display device of FIG. 1 . FIG. 3 is a view showing one of the first and second gate driving units of FIG. 2 .

As shown in FIG. 1 , a display device according to an embodiment of the present invention includes a display panel 10 including a display area AA where an image is displayed, and signal lines 14 and 15 of the display panel 10 It includes a data driver 12 and a gate driver 13 that drive the data driver 12 and a timing controller 11 that controls driving timings of the data driver 12 and the gate driver 13 .

The display panel 10 includes a plurality of pixel areas PXL defined in a display area AA where an image is displayed, and pixels arranged side by side in a vertical direction (vertical direction in FIG. 1 ) among the plurality of pixel areas PXL. At least one vertical signal line 14 corresponding to each vertical line made up of areas, and each horizontal line made up of pixel areas arranged side by side in a horizontal direction (left-right direction in FIG. 1) among a plurality of pixel areas PXL. and at least one horizontal signal line 15 corresponding to the line.

In this way, a plurality of pixel areas PXL arranged in a matrix form in the display area AA may be defined by the vertical signal lines 14 and the horizontal signal lines 15 crossing each other.

Here, at least one vertical signal line 14 may include a data line supplying the data signal VDATA to the pixel region PXL.

At least one horizontal signal line 15 may include a gate line supplying a gate signal GS corresponding to an addressing period for supplying a data signal to the pixel region PXL.

Alternatively, according to the equivalent circuit of the pixel region PXL, the display panel 10 may include two or more gate lines for supplying two or more different gate signals to each horizontal line.

In addition, in the following description, a horizontal signal line is referred to as a gate line 15 and a vertical signal line is referred to as a data line 14 for simple explanation.

The timing controller 11 rearranges the digital video data RGB input from the outside according to the resolution of the display panel 10 and supplies the rearranged digital video data RGB′ to the data driver 12 .

Also, the timing controller 11 operates the data driver 12 based on timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK, and the data enable signal DE. A data control signal DDC for controlling the driving timing and a gate control signal GDC for controlling the driving timing of the gate drivers 13a and 13b are supplied.

The data driver 12 converts the rearranged digital video data RGB' into an analog data voltage based on the data control signal DDC. Also, the data driver 12 supplies the data signal VDATA corresponding to each pixel area to the data line 14 during each horizontal period based on the rearranged digital video data RGB'.

The gate driving units 13a and 13b are disposed on both sides of the gate line 15 and include first and second gate driving units 13a and 13b supplying gate signals to both sides of the gate line 15 . That is, the gate signals GS by the first and second gate drivers 13a and 13b are input to both sides of each gate line 15 .

Each of the first and second gate drivers 13a and 13b sequentially supplies a gate signal GS to the plurality of gate lines 15 included in the display panel 10 based on the gate control signal GDC. .

Further, each of the first and second gate drivers 13a and 13b detects the gate signal RGS of each gate line 15 based on the gate control signal GDC.

As shown in FIG. 2, the gate control signal (GDC in FIG. 1) is a gate start signal (GST; Gate StarT) for sequentially supplying the gate signal GS to the plurality of gate lines 15 and at least one It may include a gate clock signal (Gclks).

And, the gate control signal (GDC in FIG. 1 ) may further include a sensing start signal (RST; Receiving StarT) for sequentially detecting the gate signals (RGS; Received Gate Signal) of the plurality of gate lines 15 . .

That is, the timing controller 11 supplies the sensing start signals RST1 and RST2 to the sensing-side gate driver, which is one of the first and second gate drivers. Also, the timing controller 11 receives the sensing start signal responses (RST1', RST2') from the sensing-side gate driver.

That is, when the first gate driver 13a is a sensing-side gate driver and the second gate driver 13b is a supply-side gate driver, the timing controller 11 sends a first sensing start signal ( RST1) is supplied, and a gate start signal (GST) and at least one gate clock signal (Gclks) are supplied to the second gate driver 13b. Accordingly, the second gate driver 13b supplies the gate signal GS to one side (eg, the right side) of each gate line 15, and the first gate driver 13a supplies the gate signal GS to one side (eg, the right side) of each gate line 15. The gate signal RGS is detected. Subsequently, the timing controller 11 determines whether the second gate driver 13b, which is the supply-side gate driver, is normal according to whether or not the first sensing start signal response (RST1') is received within a predetermined threshold period.

Alternatively, when the first gate driver 13a is a supply-side gate driver and the second gate driver 13b is a sensing-side gate driver, the timing controller 11 sends a second sensing start signal ( RST2) is supplied, and a gate start signal (GST) and at least one gate clock signal (Gclks) are supplied to the first gate driver 13a. Accordingly, the first gate driver 13a supplies the gate signal GS to the other side (eg, the left side) of each gate line 15, and the second gate driver 13b supplies the gate signal GS to each gate line 15. Detects the gate signal RGS of Subsequently, the timing controller 11 determines whether the first gate driver 13a, which is the supply-side gate driver, is normal according to whether or not the second sensing start signal response (RST2') is received within a predetermined threshold period.

In addition, although not shown in FIG. 2 , each of the first and second gate drivers 13a and 13b includes a supply buffer ( 133 in FIG. 3 ) and a detection buffer ( 135 in FIG. 3 ). Accordingly, the gate control signal (GDC in FIG. 1) is a gate supplying enable signal (GBE) for controlling the driving of the supply buffer (133 in FIG. 3) and the driving of the sensing buffer (135 in FIG. 3). A gate detection enable signal (RBE; Receive Buffer Enable) for controlling and a buffer disable signal (not shown) for stopping driving of the supply buffer 133 and the detection buffer 135 may be further included.

Each of the first and second gate drivers 13a and 13b supplies a gate signal GS to each gate line 15 based on the gate supply enable signal GBE.

Each of the first and second gate drivers 13a and 13b detects the gate signal RGS of each gate line 15 based on the gate detection enable signal RBE.

Each of the first and second gate drivers 13a and 13b is maintained in a state of not supplying and detecting a gate signal, that is, a floating state, based on a buffer disable signal (not shown).

As shown in FIG. 3, each of the first and second gate drivers 13 corresponds to a plurality of gate lines 15 included in the display panel (10 in FIG. 1) and is sequentially connected to a plurality of stages ST1. , ST2, ST3, STi, STn; 3<i<n).

The shift register 131 generates gate pulses (GP1, GP2, GPn) by a plurality of stages (ST1, ST2, ST3, STi, STn) based on the gate start signal (GST) and at least one gate clock signal (Gclks). are output sequentially.

In addition, each gate driver 13 includes a supply level shifter 132 and a supply buffer 133 disposed between each stage ST1, ST2, ST3, STi, STn of the shift register 131 and each gate line 15. ) is further included.

The supply level shifter 132 corresponds to each of the stages ST1, ST2, ST3, STi, and STn. The supply level shifter 132 outputs gate signals GS1, GS2, and GSn based on the gate pulses GP1, GP2, and GPn of the respective stages ST1, ST2, ST3, STi, and STn. Here, the gate signal has a larger swing width than the gate pulse.

For example, the gate pulses GP1, GP2, and GPn have a swing width of 0V to 3.3V corresponding to the logic circuit of the shift register 131, and the supply level shifter 132 generates the gate pulses GP1, GP2, and GPn. ) may be pulled up to output gate signals GS1 , GS2 , and GSn composed of swing widths of the gate low voltage to the gate high voltage corresponding to the switching elements of the display panel 10 . Here, the gate low voltage may be -6V and the gate high voltage may be 24V.

The supply buffer 133 is disposed between the supply level shifter 132 and each gate line 15 . The supply buffer 133 applies the gate signals GS1, GS2, and GSn of the supply level shifter 132 to the gate based on the gate supply enable signal GBE among the gate control signals GDC by the timing controller 11. Pass on line 15.

In addition, according to an embodiment of the present invention, each gate driver 13 has a sensing level disposed between each stage ST1, ST2, ST3, STi, STn of the shift register 131 and each gate line 15. A shifter 134 and a detection buffer 135 are further included.

The sensing level shifter 134 corresponds to each gate line 15 . The sensing level shifter 134 outputs sensing signals RS1 , RS2 , and RSn corresponding to the gate signals RGS1 , RGS2 , and RGSn of each gate line 15 . Here, the sensing signals RS1, RS2, and RSn have swing widths smaller than those of the detected gate signals RGS1, RGS2, and RGSn.

For example, the detected gate signals RGS1 , RGS2 , and RGSn may have a swing width of a gate low voltage to a gate high voltage corresponding to the switching elements of the display panel 10 . Here, the gate low voltage may be -6V and the gate high voltage may be 24V. Then, the sensing level shifter 134 pulls down the detected gate signal RGS to generate sensing signals RS1, RS2, and RSn having a swing width of 0V to 3.3V corresponding to the logic circuit of the shift register 131. can be printed out.

The sensing buffer 135 is disposed between the sensing level shifter 134 and each stage ST1, ST2, ST3, STi, and STn of the shift register 131. The sensing buffer 135 transmits the sensing signals RS1, RS2, and RSn of the sensing level shifter 134 to each stage based on the gate sensing enable signal RBE among the gate control signals GDC by the timing controller 11. (ST1, ST2, ST3, STi, STn).

In addition, the shift register 131 transmits the sensing signals RS1, RS2, and RSn from the sensing buffer 135 to each stage ( ST1, ST2, ST3, STi, STn), the plurality of stages (ST1, ST2, ST3, STi, STn) are sequentially shifted.

That is, whenever the detection signals RS1, RS2, and RSn are received from the detection buffer 135, the detection start signal RST is sequentially moved in the plurality of stages ST1, ST2, ST3, STi, and STn.

When the shift register 131 shifts to the last stage STn among the plurality of stages ST1, ST2, ST3, STi, and STn, the response of the detection start signal (RST') is sent to the timing controller 11. convey

That is, when the sensing start signal RST moves to the last sequential stage STn among the plurality of stages ST1, ST2, ST3, STi, and STn, the shift register 131 reaches the last sequential stage STn. The sensed start signal RST' is returned to the timing controller 11.

In this way, the timing controller 11 can detect whether or not there is an abnormality in the supply-side gate driver supplying the gate signal GS to the gate line 15 by receiving the response (RST′) of the detection start signal.

In the display device according to the exemplary embodiment of the present invention, a method of driving the first and second gate driving units 13a and 13b in FIG. 1 by the timing controller (11 in FIG. 1) is as follows.

4 is a diagram illustrating a method of driving a display device according to an exemplary embodiment of the present invention. FIG. 5 is a diagram illustrating an example of the display device of FIG. 1 .

FIG. 6 is a diagram illustrating an operation of a supply-side gate driver according to the driving method of FIG. 4 . FIG. 7 is a diagram illustrating an operation of a sensing-side gate driver according to the driving method of FIG. 4 .

As shown in FIG. 4, a method of driving a display device according to an embodiment of the present invention includes setting an abnormality detection mode for detecting whether or not the first and second gate driving units (13a and 13b in FIG. 1) are abnormal. In step S10, a gate start signal (GST) and at least one gate clock signal (Gclks) are supplied to a supply-side gate driver, which is one of the first and second gate driver units 13a and 13b, corresponding to the abnormality detection mode. Supplying the sensing start signal (RST) to the other sensing-side gate driver (S20), receiving a response (RST') of the sensing start signal from the sensing-side gate driver (S31), and receiving the sensing start signal (RST') ) is within a predetermined critical period (S32), determining that the supply-side gate driver is normal (S33), and the detection start signal is returned from the sensing-side gate driver (RST') within the critical period (S32). If it is not received (S31, S32), determining the supply-side gate driver as abnormal (S34), the first and second gate driver (FIG. 1) corresponding to the display mode for displaying an image on the display panel (FIG. 1 10) Supplying a gate start signal (GST) and at least one gate clock signal (Gclks) to the gate driver determined to be normal among 13a and 13b) (S40), and first and second gate driver corresponding to the display mode Supplying a buffer disable signal to the gate driver determined to be abnormal among (13a and 13b of FIG. 1) (S50).

As mentioned above, the display device according to an exemplary embodiment of the present invention includes first and second gate drivers 13a and 13b disposed on both sides of the gate line 15 . That is, in order to improve the reliability of gate signal supply, it is necessary to detect whether each of the first and second gate driving units 13a and 13b has an abnormality. Accordingly, the step of supplying the gate start signal (GST) and at least one gate clock signal (Gclks) to the supply-side gate driver (S20) and the steps of determining whether the supply-side gate driver is normal or abnormal (S33, S34) are the first gate This is performed for the case where the driver 13a is selected as the supply-side gate driver and the case where the second gate driver 13b is selected as the supply-side gate driver.

On the other hand, as shown in FIG. 5 , according to an embodiment of the present invention, each of the first and second gate drivers ( 13a and 13b in FIG. 1 ) is connected to both sides of the display panel 10 in the horizontal direction of the film ( 201) and a gate driving chip 202 mounted on the film 201. At this time, due to the large size and high resolution of the display panel 10 , each of the first and second gate drivers 13a and 13b may be implemented with two or more chip-on films 201 and 202 .

Alternatively, although not separately shown, each of the first and second gate driving units 13a and 13b may be implemented as at least one gate driving chip mounted in a non-display area of the display panel 10 .

In addition, the data driver (12 in FIG. 1) is in the form of a chip-on-film consisting of a film 203 connected to at least one side of the display panel 10 in the vertical direction and a data driver chip 204 mounted on the film 203. can be implemented Due to the large size and high resolution of the display panel 10 , the data driver 12 may also be implemented with two or more chip-on-films 201 and 202 .

Also, the timing controller 11 and a power supply module (not shown) may be mounted on the printed circuit board 205 connected to two or more chip-on-films 201 and 202 corresponding to the data driver 12 .

And, as shown in FIGS. 6 and 7, each gate driver chip 202, 202' includes a shift register including a plurality of stages ST1, ST2, STn, and each stage ST1, ST2, STn It includes a supply level shifter 132, a supply buffer 133, a detection level shifter 134 and a detection buffer 135 corresponding to .

As shown in FIG. 6, each gate driving chip 202 has a plurality of gate lines based on a gate start signal (GST) and at least one gate clock signal (Gclks) supplied from a timing controller (11 in FIG. 1). Gate signals GS1, GS2 and GSn are sequentially supplied to (15).

That is, a gate start signal (GST) and at least one gate clock signal (Gclks) are supplied to each gate driving chip 202, and the gate start signal (GST) is applied to the first stage (ST1), which is the first order of the shift register. When shifted, the first stage ST1 outputs a gate pulse GP1 based on the gate start signal GST and at least one gate clock signal Gclks. Next, the supply level shifter 132 outputs the gate signal GS1 based on the gate pulse GP1 of the first stage ST1, and the supply buffer 133 outputs the gate signal GS1 based on the gate supply enable signal GBE. The gate signal GS1 is transferred to the gate line 15 .

Then, the gate start signal GST of the first stage ST1 is shifted to the next second stage ST2.

Through this process, when the gate start signal (GST) is shifted to the nth stage (STn), which is the last sequence of the shift register, the nth stage (STn) transmits the gate start signal (GST) to the gate driving chip 202' of the next sequence. ) and the timing controller 11.

In addition, the timing controller 11 may supply a turn-off level gate detection enable signal RBE to the supply-side gate driver so that the detection buffer 135 of the supply-side gate driver is not driven.

7 shows an example in which each of the first and second gate driving units 13a and 13b is composed of m number of gate driving chips, which is one of the m number of gate driving chips, that is, the k th gate driving chip ((k)th GIC) shows the operation of detecting the gate signals (GRS1, GRS2, GRSn) of the gate line.

Each gate driving chip ((k)th GIC) generates gate signals (GRS1, GRS2, and GRSN) of a plurality of gate lines 15 based on the sensing start signal (RST) supplied from the timing controller (11 in FIG. 1). After sequential detection, the sensing start signal RST is transferred to the next gate driving chip ((k+1)th GIC). And, the last gate driving chip ((m)th GIC) sequentially detects the corresponding gate signals (GRS1, GRS2, GRSn) of the plurality of gate lines 15 based on the sensing start signal (RST). After that, the response (RST') of the detection start signal is transmitted to the timing controller 11.

In other words, in each gate driving chip ((k)th GIC) corresponding to the sensing-side gate driving unit, the gate sensing enable signal RBE by the timing controller 11 and the timing controller 11 or the previous gate driving chip A detection start signal (RST) is supplied.

In this state, the sensing level shifter 134 outputs sensing signals RS1, RS2, and RSn corresponding to the gate signals RGS1, RGS2, and RGSn of the gate line 15, and the sensing buffer 135 outputs the sensing signals RS1, RGS2, and RGSn. Based on the enable signal RBE, the detection signals RS1, RS2, and RSn are transferred to each stage ST1, ST2, and STn of the shift register.

Here, since the supply-side gate driver is in a state of sequentially supplying gate signals to the plurality of gate lines 15, the plurality of detection buffers 135 connected to the plurality of stages ST1, ST2, and STn are sequentially input detection signals. (RS1, RS2, RSn) is transferred to each stage (ST1, ST2, STn).

In this way, whenever the sensing signals RS1, RS2, and RSn are transmitted, the sensing start signal RST is sequentially shifted in a plurality of stages ST1, ST2, and STn. That is, when the detection signal RS1 is transmitted from the detection buffer 135 corresponding to the first stage ST1 while the detection start signal RST is disposed in the first stage ST1, the first stage ST1 ) is shifted to the next sequential second stage ST2.

Also, when the detection signal RS2 is transmitted from the detection buffer 135 corresponding to the second stage ST2, the detection start signal RST of the second stage ST2 is shifted to the next stage.

Through this process, when the sensing start signal RST is shifted to the nth stage STn, which is the last sequence of the shift register, the nth stage STn transmits the sensing start signal RST to the next sequential gate driving chip ((k +1) forward to the th GIC).

Then, when the sensing start signal RST is shifted to the nth stage STn of the gate driving chip ((m)th GIC) in the last sequence, the gate driving chip ((m)th GIC) in the last sequence is the sensing start signal The response (RST') of is transferred to the timing controller 11.

In addition, the timing controller 11 may supply a turn-off level gate supply enable signal GBE to the sensing-side gate driver so that the supply buffer 133 of the sensing-side gate driver is not driven.

The timing controller 11 receives the response (RST') of the detection start signal (S31), and if the period corresponding to the time of receiving the response (RST') of the detection start signal is within a predetermined threshold period (S32), Check the gate driver on the supply side as normal. (S33)

On the other hand, if the timing controller 11 does not receive the response (RST') of the detection start signal within the critical period (S31 and S32), it determines that the supply-side gate driver is abnormal. (S34)

The timing controller 11 may determine whether the first and second gate drivers 13a and 13b are abnormal by alternately selecting the first and second gate drivers 13a and 13b as the supply-side gate driver.

Thereafter, in response to a display mode for displaying an image, the timing controller 11 sends a gate start signal (GST) to at least one gate driver determined to be normal among the first and second gate driver units 13a and 13b and transmits a gate start signal (GST) and at least one A gate clock signal (Gclks) is supplied.

Thus, in the display mode, at least one gate driver determined to be normal is normally driven, and the gate signal GS is supplied to the gate line 15 .

On the other hand, the timing controller 11 supplies a buffer disable signal to at least one gate driver determined to be faulty among the first and second gate driver 13a and 13b. Since the operation of the supply buffer 133 and the detection buffer 135 of each gate driver is stopped based on the buffer disable signal, the gate driver does not supply or detect the gate signal. That is, at least one gate driver determined as abnormal is maintained in a floating state based on the buffer disable signal.

For example, when both of the first and second gate drivers 13a and 13b are determined to be normal, gate signals may be supplied to both sides of each gate line 15 in the display mode.

On the other hand, when only one of the first and second gate drivers 13a and 13b is determined to be normal, a gate signal is supplied only to one side of each gate line 15 in the display mode. Also, the other side of each gate line 15 connected to the gate driver determined to be faulty among the first and second gate driver 13a and 13b is maintained in a floating state.

Meanwhile, although not separately shown, when the display panel includes two or more gate lines corresponding to respective horizontal lines and supplying two or more different gate signals, the first and second gate drivers 13a and 13b respectively It may include two or more signal blocks supplying two or more gate signals corresponding to horizontal lines.

Here, each of the two or more signal blocks has a structure including a shift register 131, a supply level shifter 132, a supply buffer 133, a detection level shifter 134, and a detection buffer 135 shown in FIG. .

As described above, according to an embodiment of the present invention, the first and second gate drivers 13a and 13b corresponding to both sides of the gate line detect the gate signal of each gate line, respectively, the sensing level shifter 134 and A detection buffer 135 is included, and when the detection signal is transmitted by the detection buffer 135, the detection start signal RST is sequentially shifted in each stage of the shift register 131, and finally the detection start signal is returned ( RST') is transmitted to the timing controller 11. Accordingly, it is possible to detect whether or not the gate signal is normally supplied by the supply-side gate driver. That is, it is possible to detect whether or not the first and second gate driving units 13a and 13b are abnormal.

In response to the display mode, the timing controller 11 supplies a buffer disable signal to the gate driver determined to be abnormal. Accordingly, the supply of the gate signal by the gate driver determined to be abnormal can be stopped.

Accordingly, secondary defects due to malfunction or damage of the first and second gate driving units 13a and 13b can be prevented. As a result, the picture quality and reliability of the display device may be improved.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the technical spirit of the present invention. Conventionally in the art to which the present invention belongs It will be clear to those who have knowledge of

10: display panel
AA: display area
PXL: pixel area
12: data driving unit
13a, 13b: first and second gate driving units
11: timing controller
15: gate line
GS: gate signal
RGS: detected gate signal
RS: detection signal
GST: gate start signal
Gclks: gate clock signal
RST: detection start signal
RST': Response of detection start signal
GBE: gate supply enable signal
RBE: Gate detection enable signal
131: shift register
ST: stage
132; supply level shifter
133: supply buffer
134: detection level shifter
135: detection buffer

Claims (12)

a display panel including a plurality of pixel areas defined in a display area and at least one gate line corresponding to the pixel areas arranged in a horizontal direction among the plurality of pixel areas;
first and second gate drivers disposed on both sides of the gate line and sequentially supplying gate signals to a plurality of gate lines included in the display panel; and
A timing controller supplying a gate control signal for controlling driving timing of the first and second gate drivers;
Each of the first and second gate drivers
a shift register including a plurality of stages corresponding to the plurality of gate lines and sequentially connected to each other;
a sensing level shifter corresponding to each of the gate lines and outputting a sensing signal corresponding to a gate signal of each of the gate lines; and
and a detection buffer disposed between the detection level shifter and each of the stages, and transmitting the detection signal to each of the stages based on a gate detection enable signal among the gate control signals.
According to claim 1,
The shift register is
When the detection signal is transmitted, the display device sequentially shifts the detection start signal among the gate control signals to the plurality of stages.
According to claim 2,
wherein the shift register transfers a response of the sensing start signal to the timing controller when the sensing start signal is shifted to the last stage among the plurality of stages.
According to claim 3,
the timing controller
Corresponding to the abnormality detection mode for detecting whether or not the first and second gate driving units are abnormal, a gate start signal and at least one of the gate control signals are sent to a supply-side gate driving unit that is one of the first and second gate driving units. supplying a gate clock signal and supplying the sensing start signal to the other sensing-side gate driver;
A display mode for displaying an image on the display panel when a response of the sensing start signal is received from the shift register of the sensing-side gate driver and the period corresponding to the response time of the sensing start signal is within a predetermined threshold period. and supplying the gate start signal and the at least one gate clock signal to the supply-side gate driver in response to
According to claim 1,
The shift register of each of the first and second gate drivers sequentially outputs gate pulses by the plurality of stages based on a gate start signal and at least one gate clock signal among the gate control signals;
Each of the first and second gate drivers
a supply level shifter corresponding to each stage and outputting a gate signal based on the gate pulse of each stage; and
and a supply buffer disposed between the supply level shifter and each of the gate lines, and transferring the gate signal to each of the gate lines based on a gate supply enable signal among the gate control signals.
According to claim 5,
The gate signal has a larger swing width than the gate pulse.
According to claim 1,
The detection signal has a smaller swing width than the gate signal.
A display panel including a plurality of pixel areas defined in a display area and at least one gate line corresponding to the pixel areas arranged in a horizontal direction among the plurality of pixel areas, disposed on both sides of the gate line, wherein the gate A method of driving a display device including first and second gate driver units supplying gate signals to both sides of a line, and a timing controller supplying gate control signals for controlling drive timing of the first and second gate driver units. in
setting an abnormality detection mode for detecting whether the first and second gate drivers are abnormal;
In response to the abnormality detection mode, a gate start signal and at least one gate clock signal among the gate control signals are supplied to a supply-side gate driver, which is one of the first and second gate drivers, and the other sensing gate is the other one. supplying a sensing start signal to a driving unit;
receiving a response of the sensing start signal from the sensing-side gate driver, and determining that the supply-side gate driver is normal if a period corresponding to a response point of the sensing start signal is within a predetermined threshold period; and
and supplying the gate start signal and the at least one gate clock signal to a gate driver determined to be normal among the first and second gate drivers in response to a display mode for displaying an image on the display panel. How to drive the device.
According to claim 8,
supplying the gate start signal and at least one gate clock signal to a supply-side gate driver, which is one of the first and second gate drivers, and determining that the supply-side gate driver is normal
A method of driving a display device performed for each case where the first gate driver is selected as the supply-side gate driver and when the second gate driver is selected as the supply-side gate driver.
According to claim 8,
Prior to the step of receiving the response of the detection start signal, the step of transmitting the response of the detection start signal to the timing controller by the detection-side gate driver;
The step of transmitting the response of the sensing start signal to the timing controller by the sensing-side gate driver
outputting, by the sensing level shifter of the sensing-side gate driver, a sensing signal corresponding to the gate signal of each gate line included in the display panel and having a smaller swing width than the gate signal;
transmitting, by a sensing buffer of the sensing-side gate driver, the sensing signal to a shift register of the sensing-side gate driver based on a gate sensing enable signal among the gate control signals;
sequentially shifting the sensing start signal to a plurality of stages corresponding to a plurality of gate lines included in the display panel when a shift register of the sensing-side gate driver receives the sensing signal; and
and transmitting a response of the sensing start signal to the timing controller when the sensing start signal is shifted to the last stage among the plurality of stages.
According to claim 10,
Prior to the step of outputting the detection signal, the step of supplying the gate signal to each of the gate lines by the supply-side gate driver;
The step of supplying the gate signal to each of the gate lines by the supply-side gate driver,
sequentially outputting gate pulses of the plurality of stages based on the gate start signal and the at least one gate clock signal by a shift register of the supply-side gate driver;
outputting, by the supply level shifter of the supply-side gate driver, a gate signal corresponding to the gate pulse of each stage and having a larger swing width than the gate pulse; and
and supplying, by the supply buffer of the supply-side gate driver, the gate signal to each of the gate lines based on a gate supply enable signal among the gate control signals.
According to claim 11,
determining that the supply-side gate driver is abnormal when the sensing start signal is not received from the sensing-side gate driver within the threshold period; and
Corresponding to the display mode, a buffer disable signal is supplied to the gate driver determined to be abnormal among the first and second gate driver, and the supply buffer and detection buffer of the supply-side gate driver are driven based on the buffer disable signal. A method of driving a display device further comprising the step of stopping.

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