KR102253295B1 - 기존 토포그래피 위에 평탄화된 에칭 마스크 구조를 형성하는 방법 - Google Patents

기존 토포그래피 위에 평탄화된 에칭 마스크 구조를 형성하는 방법 Download PDF

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KR102253295B1
KR102253295B1 KR1020180017407A KR20180017407A KR102253295B1 KR 102253295 B1 KR102253295 B1 KR 102253295B1 KR 1020180017407 A KR1020180017407 A KR 1020180017407A KR 20180017407 A KR20180017407 A KR 20180017407A KR 102253295 B1 KR102253295 B1 KR 102253295B1
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feature
layer
substrate
features
multilayer stack
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KR20180098138A (ko
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엘 드웨인 라브레이크
제이 더글라스 레스닉
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캐논 가부시끼가이샤
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    • H01L21/0337—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H01L21/0274—
    • H01L21/76816—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6342—Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/6902—Inorganic materials composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/696—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Shaping Of Tube Ends By Bending Or Straightening (AREA)
  • Laminated Bodies (AREA)
KR1020180017407A 2017-02-24 2018-02-13 기존 토포그래피 위에 평탄화된 에칭 마스크 구조를 형성하는 방법 Active KR102253295B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/441,381 2017-02-24
US15/441,381 US10079152B1 (en) 2017-02-24 2017-02-24 Method for forming planarized etch mask structures over existing topography

Publications (2)

Publication Number Publication Date
KR20180098138A KR20180098138A (ko) 2018-09-03
KR102253295B1 true KR102253295B1 (ko) 2021-05-20

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US (1) US10079152B1 (https=)
JP (1) JP7222606B2 (https=)
KR (1) KR102253295B1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
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JP7403961B2 (ja) * 2019-03-19 2023-12-25 キオクシア株式会社 インプリント方法および半導体装置の製造方法
JP7336303B2 (ja) * 2019-07-31 2023-08-31 キヤノン株式会社 物品製造方法、膜形成方法、型製造方法、物品製造システム、情報処理方法およびプログラム
US11567401B2 (en) * 2019-12-20 2023-01-31 Canon Kabushiki Kaisha Nanofabrication method with correction of distortion within an imprint system
US11656546B2 (en) 2020-02-27 2023-05-23 Canon Kabushiki Kaisha Exposure apparatus for uniform light intensity and methods of using the same
US11349061B2 (en) * 2020-06-08 2022-05-31 International Business Machines Corporation Glassy carbon mask for immersion implant and selective laser anneal
US11443940B2 (en) * 2020-06-24 2022-09-13 Canon Kabushiki Kaisha Apparatus for uniform light intensity and methods of using the same
US20250013153A1 (en) * 2023-07-06 2025-01-09 Tokyo Electron Limited Method of preventing pattern collapse

Citations (4)

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US20050184637A1 (en) 2004-01-29 2005-08-25 Asahi Glass Company, Limited Envelope for a flat panel display and flat panel display employing the envelope
US20130068720A1 (en) 2011-09-16 2013-03-21 Shuichi Taniguchi Pattern forming method
US20140227887A1 (en) 2011-09-06 2014-08-14 Dongjin Semichem Co., Ltd. Phenol-based self-crosslinking polymer and resist underlayer film composition including same
US20170003568A1 (en) 2014-01-30 2017-01-05 Sony Corporation Display unit and electronic apparatus

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US6873087B1 (en) 1999-10-29 2005-03-29 Board Of Regents, The University Of Texas System High precision orientation alignment and gap control stages for imprint lithography processes
US7077992B2 (en) 2002-07-11 2006-07-18 Molecular Imprints, Inc. Step and repeat imprint lithography processes
US6932934B2 (en) 2002-07-11 2005-08-23 Molecular Imprints, Inc. Formation of discontinuous films during an imprint lithography process
US7179396B2 (en) 2003-03-25 2007-02-20 Molecular Imprints, Inc. Positive tone bi-layer imprint lithography method
US7396475B2 (en) 2003-04-25 2008-07-08 Molecular Imprints, Inc. Method of forming stepped structures employing imprint lithography
US7157036B2 (en) 2003-06-17 2007-01-02 Molecular Imprints, Inc Method to reduce adhesion between a conformable region and a pattern of a mold
US7790231B2 (en) 2003-07-10 2010-09-07 Brewer Science Inc. Automated process and apparatus for planarization of topographical surfaces
US8076386B2 (en) 2004-02-23 2011-12-13 Molecular Imprints, Inc. Materials for imprint lithography
US7998651B2 (en) 2006-05-15 2011-08-16 Asml Netherlands B.V. Imprint lithography
EP2249204A4 (en) * 2008-02-18 2012-01-11 Nissan Chemical Ind Ltd SILICULAR RESISTANT LAYERING COMPOSITION COMPOSITION CONTAINING A CYCLIC AMINO GROUP
US8071275B2 (en) 2008-04-10 2011-12-06 Lexmark International, Inc. Methods for planarizing unevenness on surface of wafer photoresist layer and wafers produced by the methods
WO2009151560A2 (en) 2008-06-09 2009-12-17 Board Of Regents, The University Of Texas System Adaptive nanotopography sculpting
CN104137235B (zh) * 2012-01-19 2017-02-22 布鲁尔科技公司 含金刚烷基的非聚合物减反射组合物
KR102292465B1 (ko) 2013-08-19 2021-08-20 보드 오브 레젼츠, 더 유니버시티 오브 텍사스 시스템 나노미터 스케일 정확도를 갖는 사용자 정의 프로파일의 프로그램 가능한 박막 적층 방법
JP6323456B2 (ja) * 2013-09-11 2018-05-16 Jsr株式会社 多層レジストプロセス用無機膜形成組成物及びパターン形成方法

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US20050184637A1 (en) 2004-01-29 2005-08-25 Asahi Glass Company, Limited Envelope for a flat panel display and flat panel display employing the envelope
US20140227887A1 (en) 2011-09-06 2014-08-14 Dongjin Semichem Co., Ltd. Phenol-based self-crosslinking polymer and resist underlayer film composition including same
US20130068720A1 (en) 2011-09-16 2013-03-21 Shuichi Taniguchi Pattern forming method
JP2013065725A (ja) * 2011-09-16 2013-04-11 Toshiba Corp パターン形成方法
US20170003568A1 (en) 2014-01-30 2017-01-05 Sony Corporation Display unit and electronic apparatus

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Publication number Publication date
US20180247823A1 (en) 2018-08-30
KR20180098138A (ko) 2018-09-03
JP7222606B2 (ja) 2023-02-15
JP2018142701A (ja) 2018-09-13
US10079152B1 (en) 2018-09-18

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