JP7222606B2 - エッチングマスク構造を形成するための方法 - Google Patents

エッチングマスク構造を形成するための方法 Download PDF

Info

Publication number
JP7222606B2
JP7222606B2 JP2018027233A JP2018027233A JP7222606B2 JP 7222606 B2 JP7222606 B2 JP 7222606B2 JP 2018027233 A JP2018027233 A JP 2018027233A JP 2018027233 A JP2018027233 A JP 2018027233A JP 7222606 B2 JP7222606 B2 JP 7222606B2
Authority
JP
Japan
Prior art keywords
layer
substrate
features
stack
feature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018027233A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018142701A5 (https=
JP2018142701A (ja
Inventor
ラボレイク ドウェイン
レズニック ダグラス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of JP2018142701A publication Critical patent/JP2018142701A/ja
Publication of JP2018142701A5 publication Critical patent/JP2018142701A5/ja
Application granted granted Critical
Publication of JP7222606B2 publication Critical patent/JP7222606B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6342—Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/6902—Inorganic materials composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/696—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Shaping Of Tube Ends By Bending Or Straightening (AREA)
  • Laminated Bodies (AREA)
JP2018027233A 2017-02-24 2018-02-19 エッチングマスク構造を形成するための方法 Active JP7222606B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/441,381 2017-02-24
US15/441,381 US10079152B1 (en) 2017-02-24 2017-02-24 Method for forming planarized etch mask structures over existing topography

Publications (3)

Publication Number Publication Date
JP2018142701A JP2018142701A (ja) 2018-09-13
JP2018142701A5 JP2018142701A5 (https=) 2021-04-08
JP7222606B2 true JP7222606B2 (ja) 2023-02-15

Family

ID=63246983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018027233A Active JP7222606B2 (ja) 2017-02-24 2018-02-19 エッチングマスク構造を形成するための方法

Country Status (3)

Country Link
US (1) US10079152B1 (https=)
JP (1) JP7222606B2 (https=)
KR (1) KR102253295B1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7403961B2 (ja) * 2019-03-19 2023-12-25 キオクシア株式会社 インプリント方法および半導体装置の製造方法
JP7336303B2 (ja) * 2019-07-31 2023-08-31 キヤノン株式会社 物品製造方法、膜形成方法、型製造方法、物品製造システム、情報処理方法およびプログラム
US11567401B2 (en) * 2019-12-20 2023-01-31 Canon Kabushiki Kaisha Nanofabrication method with correction of distortion within an imprint system
US11656546B2 (en) 2020-02-27 2023-05-23 Canon Kabushiki Kaisha Exposure apparatus for uniform light intensity and methods of using the same
US11349061B2 (en) * 2020-06-08 2022-05-31 International Business Machines Corporation Glassy carbon mask for immersion implant and selective laser anneal
US11443940B2 (en) * 2020-06-24 2022-09-13 Canon Kabushiki Kaisha Apparatus for uniform light intensity and methods of using the same
US20250013153A1 (en) * 2023-07-06 2025-01-09 Tokyo Electron Limited Method of preventing pattern collapse

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009104552A1 (ja) 2008-02-18 2009-08-27 日産化学工業株式会社 環状アミノ基を有するシリコン含有レジスト下層膜形成組成物
JP2013065725A (ja) 2011-09-16 2013-04-11 Toshiba Corp パターン形成方法
JP2015507223A (ja) 2012-01-19 2015-03-05 ブルーワー サイエンス アイ エヌシー． アダマンチル基を含む非ポリマー性反射防止組成物
WO2015037398A1 (ja) 2013-09-11 2015-03-19 Jsr株式会社 多層レジストプロセス用無機膜形成組成物及びパターン形成方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6873087B1 (en) 1999-10-29 2005-03-29 Board Of Regents, The University Of Texas System High precision orientation alignment and gap control stages for imprint lithography processes
US7077992B2 (en) 2002-07-11 2006-07-18 Molecular Imprints, Inc. Step and repeat imprint lithography processes
US6932934B2 (en) 2002-07-11 2005-08-23 Molecular Imprints, Inc. Formation of discontinuous films during an imprint lithography process
US7179396B2 (en) 2003-03-25 2007-02-20 Molecular Imprints, Inc. Positive tone bi-layer imprint lithography method
US7396475B2 (en) 2003-04-25 2008-07-08 Molecular Imprints, Inc. Method of forming stepped structures employing imprint lithography
US7157036B2 (en) 2003-06-17 2007-01-02 Molecular Imprints, Inc Method to reduce adhesion between a conformable region and a pattern of a mold
US7790231B2 (en) 2003-07-10 2010-09-07 Brewer Science Inc. Automated process and apparatus for planarization of topographical surfaces
KR20050077751A (ko) * 2004-01-29 2005-08-03 아사히 가라스 가부시키가이샤 평판 디스플레이용 외부용기 및 그것을 사용한 평판디스플레이
US8076386B2 (en) 2004-02-23 2011-12-13 Molecular Imprints, Inc. Materials for imprint lithography
US7998651B2 (en) 2006-05-15 2011-08-16 Asml Netherlands B.V. Imprint lithography
US8071275B2 (en) 2008-04-10 2011-12-06 Lexmark International, Inc. Methods for planarizing unevenness on surface of wafer photoresist layer and wafers produced by the methods
WO2009151560A2 (en) 2008-06-09 2009-12-17 Board Of Regents, The University Of Texas System Adaptive nanotopography sculpting
KR101821705B1 (ko) * 2011-09-06 2018-01-25 주식회사 동진쎄미켐 페놀계 자가가교 고분자 및 이를 포함하는 레지스트 하층막 조성물
KR102292465B1 (ko) 2013-08-19 2021-08-20 보드 오브 레젼츠, 더 유니버시티 오브 텍사스 시스템 나노미터 스케일 정확도를 갖는 사용자 정의 프로파일의 프로그램 가능한 박막 적층 방법
WO2015114960A1 (ja) * 2014-01-30 2015-08-06 ソニー株式会社 表示装置および電子機器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009104552A1 (ja) 2008-02-18 2009-08-27 日産化学工業株式会社 環状アミノ基を有するシリコン含有レジスト下層膜形成組成物
JP2013065725A (ja) 2011-09-16 2013-04-11 Toshiba Corp パターン形成方法
JP2015507223A (ja) 2012-01-19 2015-03-05 ブルーワー サイエンス アイ エヌシー． アダマンチル基を含む非ポリマー性反射防止組成物
WO2015037398A1 (ja) 2013-09-11 2015-03-19 Jsr株式会社 多層レジストプロセス用無機膜形成組成物及びパターン形成方法

Also Published As

Publication number Publication date
US20180247823A1 (en) 2018-08-30
KR20180098138A (ko) 2018-09-03
JP2018142701A (ja) 2018-09-13
KR102253295B1 (ko) 2021-05-20
US10079152B1 (en) 2018-09-18

Similar Documents

Publication Publication Date Title
JP7222606B2 (ja) エッチングマスク構造を形成するための方法
US7960090B2 (en) Pattern forming method, pattern formed thereby, mold, processing apparatus, and processing method
US8961852B2 (en) Templates having high contrast alignment marks
US8012394B2 (en) Template pattern density doubling
US7357876B2 (en) Eliminating printability of sub-resolution defects in imprint lithography
US10211051B2 (en) Method of reverse tone patterning
TWI388417B (zh) 於模板形成過程中之關鍵尺寸控制技術
KR102379626B1 (ko) 차광 재료를 구비한 나노임프린트 템플릿 및 제작 방법
WO2007133346A2 (en) Imprint lithography method and system
US8935981B2 (en) High contrast alignment marks through multiple stage imprinting
JP2018074159A (ja) 基板からナノインプリントテンプレートを引き離す方法
JP5848386B2 (ja) インサイチュ嵌込み構造物形成方法
CN114127899B (zh) 用于平坦化旋涂膜和cvd沉积有机膜的方法
KR20210080218A (ko) 임프린트 시스템 내의 왜곡의 보정을 갖는 나노제조 방법
US20100095862A1 (en) Double Sidewall Angle Nano-Imprint Template
JP4861044B2 (ja) 基板の加工方法、パターン領域を有する部材の製造方法
TW202400507A (zh) 用於製造壓印微影模板的方法、用於製造光學部件的方法以及用於製造光學元件的方法
US12085852B2 (en) Template, method of forming a template, apparatus and method of manufacturing an article
JP6213610B2 (ja) ナノインプリントリソグラフィ用テンプレートの製造方法

Legal Events

Date Code Title Description
RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20210103

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210113

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210219

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210219

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20211209

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220124

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220314

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220812

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221007

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230105

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230203

R151 Written notification of patent or utility model registration

Ref document number: 7222606

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151