KR102253295B1 - 기존 토포그래피 위에 평탄화된 에칭 마스크 구조를 형성하는 방법 - Google Patents

기존 토포그래피 위에 평탄화된 에칭 마스크 구조를 형성하는 방법 Download PDF

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KR102253295B1
KR102253295B1 KR1020180017407A KR20180017407A KR102253295B1 KR 102253295 B1 KR102253295 B1 KR 102253295B1 KR 1020180017407 A KR1020180017407 A KR 1020180017407A KR 20180017407 A KR20180017407 A KR 20180017407A KR 102253295 B1 KR102253295 B1 KR 102253295B1
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feature
layer
substrate
features
multilayer stack
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KR20180098138A (ko
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엘 드웨인 라브레이크
제이 더글라스 레스닉
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캐논 가부시끼가이샤
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • HELECTRICITY
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    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088Process specially adapted to improve the resolution of the mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Laminated Bodies (AREA)
  • Shaping Of Tube Ends By Bending Or Straightening (AREA)
KR1020180017407A 2017-02-24 2018-02-13 기존 토포그래피 위에 평탄화된 에칭 마스크 구조를 형성하는 방법 Active KR102253295B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/441,381 2017-02-24
US15/441,381 US10079152B1 (en) 2017-02-24 2017-02-24 Method for forming planarized etch mask structures over existing topography

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KR20180098138A KR20180098138A (ko) 2018-09-03
KR102253295B1 true KR102253295B1 (ko) 2021-05-20

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US (1) US10079152B1 (enExample)
JP (1) JP7222606B2 (enExample)
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7403961B2 (ja) * 2019-03-19 2023-12-25 キオクシア株式会社 インプリント方法および半導体装置の製造方法
JP7336303B2 (ja) * 2019-07-31 2023-08-31 キヤノン株式会社 物品製造方法、膜形成方法、型製造方法、物品製造システム、情報処理方法およびプログラム
US11567401B2 (en) * 2019-12-20 2023-01-31 Canon Kabushiki Kaisha Nanofabrication method with correction of distortion within an imprint system
US11656546B2 (en) 2020-02-27 2023-05-23 Canon Kabushiki Kaisha Exposure apparatus for uniform light intensity and methods of using the same
US11349061B2 (en) * 2020-06-08 2022-05-31 International Business Machines Corporation Glassy carbon mask for immersion implant and selective laser anneal
US11443940B2 (en) * 2020-06-24 2022-09-13 Canon Kabushiki Kaisha Apparatus for uniform light intensity and methods of using the same
US20250013153A1 (en) * 2023-07-06 2025-01-09 Tokyo Electron Limited Method of preventing pattern collapse

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050184637A1 (en) 2004-01-29 2005-08-25 Asahi Glass Company, Limited Envelope for a flat panel display and flat panel display employing the envelope
US20130068720A1 (en) 2011-09-16 2013-03-21 Shuichi Taniguchi Pattern forming method
US20140227887A1 (en) 2011-09-06 2014-08-14 Dongjin Semichem Co., Ltd. Phenol-based self-crosslinking polymer and resist underlayer film composition including same
US20170003568A1 (en) 2014-01-30 2017-01-05 Sony Corporation Display unit and electronic apparatus

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6873087B1 (en) 1999-10-29 2005-03-29 Board Of Regents, The University Of Texas System High precision orientation alignment and gap control stages for imprint lithography processes
US6932934B2 (en) 2002-07-11 2005-08-23 Molecular Imprints, Inc. Formation of discontinuous films during an imprint lithography process
US7077992B2 (en) 2002-07-11 2006-07-18 Molecular Imprints, Inc. Step and repeat imprint lithography processes
US7179396B2 (en) 2003-03-25 2007-02-20 Molecular Imprints, Inc. Positive tone bi-layer imprint lithography method
US7396475B2 (en) 2003-04-25 2008-07-08 Molecular Imprints, Inc. Method of forming stepped structures employing imprint lithography
US7157036B2 (en) 2003-06-17 2007-01-02 Molecular Imprints, Inc Method to reduce adhesion between a conformable region and a pattern of a mold
US7790231B2 (en) 2003-07-10 2010-09-07 Brewer Science Inc. Automated process and apparatus for planarization of topographical surfaces
US8076386B2 (en) 2004-02-23 2011-12-13 Molecular Imprints, Inc. Materials for imprint lithography
US7998651B2 (en) 2006-05-15 2011-08-16 Asml Netherlands B.V. Imprint lithography
CN101946209B (zh) * 2008-02-18 2014-01-22 日产化学工业株式会社 具有环状氨基的含有硅的形成抗蚀剂下层膜的组合物
US8071275B2 (en) 2008-04-10 2011-12-06 Lexmark International, Inc. Methods for planarizing unevenness on surface of wafer photoresist layer and wafers produced by the methods
US8394282B2 (en) 2008-06-09 2013-03-12 Board Of Regents, The University Of Texas System Adaptive nanotopography sculpting
SG11201404229YA (en) * 2012-01-19 2014-08-28 Brewer Science Inc Nonpolymeric antireflection compositions containing adamantyl groups
JP6495283B2 (ja) 2013-08-19 2019-04-03 ボード・オブ・リージエンツ,ザ・ユニバーシテイ・オブ・テキサス・システム ナノメータスケール精度を有するユーザ定義プロファイルのプログラム可能な薄膜蒸着
JP6323456B2 (ja) * 2013-09-11 2018-05-16 Jsr株式会社 多層レジストプロセス用無機膜形成組成物及びパターン形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050184637A1 (en) 2004-01-29 2005-08-25 Asahi Glass Company, Limited Envelope for a flat panel display and flat panel display employing the envelope
US20140227887A1 (en) 2011-09-06 2014-08-14 Dongjin Semichem Co., Ltd. Phenol-based self-crosslinking polymer and resist underlayer film composition including same
US20130068720A1 (en) 2011-09-16 2013-03-21 Shuichi Taniguchi Pattern forming method
JP2013065725A (ja) * 2011-09-16 2013-04-11 Toshiba Corp パターン形成方法
US20170003568A1 (en) 2014-01-30 2017-01-05 Sony Corporation Display unit and electronic apparatus

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US20180247823A1 (en) 2018-08-30
US10079152B1 (en) 2018-09-18
KR20180098138A (ko) 2018-09-03
JP2018142701A (ja) 2018-09-13
JP7222606B2 (ja) 2023-02-15

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