KR102242125B1 - 열팽창 매칭된 장치를 제공하는 이동 방법 - Google Patents

열팽창 매칭된 장치를 제공하는 이동 방법 Download PDF

Info

Publication number
KR102242125B1
KR102242125B1 KR1020197014262A KR20197014262A KR102242125B1 KR 102242125 B1 KR102242125 B1 KR 102242125B1 KR 1020197014262 A KR1020197014262 A KR 1020197014262A KR 20197014262 A KR20197014262 A KR 20197014262A KR 102242125 B1 KR102242125 B1 KR 102242125B1
Authority
KR
South Korea
Prior art keywords
substrate
major surface
circuit layer
bonding
handle
Prior art date
Application number
KR1020197014262A
Other languages
English (en)
Korean (ko)
Other versions
KR20190065430A (ko
Inventor
존 제이. 드래브
Original Assignee
레이던 컴퍼니
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 레이던 컴퍼니 filed Critical 레이던 컴퍼니
Publication of KR20190065430A publication Critical patent/KR20190065430A/ko
Application granted granted Critical
Publication of KR102242125B1 publication Critical patent/KR102242125B1/ko

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Storage Device Security (AREA)
  • Wire Bonding (AREA)
KR1020197014262A 2016-10-21 2017-10-17 열팽창 매칭된 장치를 제공하는 이동 방법 KR102242125B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/331,149 US10453731B2 (en) 2016-10-21 2016-10-21 Direct bond method providing thermal expansion matched devices
US15/331,149 2016-10-21
PCT/US2017/056875 WO2018075444A1 (en) 2016-10-21 2017-10-17 Transfer method providing thermal expansion matched devices

Publications (2)

Publication Number Publication Date
KR20190065430A KR20190065430A (ko) 2019-06-11
KR102242125B1 true KR102242125B1 (ko) 2021-04-20

Family

ID=60201679

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020197014262A KR102242125B1 (ko) 2016-10-21 2017-10-17 열팽창 매칭된 장치를 제공하는 이동 방법

Country Status (10)

Country Link
US (2) US10453731B2 (ja)
EP (1) EP3529830A1 (ja)
JP (1) JP2019535147A (ja)
KR (1) KR102242125B1 (ja)
CN (1) CN109863586A (ja)
CA (1) CA3041040A1 (ja)
IL (1) IL266052B (ja)
SG (1) SG11201902587RA (ja)
TW (1) TW201816993A (ja)
WO (1) WO2018075444A1 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7143182B2 (ja) * 2018-10-23 2022-09-28 株式会社ダイセル 半導体装置製造方法および半導体装置
US10847569B2 (en) * 2019-02-26 2020-11-24 Raytheon Company Wafer level shim processing
US12046477B2 (en) * 2021-01-08 2024-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. By-site-compensated etch back for local planarization/topography adjustment
CN117549205B (zh) * 2024-01-11 2024-04-02 东晶电子金华有限公司 一种石英晶片的抛光方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994017557A1 (en) 1993-01-19 1994-08-04 Hughes Aircraft Company Thermally matched readout/detector assembly and method for fabricating same
US20040241958A1 (en) * 2003-06-02 2004-12-02 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5308980A (en) 1991-02-20 1994-05-03 Amber Engineering, Inc. Thermal mismatch accommodated infrared detector hybrid array
US5591678A (en) 1993-01-19 1997-01-07 He Holdings, Inc. Process of manufacturing a microelectric device using a removable support substrate and etch-stop
GB0019322D0 (en) * 2000-08-08 2000-09-27 Isis Innovation Method of separating nucleoside phosphates
US6731244B2 (en) * 2002-06-27 2004-05-04 Harris Corporation High efficiency directional coupler
US7535100B2 (en) * 2002-07-12 2009-05-19 The United States Of America As Represented By The Secretary Of The Navy Wafer bonding of thinned electronic materials and circuits to high performance substrates
US7723815B1 (en) 2004-07-09 2010-05-25 Raytheon Company Wafer bonded composite structure for thermally matching a readout circuit (ROIC) and an infrared detector chip both during and after hybridization
US8154099B2 (en) 2009-08-19 2012-04-10 Raytheon Company Composite semiconductor structure formed using atomic bonding and adapted to alter the rate of thermal expansion of a substrate
US10094024B2 (en) * 2011-06-24 2018-10-09 Tokyo Ohka Kogyo Co., Ltd. Method of manufacturing multilayer body, method of processing substrate, and multilayer body
US20130168803A1 (en) * 2011-09-16 2013-07-04 Sionyx, Inc. Semiconductor-On-Insulator Devices and Associated Methods
US9673077B2 (en) * 2012-07-03 2017-06-06 Watlow Electric Manufacturing Company Pedestal construction with low coefficient of thermal expansion top
DE102013004559B4 (de) * 2013-03-18 2015-07-23 Apple Inc. Bruchstabile Saphirscheibe und Verfahren zu ihrer Herstellung
US9048091B2 (en) * 2013-03-25 2015-06-02 Infineon Technologies Austria Ag Method and substrate for thick III-N epitaxy
US9912084B2 (en) 2014-08-20 2018-03-06 Te Connectivity Corporation High speed signal connector assembly

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994017557A1 (en) 1993-01-19 1994-08-04 Hughes Aircraft Company Thermally matched readout/detector assembly and method for fabricating same
US20040241958A1 (en) * 2003-06-02 2004-12-02 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature

Also Published As

Publication number Publication date
US10453731B2 (en) 2019-10-22
JP2019535147A (ja) 2019-12-05
WO2018075444A1 (en) 2018-04-26
CA3041040A1 (en) 2018-04-26
SG11201902587RA (en) 2019-05-30
KR20190065430A (ko) 2019-06-11
TW201816993A (zh) 2018-05-01
US20200035539A1 (en) 2020-01-30
IL266052A (en) 2019-06-30
EP3529830A1 (en) 2019-08-28
US20180114713A1 (en) 2018-04-26
US11177155B2 (en) 2021-11-16
IL266052B (en) 2022-02-01
CN109863586A (zh) 2019-06-07

Similar Documents

Publication Publication Date Title
KR102242125B1 (ko) 열팽창 매칭된 장치를 제공하는 이동 방법
US10580823B2 (en) Wafer level packaging method
US9859322B2 (en) Methods and apparatus for glass removal in CMOS image sensors
US8580594B2 (en) Method of fabricating a semiconductor device having recessed bonding site
US8697542B2 (en) Method for thin die-to-wafer bonding
US10153237B2 (en) Chip package and method for forming the same
US8969200B2 (en) Apparatus and method for integration of through substrate vias
US8154099B2 (en) Composite semiconductor structure formed using atomic bonding and adapted to alter the rate of thermal expansion of a substrate
TW201729303A (zh) 半導體結構及其製造方法
US20170154881A1 (en) Semiconductor device and method of manufacturing the same
US9318527B2 (en) Method for producing photosensitive infrared detectors
US20080009095A1 (en) Advanced Thin Flexible Microelectronic Assemblies and Methods for Making Same
US7297613B1 (en) Method of fabricating and integrating high quality decoupling capacitors
WO2010082464A1 (ja) 半導体装置及びその製造方法
US20180082888A1 (en) Wafer level integration including design/co-design, structure process, equipment stress management, and thermal management
US7723815B1 (en) Wafer bonded composite structure for thermally matching a readout circuit (ROIC) and an infrared detector chip both during and after hybridization
US11769785B2 (en) Process for collectively curving a set of electronic chips
JP2007059755A (ja) 固体撮像装置及びその製造方法
US11424286B2 (en) Wafer-level process for curving a set of electronic chips
US11164749B1 (en) Warpage reduction
JP7477285B2 (ja) 半導体装置、および半導体装置の製造方法
Chang et al. Process integration of backside illuminated image sensor with thin wafer handling technology
CN117673008A (zh) 使用应力水平不同的两个氧化物层的接合结构和相关方法

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant