WO1994017557A1 - Thermally matched readout/detector assembly and method for fabricating same - Google Patents

Thermally matched readout/detector assembly and method for fabricating same Download PDF

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Publication number
WO1994017557A1
WO1994017557A1 PCT/US1994/000370 US9400370W WO9417557A1 WO 1994017557 A1 WO1994017557 A1 WO 1994017557A1 US 9400370 W US9400370 W US 9400370W WO 9417557 A1 WO9417557 A1 WO 9417557A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
substrate
assembly
bonded
layer
Prior art date
Application number
PCT/US1994/000370
Other languages
French (fr)
Inventor
Ronald M. Finnila
Gerard T. Malloy
Joseph J. Bendik
Original Assignee
Hughes Aircraft Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Company filed Critical Hughes Aircraft Company
Priority to GB9418859A priority Critical patent/GB2279808B/en
Priority to JP6517072A priority patent/JPH07506937A/en
Priority to PCT/US1994/000370 priority patent/WO1994017557A1/en
Publication of WO1994017557A1 publication Critical patent/WO1994017557A1/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/02—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating by means of a press ; Diffusion bonding
    • B23K20/023—Thermo-compression bonding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/16—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating with interposition of special material to facilitate connection of the parts, e.g. material for absorbing or producing gas
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/001—Interlayers, transition pieces for metallurgical bonding of workpieces
    • B23K35/004—Interlayers, transition pieces for metallurgical bonding of workpieces at least one of the workpieces being of a metal of the iron group
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Definitions

  • the invention relates to integrated circuit manufacturing technology and more particularly to methods for fabricating readout chips for use in sensor chip assemblies (SCA's).
  • Sensor Chip Assemblies are key components in Infrared (IR) detection systems.
  • IR Infrared
  • One typical failure mode results in a deterioration of the electrical conductors, such as indium bumps, that are used to hybridize the readout chip to the detector chip.
  • a chip assembl for hybridization, or bump bonding with another devic having a determined thermal expansion characteristic, th assembly comprising a silicon thin film circuit bonded t a substrate of a material selected so as to match th thermal expansion characteristic of the readout chi assembly to the thermal expansion characteristic of th other device.
  • the device is a radiatio detector comprised of a Group II-VI material, such a HgCdTe.
  • a first method referred to herein as a thin film transfer method, includes the steps of providing a bonded silicon wafer whic includes a thin layer of silicon on a silicon substrate; forming a circuit in the thin silicon layer; forming a least one electrical feedthrough in the thin silicon layer; bonding the thin silicon layer, including the circuit, to a selected substrate comprising a material selected for thermally matching the chip assembly to another material to be hybridized therewith; and thereafter removing the silicon substrate.
  • a second method includes the steps of providing a bonded silicon wafer which includes a thin layer of silicon on a silicon substrate; forming a circuit in the thin silicon layer; bonding the thin silicon layer, including the circuit, to a selected temporary carrier substrate; removing the silicon substrate; bonding the thin silicon layer to a final substrate that is comprised of a material selected for thermally matching the readout chip assembly to another material to be hybridized therewith; and thereafter removing the temporary carrier substrate.
  • this invention also allows processing (e.g. depositing and patterning thin films) on both sides of the active silicon film. This improves layout density, makes possible new and novel transistor structures and provides superior RF shielding.
  • the active circuits in thin silicon (0.2-4 microns thick) films, as well as performing low temperature (below 450 ) processing steps (e.g. deposit and pattern metal, low temperature insulating film, etc.) on the backside of the thin silicon film.
  • This technique provides the advantage of higher device density because of an extra layer of interconnection available on the back surface, fabricating novel devices such as a dual gate MOS transistor, and superior RF shielding by providing shielding layers on both sides of the active circuitry.
  • the silicon film thickness for active devices may be very thin (»0.2 micron). These very thin films provide superior radiation hardness and facilitate operation of the MOS transistors in a fully depleted mode to provide higher performance.
  • this invention also has the advantage of being applicable to any detector material, and is not limited for use with Group III-V material, such as HgCdTe.
  • Figs, la through Id are cross-sectional views (not t scale) that illustrate processing steps of a first metho of the invention, specifically a thin film transfer method, wherein,
  • Fig. la is a cross section of a wafer illustrating the initial stage of fabrication of a chip assembly i accordance with the invention
  • Fig. lb is a cross section illustrating an example of a feedthrough
  • Fig. lc is a cross sectional view with the circuits fabricated and the wafer attached to the chosen substrate in accordance with the invention
  • Fig. Id is a simplified cross section of the assembly in accordance with the invention.
  • Figs. 2a through 2e are cross-sectional views, not to scale, that illustrate a second method of the invention, specifically a double transfer method.
  • the method for making an assembly in accordance with the first or second methods of the invention begins with a bonded silicon wafer as illustrated in cross-section at 10 in Fig. la.
  • the wafer 10 comprises a thin, preferably 0.2- 10 micrometers thick, film 12 made of single crystal silicon of bulk silicon quality on top of a layer of thermal SiO_, as shown at 14. It will be understood that the thickness of the SiO- layer is not critical and would typically be in the range 0.1 - 1.5 microns.
  • the films 12 and 14 are disposed on top of a normal bulk silicon wafer illustrated at 16.
  • the wafer 10 may be purchased commercially, or may be fabricated by providing two silicon wafers, depositing the silicon dioxide layer on a surface of one, and then fusion bonding ( ⁇ 1200 degrees C) the two wafers together with the layer of silicon dioxide interposed between the two wafers. One of the wafers is then thinned to a desired thickness in the range of a fraction of a micrometer to 50 micrometers. Thinning can be accomplished by a mechanical grinding process that is optionally followed by a plasma etching process.
  • Conventional readout circuits (not seen in Fig. lb) are processed in the thin film 12 using conventional methods disclosed, for example, by Hayashi, et al. previously cited.
  • Conventional readout circuits can include transimpedance amplifiers, signal multiplexers, and the like of a type conventionally used for interfacing to an array of IR radiation detectors. Processing continues through the step of depositing an overglass layer (shown in Fig. lc at 18), and includes the addition of electrical feedthroughs illustrated in Fig. lb at 20.
  • the electrical feedthroughs illustrated at 20 can be incorporated at any convenient part of the process, though preferably at an early stage in the process.
  • the feedthroughs 20 are made by etching trenches through the thin silicon layer 12 to the oxide layer 14 below.
  • the etching step is readily accomplished because the oxide acts as an etch stop.
  • the trench walls indicated at 22 are then oxidized using a conventional thermal oxidation process.
  • the trench hole is then filled with a conductive material.
  • Doped polycrystalline silicon polysilicon
  • other materials such as, for example, tungsten, may also be used if desired.
  • An alternative feedthrough arrangement may be fabricated by using the doped single crystal silicon layer itself and isolating a portion with a trench.
  • Fig. lc shows illustrative examples of devices fabricated in the thin film 12.
  • the structure formed thus far has been processed to form N-type and P- type regions, as required for the particular circuit application, within the silicon film 12. These regions may be delineated through a photolithographic process and are formed through a diffusion or an implantation step. Subsequent to doping the silicon film 12 both p+ and n+ regions are also photolithographically defined and diffused or implanted.
  • One or more polysilicon gate electrodes 17 may be also deposited, as required.
  • a further layer of SiO- shown at 14' may be formed to bury the gate electrodes 17.
  • An electrically insulating overglass layer 18 may also be deposited in a conventional manner.
  • the bonded wafer 10 with the circuits fabricated (Fig. lc) is next attached as seen in Fig. Id to a substrate 24 which is chosen to have a coefficient of thermal expansion that is selected for providing the resultant readout chip assembly with an effective coefficient of thermal expansion that is approximately the same as the coefficient of thermal expansion of the intended detector chip.
  • a substrate 24 which is chosen to have a coefficient of thermal expansion that is selected for providing the resultant readout chip assembly with an effective coefficient of thermal expansion that is approximately the same as the coefficient of thermal expansion of the intended detector chip.
  • suitable substrate materials have been found to include GaAs, CdTe, Ge, and a-plane sapphire.
  • the effective coefficient of thermal expansion of the readout integrated circuit assembly is within approximately 20% of the coefficient of thermal expansion of the detector material so as to avoid deleterious effects due to thermal cycling.
  • the attachment at 26 of the ' substrate 24 to the thin film silicon side of the bonded silicon wafer can be made with an epoxy adhesive, glass frit (either conducting or non- conducting) , a low temperature diffusion bond, or an alloy (eutectic) bond.
  • the thick silicon substrate 16 portion of the bonded wafer is next removed. This is accomplished using an etching process (or a lapping process followed by etching) .
  • the etch is chosen so it will stop at the oxide layer 14 which separates the silicon substrate 16 from the thin film silicon 12 containing the circuitry. It will be understood that many etching methods are possible, for example, a hot KOH solution, plasma etch, or the like.
  • the edge of the thin film 12 is preferably protected from the etch by providing an oxide 28 around the thin film wafer edge 30, the protective oxide being suitably formed during the process of fabricating the circuits.
  • the wafers are next processed through the conventional steps for forming Al bonding pads 34a and Indium bumps 34b for interconnection to the detector, shown generally as 36.
  • the Al bonding pads 34a and the In bumps 34b contact the feedthroughs 20 which contact appropriate portions of the circuit within the thin film layer 12.
  • the In bumps 34b are mated with and cold welded to corresponding In bumps 36a of the detector 36 in a conventional and well known bump bonding procedure.
  • IR radiation is incident upon the detector 36 and is converted therein into detectable charge carriers.
  • the charge carriers are collected under the influence of a bias voltage and are provided, via the In bump interconnects, to the circuits fabricated within the thin film layer 12 for amplification and readout.
  • Figs. 2a-2e illustrate a double transfer method of the invention. Processing begins with a bonded silicon wafer 40.
  • the wafer 40 includes a silicon substrate 42, a layer of silicon dioxide 44, and a thinned silicon layer 46.
  • the thinned silicon layer 46 has been processed to form the required readout circuitry and contact pads 46'.
  • bonded silicon wafer 40 is attached to a temporary carrier substrate 50 with a layer of adhesive or wax 48.
  • the silicon substrate 42 is removed by a suitable process, such as by etching with KOH.
  • the temporary carrier substrate 50 provides mechanical support for the thinned silicon layer 46.
  • the silicon dioxide layer 44 functions as an etch stop to terminate the etching process after the silicon substrate 40 has been removed.
  • Fig. 2d the structure fabricated thus far, including the temporary carrier substrate 50, is bonded to a final carrier substrate 54 with a layer 52 of, by example, epoxy adhesive that is applied between the silicon dioxide layer 44 and the carrier substrate 54.
  • the bonding layer 48 is removed, which also removes the temporary carrier substrate 50.
  • a heating process is employed to melt the wax, thereby releasing the temporary substrate 50.
  • the substrate 54 which is comprised of a material that is selected so as to cause the effective coefficient of thermal expansion of the readout chip assembly to match (within approximately 20%) the coefficient of thermal expansion of the material of the radiation detector.
  • suitable substrate 54 materials include GaAs, CdTe, Ge, and a-plane sapphire. Processing continues as described above to form indium bump interconnects 34b for eventual hybridization of the readout integrated circuit assembly with a detector array (not shown) .
  • the readout chip assembly combination comprised of the Si layer 12 or 46, the epoxy adhesive layer 26 or 52, and the substrate 24 or 54, has an effective coefficient of thermal expansion that is selected to approximately match the coefficient of thermal expansion of the detector material.
  • the readout chip and the detector will each shrink at approximately the same rate during cooling, and ui.due bowing and stress upon the assemblies and interconnects (indium bumps) is avoided at the desired operating temperature.
  • epoxy adhesives have a coefficient of thermal expansion in the range of 30-50 X 10 *6 m/mK
  • HgCdTe has a coefficient of thermal expansion in the range of 3.8-4.5 X 10 *6 m/mK
  • Si has a coefficient of thermal expansion of approximately 1.2 X 10 * * m/mK
  • GaAs has a coefficient of thermal expansion in the range of 4.5-5.9 X 10 *6 m/mK
  • Ge has a coefficient of thermal expansion in the range of 5.5- 6.4 X 10 *6 m/mK
  • a-plane sapphire has a coefficient of thermal expansion in the range of 3.5-7.5 X 10 '6 m/mK.
  • the adhesive layer 26 preferably has a thickness that is approximately equal to the thickness of the Si layer 12, and the epoxy adhesive is selected to be one having low outgas ⁇ ing at approximately 77K under vacuum conditions.
  • the detector assembly 36 is comprised of HgCdTe
  • the readout chip assembly is a multilayered structure comprised of a 10 micrometer thick layer of Si, a 10 micrometer thick layer of epoxy adhesive, and a 525 micrometer thick layer of GaAs.
  • the effective coefficient of thermal expansion and contraction of the readout chip assembly is within 20% of the coefficient of thermal expansion and contraction of the HgCdTe material of the detector assembly, which is the desired result.
  • the assembly that results from the execution of either the first or second methods features silicon-based readout circuitry bonded to a non- silicon substrate, wherein the non-silicon substrate is comprised of a material that is selected, in combination with the Si circuit layer and the bonding material, to approximately match the thermal expansion characteristics of the detector material.
  • the assembly is suitable for mating with a radiation detector comprised of a Group II-VI material, such as HgCdTe.
  • the material of the substrate is selected from the group consisting of a Group III-V material, such as GaAs; a Group II-VI material, such as CdTe; a Group IV material, such as Ge; and a-plane sapphire.

Abstract

An integrated circuit assembly includes a silicon thin film circuit bonded to a substrate of a material selected to provide the assembly with an effective thermal expansion characteristic that approximately matches that of another device, such as HgCdTe detector. The assembly, when bump bonded with the device, is resistant to failure when subjected to thermal cycling. A first method for manufacturing the assembly includes the steps of forming a desired circuit in a thin layer (12) of silicon on a silicon substrate of a bonded silicon wafer. The thin silicon layer including the circuit is then bonded to the selected substrate material (24). Thereafter the silicon substrate is removed and the resulting assembly may be mated to the device (36). A second method employs a two stage transfer technique wherein the processed thin silicon layer is bonded to a first, temporary substrate; the silicon substrate is removed; a second, permanent substrate is attached; and the first substrate is removed. The second substrate is comprised of a material selected for providing the assembly with a coefficient of thermal expansion that is matched to the material of the device.

Description

THERMALLY MATCHED READOUT/DETECTOR ASSEMBLY AND METHOD FOR FABRICATING SAME
FIELD OF THE INVENTION:
The invention relates to integrated circuit manufacturing technology and more particularly to methods for fabricating readout chips for use in sensor chip assemblies (SCA's).
BACKGROUND OF THE INVENTION:
Sensor Chip Assemblies are key components in Infrared (IR) detection systems. However, a significant problem exists for the current sensor chip assemblies that include silicon readout chips which are mated to, or hybridized with, Group II-VI material IR detectors, such as those comprised of HgCdTe. Due to the significant difference in the coefficient of thermal expansion of Si and HgCdTe, it has been found that these assemblies are unable to survive a large number («1000) of thermal cycles between room temperature and operating temperature («77K) . One typical failure mode results in a deterioration of the electrical conductors, such as indium bumps, that are used to hybridize the readout chip to the detector chip.
The failure of SCAs as a result of thermal cycling has heretofore impeded the use of HgCdTe direct hybrid SCAs in production programs.
it is known to make three-dimensional circuits in bulk silicon and thin layers of silicon bonded thereto as described, for example, by Hayashi et. al. in a paper entitled "Cumulatively Bonded IC Devices Stacking Thin Film DUAL-CMOS Functional Blocks" presented at the 1990 Symposium on VLSI Technology.
As was noted above, it has been found that the SCA's tend to fail because the silicon readout chips and the detector chips have different thermal expansion coefficients. Thus, the use of three-dimensional, same material circuits a known from Hayashi et.al. is not helpful because of th mismatch in thermal expansion coefficients between th silicon of the readout chip and the detector material.
It is therefore an object of the invention to provide a integrated circuit assembly which overcomes the problem o failure due to thermal cycling.
It is another object of this invention to provide practical, inexpensive method for adjusting the effectiv thermal expansion coefficient of a readout integrate circuit assembly.
SUMMARY OF THE INVENTION
The foregoing and other problems are overcome and th objects of the invention are realized by a chip assembl for hybridization, or bump bonding, with another devic having a determined thermal expansion characteristic, th assembly comprising a silicon thin film circuit bonded t a substrate of a material selected so as to match th thermal expansion characteristic of the readout chi assembly to the thermal expansion characteristic of th other device.
In the preferred embodiment, the device is a radiatio detector comprised of a Group II-VI material, such a HgCdTe.
In another aspect of the invention there are provided methods for manufacturing a chip assembly. A first method, referred to herein as a thin film transfer method, includes the steps of providing a bonded silicon wafer whic includes a thin layer of silicon on a silicon substrate; forming a circuit in the thin silicon layer; forming a least one electrical feedthrough in the thin silicon layer; bonding the thin silicon layer, including the circuit, to a selected substrate comprising a material selected for thermally matching the chip assembly to another material to be hybridized therewith; and thereafter removing the silicon substrate.
A second method, referred to herein as a double transfer method, includes the steps of providing a bonded silicon wafer which includes a thin layer of silicon on a silicon substrate; forming a circuit in the thin silicon layer; bonding the thin silicon layer, including the circuit, to a selected temporary carrier substrate; removing the silicon substrate; bonding the thin silicon layer to a final substrate that is comprised of a material selected for thermally matching the readout chip assembly to another material to be hybridized therewith; and thereafter removing the temporary carrier substrate.
It will be appreciated that this invention also allows processing (e.g. depositing and patterning thin films) on both sides of the active silicon film. This improves layout density, makes possible new and novel transistor structures and provides superior RF shielding.
In accordance with this invention, it is possible to process the active circuits in thin silicon (0.2-4 microns thick) films, as well as performing low temperature (below 450 ) processing steps (e.g. deposit and pattern metal, low temperature insulating film, etc.) on the backside of the thin silicon film. This technique provides the advantage of higher device density because of an extra layer of interconnection available on the back surface, fabricating novel devices such as a dual gate MOS transistor, and superior RF shielding by providing shielding layers on both sides of the active circuitry.
As brought out above, the silicon film thickness for active devices may be very thin (»0.2 micron). These very thin films provide superior radiation hardness and facilitate operation of the MOS transistors in a fully depleted mode to provide higher performance.
It will also be understood that this invention also has the advantage of being applicable to any detector material, and is not limited for use with Group III-V material, such as HgCdTe.
BRIEF DESCRIPTION OF THE DRAWING
The above set forth and other features of the invention are made more apparent in the ensuing Detailed Description of the Invention when read in conjunction with the attached Drawing, wherein:
Figs, la through Id are cross-sectional views (not t scale) that illustrate processing steps of a first metho of the invention, specifically a thin film transfer method, wherein,
Fig. la is a cross section of a wafer illustrating the initial stage of fabrication of a chip assembly i accordance with the invention;
Fig. lb is a cross section illustrating an example of a feedthrough;
Fig. lc is a cross sectional view with the circuits fabricated and the wafer attached to the chosen substrate in accordance with the invention;
Fig. Id is a simplified cross section of the assembly in accordance with the invention; and
Figs. 2a through 2e are cross-sectional views, not to scale, that illustrate a second method of the invention, specifically a double transfer method. DETAILED DESCRIPTION OF THE INVENTION
The method for making an assembly in accordance with the first or second methods of the invention begins with a bonded silicon wafer as illustrated in cross-section at 10 in Fig. la. The wafer 10 comprises a thin, preferably 0.2- 10 micrometers thick, film 12 made of single crystal silicon of bulk silicon quality on top of a layer of thermal SiO_, as shown at 14. It will be understood that the thickness of the SiO- layer is not critical and would typically be in the range 0.1 - 1.5 microns. The films 12 and 14 are disposed on top of a normal bulk silicon wafer illustrated at 16.
The wafer 10 may be purchased commercially, or may be fabricated by providing two silicon wafers, depositing the silicon dioxide layer on a surface of one, and then fusion bonding (~1200 degrees C) the two wafers together with the layer of silicon dioxide interposed between the two wafers. One of the wafers is then thinned to a desired thickness in the range of a fraction of a micrometer to 50 micrometers. Thinning can be accomplished by a mechanical grinding process that is optionally followed by a plasma etching process.
Conventional readout circuits (not seen in Fig. lb) are processed in the thin film 12 using conventional methods disclosed, for example, by Hayashi, et al. previously cited. Conventional readout circuits can include transimpedance amplifiers, signal multiplexers, and the like of a type conventionally used for interfacing to an array of IR radiation detectors. Processing continues through the step of depositing an overglass layer (shown in Fig. lc at 18), and includes the addition of electrical feedthroughs illustrated in Fig. lb at 20.
It will be understood that the electrical feedthroughs illustrated at 20 can be incorporated at any convenient part of the process, though preferably at an early stage in the process. In the preferred approach as illustrated in Fig. lb, the feedthroughs 20 are made by etching trenches through the thin silicon layer 12 to the oxide layer 14 below.
It will be appreciated by those skilled in the art that because of the arrangement of the layers that the etching step is readily accomplished because the oxide acts as an etch stop. The trench walls indicated at 22 are then oxidized using a conventional thermal oxidation process. The trench hole is then filled with a conductive material. Doped polycrystalline silicon (polysilicon) is used as the conductive material, but other materials, such as, for example, tungsten, may also be used if desired. An alternative feedthrough arrangement may be fabricated by using the doped single crystal silicon layer itself and isolating a portion with a trench.
Fig. lc shows illustrative examples of devices fabricated in the thin film 12. As seen in Fig. lc, the structure formed thus far has been processed to form N-type and P- type regions, as required for the particular circuit application, within the silicon film 12. These regions may be delineated through a photolithographic process and are formed through a diffusion or an implantation step. Subsequent to doping the silicon film 12 both p+ and n+ regions are also photolithographically defined and diffused or implanted. One or more polysilicon gate electrodes 17 may be also deposited, as required. A further layer of SiO- shown at 14' may be formed to bury the gate electrodes 17. An electrically insulating overglass layer 18 may also be deposited in a conventional manner.
The bonded wafer 10 with the circuits fabricated (Fig. lc) is next attached as seen in Fig. Id to a substrate 24 which is chosen to have a coefficient of thermal expansion that is selected for providing the resultant readout chip assembly with an effective coefficient of thermal expansion that is approximately the same as the coefficient of thermal expansion of the intended detector chip. For example, in the case of HgCdTe detectors, suitable substrate materials have been found to include GaAs, CdTe, Ge, and a-plane sapphire. Preferably, the effective coefficient of thermal expansion of the readout integrated circuit assembly is within approximately 20% of the coefficient of thermal expansion of the detector material so as to avoid deleterious effects due to thermal cycling.
The attachment at 26 of the' substrate 24 to the thin film silicon side of the bonded silicon wafer can be made with an epoxy adhesive, glass frit (either conducting or non- conducting) , a low temperature diffusion bond, or an alloy (eutectic) bond.
The thick silicon substrate 16 portion of the bonded wafer is next removed. This is accomplished using an etching process (or a lapping process followed by etching) . The etch is chosen so it will stop at the oxide layer 14 which separates the silicon substrate 16 from the thin film silicon 12 containing the circuitry. It will be understood that many etching methods are possible, for example, a hot KOH solution, plasma etch, or the like. The edge of the thin film 12 is preferably protected from the etch by providing an oxide 28 around the thin film wafer edge 30, the protective oxide being suitably formed during the process of fabricating the circuits.
As best seen in the simplified cross section shown in Fig. Id, the wafers are next processed through the conventional steps for forming Al bonding pads 34a and Indium bumps 34b for interconnection to the detector, shown generally as 36. The Al bonding pads 34a and the In bumps 34b contact the feedthroughs 20 which contact appropriate portions of the circuit within the thin film layer 12. The In bumps 34b are mated with and cold welded to corresponding In bumps 36a of the detector 36 in a conventional and well known bump bonding procedure.
During use, IR radiation is incident upon the detector 36 and is converted therein into detectable charge carriers. The charge carriers are collected under the influence of a bias voltage and are provided, via the In bump interconnects, to the circuits fabricated within the thin film layer 12 for amplification and readout.
Reference is now made to Figs. 2a-2e which illustrate a double transfer method of the invention. Processing begins with a bonded silicon wafer 40. The wafer 40 includes a silicon substrate 42, a layer of silicon dioxide 44, and a thinned silicon layer 46. In Fig. 2a the thinned silicon layer 46 has been processed to form the required readout circuitry and contact pads 46'.
In Fig. 2b the bonded silicon wafer 40 is attached to a temporary carrier substrate 50 with a layer of adhesive or wax 48.
In Fig. 2c the silicon substrate 42 is removed by a suitable process, such as by etching with KOH. During the etching process the temporary carrier substrate 50 provides mechanical support for the thinned silicon layer 46. The silicon dioxide layer 44 functions as an etch stop to terminate the etching process after the silicon substrate 40 has been removed.
In Fig. 2d the structure fabricated thus far, including the temporary carrier substrate 50, is bonded to a final carrier substrate 54 with a layer 52 of, by example, epoxy adhesive that is applied between the silicon dioxide layer 44 and the carrier substrate 54.
In Fig. 2e the bonding layer 48 is removed, which also removes the temporary carrier substrate 50. By example, if a wax is used for the layer 48 then a heating process is employed to melt the wax, thereby releasing the temporary substrate 50. This leaves the thinned silicon layer 46, having the readout circuitry, bonded to the substrate 54 which is comprised of a material that is selected so as to cause the effective coefficient of thermal expansion of the readout chip assembly to match (within approximately 20%) the coefficient of thermal expansion of the material of the radiation detector. As was described previously, for a radiation detector comprised of HgCdTe suitable substrate 54 materials include GaAs, CdTe, Ge, and a-plane sapphire. Processing continues as described above to form indium bump interconnects 34b for eventual hybridization of the readout integrated circuit assembly with a detector array (not shown) .
By example, for a HgCdTe detector assembly that is operated within the range of approximately 65K to approximately 85K, the readout chip assembly combination comprised of the Si layer 12 or 46, the epoxy adhesive layer 26 or 52, and the substrate 24 or 54, has an effective coefficient of thermal expansion that is selected to approximately match the coefficient of thermal expansion of the detector material. As a result, the readout chip and the detector will each shrink at approximately the same rate during cooling, and ui.due bowing and stress upon the assemblies and interconnects (indium bumps) is avoided at the desired operating temperature.
In general, epoxy adhesives have a coefficient of thermal expansion in the range of 30-50 X 10*6 m/mK, HgCdTe has a coefficient of thermal expansion in the range of 3.8-4.5 X 10*6 m/mK, Si has a coefficient of thermal expansion of approximately 1.2 X 10** m/mK, GaAs has a coefficient of thermal expansion in the range of 4.5-5.9 X 10*6 m/mK, Ge has a coefficient of thermal expansion in the range of 5.5- 6.4 X 10*6 m/mK, and a-plane sapphire has a coefficient of thermal expansion in the range of 3.5-7.5 X 10'6 m/mK. If an epoxy adhesive is employed, the adhesive layer 26 preferably has a thickness that is approximately equal to the thickness of the Si layer 12, and the epoxy adhesive is selected to be one having low outgasεing at approximately 77K under vacuum conditions.
In an exemplary embodiment the detector assembly 36 is comprised of HgCdTe, and the readout chip assembly is a multilayered structure comprised of a 10 micrometer thick layer of Si, a 10 micrometer thick layer of epoxy adhesive, and a 525 micrometer thick layer of GaAs. The effective coefficient of thermal expansion and contraction of the readout chip assembly is within 20% of the coefficient of thermal expansion and contraction of the HgCdTe material of the detector assembly, which is the desired result.
It will be appreciated that the assembly that results from the execution of either the first or second methods features silicon-based readout circuitry bonded to a non- silicon substrate, wherein the non-silicon substrate is comprised of a material that is selected, in combination with the Si circuit layer and the bonding material, to approximately match the thermal expansion characteristics of the detector material. The assembly is suitable for mating with a radiation detector comprised of a Group II-VI material, such as HgCdTe. The material of the substrate is selected from the group consisting of a Group III-V material, such as GaAs; a Group II-VI material, such as CdTe; a Group IV material, such as Ge; and a-plane sapphire.
While the invention has been particularly shown and described with respect to preferred embodiments thereof,, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope and spirit of the invention.

Claims

CLAIMSWhat is claimed is:
1. A method for manufacturing an integrated circuit assembly, comprising the steps of:
providing a bonded silicon wafer which includes a layer of silicon on a silicon substrate;
forming a circuit in said silicon layer;
bonding said silicon layer including said circuit to a substrate comprising a material selected for providing the integrated circuit assembly with an effective coefficient of thermal expansion that is similar to that of another material to be attached to the integrated circuit assembly; and
removing the silicon substrate.
2. The method of claim 1 wherein the bonded silicon wafer includes a layer of SiO. that is interposed the silicon substrate and the layer of silicon.
3. The method of claim 2 further comprising the step of forming a layer of silicon oxide around the edge of the silicon layer to protect the thin silicon layer.
4. The method of claim 3 wherein the silicon is removed by an etch chosen to stop at the silicon oxide.
5. The method of claim 1 wherein the step of forming a circuit includes a step of forming at least one electrical feedthrough, the step of forming at least one electrical feedthrough including the steps of providing a trench in the layer of silicon, providing an oxide at the edges of the trench, and filling the trench with an electrically conducting material.
6. The method of claim 5 wherein the electrically conducting material is comprised of doped polycryεtalline silicon.
7. The method of claim 5 and further comprising the steps of forming at least one bonding pad that is electrically coupled to said at least one feedthrough, and forming at least one Indium bump connected to said at least one bonding pad.
8. The method of claim 1 wherein the material to be attached is HgCdTe, and wherein the substrate material is chosen from the group of materials consisting of GaAs, CdTe, Ge, and a-plane sapphire.
9. The method of claim 1 wherein the substrate is bonded using a glass frit.
10. The method of claim 1 wherein the substrate is bonded using an epoxy adhesive.
11. The method of claim 1 wherein the substrate is bonded using a low-temperature diffusion bond.
12. The method of claim 1 wherein the substrate is bonded using an alloy bond.
13. An integrated circuit assembly for bump bonding with a device having a determined thermal expansion characteristic, said assembly comprising a silicon thin film circuit bonded to a substrate comprised of a material that is selected to provide the assembly with a coefficient of thermal expansion that approximately matches the determined thermal expansion characteristic of the device.
14. The assembly of claim 13, wherein said device is comprised of HgCdTe, and wherein the selected substrate material is chosen from the group of materials consisting of GaAs, CdTe, Ge, and a-plane sapphire.
15. The assembly of claim 13 wherein the substrate is bonded using a glass frit.
16. The assembly of claim 13 wherein the substrate is bonded using an epoxy adhesive.
17. The assembly of claim 13 wherein the substrate is bonded using a low-temperature diffusion bond.
18. The assembly of claim 13 wherein the substrate is bonded using an alloy bond.
19. A silicon readout integrated circuit assembly comprising a silicon thin film, said silicon thin film including a readout circuit, and said silicon thin film being bonded to a substrate comprising a material selected to provide said assembly with a thermal expansion characteristic that approximately matches a thermal expansion characteristic of a radiation detector to be bump bonded therewith.
20. The assembly of claim 19 wherein the radiation detector is comprised of HgCdTe, and wherein the selected substrate material is selected from the group of materials consisting of GaAs, CdTe, Ge, and a-plane sapphire.
21. The assembly of claim 19 wherein the selected substrate is bonded using a bonding material selected from the group consisting essentially of a glass frit, an epoxy adhesive, a low-temperature diffusion bond, and an alloy bond .
22. A radiation detector assembly comprising a 2 radiation detector comprised of Group II-VI material and a
3 readout chip assembly bump bonded therewith, said readout
4 chip assembly comprising a silicon thin film, said silicon
5 thin film including a readout circuit, and said silicon
6 thin film being bonded to a substrate comprising a material selected to provide said readout chip assembly with a
8 thermal expansion characteristic that is similar to a
9 thermal expansion characteristic of the radiation detector.
1 23. The assembly of claim 22 wherein the radiation
2 detector is comprised of HgCdTe, and wherein the selected
3 substrate material is selected from the group of materials
4 consisting of GaAs, CdTe, Ge, and a-plane sapphire.
1 24. A method of fabricating an integrated circuit
2 assembly, comprising the steps of:
3 providing a bonded silicon wafer which includes a
4 layer of silicon on a silicon substrate, said layer of
5 silicon having a first surface and an opposing second
6 surface;
forming a circuit in said silicon layer;
8 bonding the first surface of said silicon layer
9 including said circuit to a first substrate;
10 removing said silicon substrate;
H bonding a second substrate over the second surface of
12 said silicon layer, the second substrate being
13 comprised of a material selected for providing the
14 integrated circuit assembly with a thermal expansion
15 characteristic that is similar to a thermal expansion
16 characteristic of another material to be attached to
17 the readout circuit assembly; and
,β removing the first substrate. 1 25. The method of claim 24 wherein the bonded silicon
2 wafer further includes a layer of dielectric material that
3 is interposed between said second surface and said silicon
4 substrate, and wherein the step of bonding the second *- substrate includes a step of bonding a surface of the
6 second substrate to a first surface of the layer of
7 dielectric material.
1 26. The method of claim 25 wherein the step of
2 removing the silicon substrate includes a step of exposing
3 the first surface of the dielectric layer.
1 27. The method of claim 24 wherein the material to be
2 attached is comprised of HgCdTe, and wherein the selected
3 substrate material is chosen from the group of materials
4 consisting of GaAs, CdTe, Ge, and a-plane sapphire.
1 28. A readout circuit and radiation detector
2 assembly, comprising:
3 a radiation detector comprised of a material having a characteristic coefficient of thermal expansion and contraction; and
a multilayered readout circuit assembly having an effective coefficient of thermal expansion and contraction that is similar to that of the radiation detector.
29. An assembly as set forth in Claim 28 wherein the multilayered readout circuit assembly is comprised of a layer of silicon having readout circuitry fabricated therein; a substrate comprised of a material other than silicon; and a bonding layer that is interposed between the layer of silicon and the substrate.
30. An assembly as set forth in Claim 29 wherein the radiation detector is comprised of a Group II-VI material, and wherein the material of the substrate is selected from the group consisting of a Group III-V material, a Group II- VI material, a Group IV material, and a-plane sapphire.
PCT/US1994/000370 1993-01-19 1994-01-10 Thermally matched readout/detector assembly and method for fabricating same WO1994017557A1 (en)

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DE19546423C1 (en) * 1995-12-12 1997-02-20 Siemens Ag Radiation sensitive transducer e.g. CCD or photodiode array
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US7821106B2 (en) 2001-08-24 2010-10-26 Schott Ag Process for making contact with and housing integrated circuits
US8349707B2 (en) 2001-08-24 2013-01-08 Wafer-Level Packaging Portfolio Llc Process for making contact with and housing integrated circuits
US7880179B2 (en) 2001-08-24 2011-02-01 Wafer-Level Packaging Portfolio Llc Process for making contact with and housing integrated circuits
US7700957B2 (en) 2001-08-24 2010-04-20 Schott Ag Process for making contact with and housing integrated circuits
WO2003038492A3 (en) * 2001-10-26 2003-10-23 Massachusetts Inst Technology Hybrid integration of electrical and optical chips
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WO2003038492A2 (en) * 2001-10-26 2003-05-08 Massachusetts Institute Of Technology Hybrid integration of electrical and optical chips
US7723815B1 (en) * 2004-07-09 2010-05-25 Raytheon Company Wafer bonded composite structure for thermally matching a readout circuit (ROIC) and an infrared detector chip both during and after hybridization
US8154099B2 (en) 2009-08-19 2012-04-10 Raytheon Company Composite semiconductor structure formed using atomic bonding and adapted to alter the rate of thermal expansion of a substrate
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US10644061B2 (en) 2015-12-06 2020-05-05 Semi Conductor Devices—An Elbit Systems-Rafael Partnership Photodetector-arrays and methods of fabrication thereof
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US11393869B2 (en) 2019-02-26 2022-07-19 Raytheon Company Wafer level shim processing

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