JPH03266478A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03266478A JPH03266478A JP2066016A JP6601690A JPH03266478A JP H03266478 A JPH03266478 A JP H03266478A JP 2066016 A JP2066016 A JP 2066016A JP 6601690 A JP6601690 A JP 6601690A JP H03266478 A JPH03266478 A JP H03266478A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- substrate
- thermal expansion
- semiconductor device
- crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 239000013078 crystal Substances 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 abstract description 18
- 239000002184 metal Substances 0.000 abstract description 18
- 229910052594 sapphire Inorganic materials 0.000 abstract description 14
- 239000010980 sapphire Substances 0.000 abstract description 14
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000005083 Zinc sulfide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 229910052984 zinc sulfide Inorganic materials 0.000 description 1
- DRDVZXDWVBGGMH-UHFFFAOYSA-N zinc;sulfide Chemical compound [S-2].[Zn+2] DRDVZXDWVBGGMH-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体装置に関し、
異なる半導体基板に形成し、電気的に接続した光検知素
子と信号処理素子とがら成る半導体装置が、該装置の動
作時の低温状態の環境と、非動作時の常温状態の間の温
度履歴による熱歪によって両方の素子に位置ずれが生じ
ないようにした半導体装置を目的とし、
熱膨張率が接近した、或いは熱膨張率が等しい支持基板
にそれぞれ熱膨張率の異なる半導体結晶を成長、或いは
接着して第1の半導体基板、および第2の半導体基板を
設け、該半導体基板の各々に光検知素子、および信号処
理素子を設け、該素子間を電気的に接続して構成する。[Detailed Description of the Invention] [Summary] Regarding a semiconductor device, a semiconductor device consisting of a photodetector element and a signal processing element formed on different semiconductor substrates and electrically connected is exposed to a low temperature environment during operation of the device. The purpose of the semiconductor device is to prevent misalignment of both elements due to thermal strain due to temperature history during non-operating room temperature conditions, and a supporting substrate with similar or equal coefficients of thermal expansion. A first semiconductor substrate and a second semiconductor substrate are provided by growing or adhering semiconductor crystals having different coefficients of thermal expansion, respectively, a photodetecting element and a signal processing element are provided on each of the semiconductor substrates, and a photodetecting element and a signal processing element are provided on each of the semiconductor substrates. It is configured by electrically connecting between the two.
本発明は半導体装置に係り、特に第1の半導体素子と第
2の半導体素子とを金属バンプにて結合した半導体装置
に関する。The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a first semiconductor element and a second semiconductor element are bonded by metal bumps.
エネルギーバンドギャップの狭い化合物半導体基板に光
検知素子を形成し、また酸化膜等の絶縁膜の形成が容易
なシリコン(Si)等の半導体基板に信号処理素子を形
成し、両者を金属バンプにて電気的に結合した半導体装
置が形成されている。A photodetector element is formed on a compound semiconductor substrate with a narrow energy bandgap, and a signal processing element is formed on a semiconductor substrate made of silicon (Si), on which insulating films such as oxide films can be easily formed, and both are connected using metal bumps. An electrically coupled semiconductor device is formed.
このような半導体装置として特願昭63−308970
号に於いて第2図に示すように、P型の水銀・カドミウ
ム・テルル(Hg+−x Cdx Te)の基板1にN
型層2を形成して光検知素子を形成する。またこのP型
のHg+−x caX Te基板1に熱膨張率が接近し
たインジウム・アンチモン(InSb)基板3に電荷転
送素子を形成し、この電荷転送素子の入力ダイオード4
と前記光検知素子とを金属バンプ5を用いて電気的に接
続した半導体装置を提案している。As such a semiconductor device, patent application No. 63-308970
As shown in Figure 2 in the issue, N was added to a P-type mercury-cadmium-tellurium (Hg+-x Cdx Te) substrate 1.
A mold layer 2 is formed to form a photodetector element. Further, a charge transfer element is formed on an indium antimony (InSb) substrate 3 whose coefficient of thermal expansion is close to that of this P-type Hg+-x caX Te substrate 1, and an input diode 4 of this charge transfer element is formed.
A semiconductor device is proposed in which the photodetector and the photodetector are electrically connected using metal bumps 5.
このようにして上記光検知素子を形成した基板と、電荷
転送素子を形成した基板の熱膨張率差を少なくすること
で、前記半導体装置を77°にの低温で動作させる時の
環境と、該装置を非動作時の常温にした時の環境の温度
履歴によって上記素子を形成した基板で発生する熱歪の
差を小さくして、上記両方の素子を接続している金属バ
ンプに位置ズレを発生しないようにしている。In this way, by reducing the difference in thermal expansion coefficient between the substrate on which the photodetector element is formed and the substrate on which the charge transfer element is formed, the environment when the semiconductor device is operated at a low temperature of 77 degrees, The difference in thermal strain that occurs on the substrate on which the above elements are formed is reduced due to the temperature history of the environment when the device is brought to room temperature when not in operation, causing positional deviations in the metal bumps that connect both of the above elements. I try not to.
なお、第2図で6は電荷を蓄積するN型のウェル領域、
7はトランスファーゲート電極、8は電荷転送装置の転
送電極、9および10は各基板上に形成した絶縁膜であ
る。In addition, in FIG. 2, 6 is an N-type well region for accumulating charges;
7 is a transfer gate electrode, 8 is a transfer electrode of a charge transfer device, and 9 and 10 are insulating films formed on each substrate.
然し、上記したInSb基板3に電荷転送素子を形成す
るために該基板上に絶縁膜9や転送電極8等を形成する
技術は、Si基板に絶縁膜や転送電極を形成する技術に
比して確立しておらず、電荷転送素子の製造が容易でな
い難点がある。However, the technique of forming the insulating film 9, transfer electrode 8, etc. on the above-mentioned InSb substrate 3 in order to form a charge transfer element on the substrate is slower than the technique of forming the insulating film and transfer electrode on the Si substrate. This method has not been established yet, and there is a drawback that it is not easy to manufacture charge transfer devices.
本発明は上記した問題点を除去し、製造が容易でかつ両
者の素子を形成した基板が温度変動に対して熱歪の差が
小さく、両者の素子を結合している金属バンプに位置ず
れを生じないようにした半導体装置の提供を目的とする
。The present invention eliminates the above-mentioned problems, is easy to manufacture, and the substrate on which both elements are formed has a small difference in thermal distortion due to temperature fluctuations, and the metal bumps that connect the two elements are free from misalignment. An object of the present invention is to provide a semiconductor device in which this phenomenon does not occur.
上記目的を達成する本発明の半導体装置は、熱膨張率が
接近した、或いは熱膨張率が等しい支持基板にそれぞれ
熱膨張率の異なる半導体結晶を成長、或いは接着して第
1の半導体基板、および第2の半導体基板と成し、該半
導体基板の各々に光検知素子、および信号処理素子を設
け、該素子間を電気的に接続したことを特徴としている
。A semiconductor device of the present invention that achieves the above object includes a first semiconductor substrate, in which semiconductor crystals having different coefficients of thermal expansion are grown or adhered to a support substrate having close or equal coefficients of thermal expansion, and A second semiconductor substrate is formed, a photodetecting element and a signal processing element are provided on each of the semiconductor substrates, and the elements are electrically connected.
[作 用]
本発明の半導体装置は光検知素子を形成する半導体基板
をサファイア(Al!zo3)より成る支持基板にIn
Sb結晶を設けて形成する。また電荷転送素子を形成す
る半導体基板を前記サファイアより成る支持基板にSi
結晶を設けて形成する。[Function] In the semiconductor device of the present invention, a semiconductor substrate forming a photodetecting element is injected into a support substrate made of sapphire (Al!zo3).
A Sb crystal is provided and formed. Further, the semiconductor substrate forming the charge transfer element is placed on the supporting substrate made of sapphire.
Provide and form crystals.
上記サファイア基板に形成したSi結晶はICやLSI
等の半導体装置に用いられており、上記電荷転送素子を
形成するための絶縁膜、つまりSin。The Si crystal formed on the above sapphire substrate is used for IC and LSI.
An insulating film, ie, Sin, is used in semiconductor devices such as, for forming the charge transfer element.
膜や、転送電極の製造技術は確立しており、高品質の電
荷転送素子が容易に得られる。The manufacturing technology for films and transfer electrodes has been established, and high-quality charge transfer elements can be easily obtained.
また上記InSb結晶の熱膨張率は、300°Kから8
0°にの温度変動で0.06%収縮するが、一方、Si
では0.03%しか収縮しない。In addition, the thermal expansion coefficient of the above InSb crystal is 8 from 300°K.
It shrinks by 0.06% due to temperature fluctuation to 0°, but on the other hand, Si
In this case, the shrinkage is only 0.03%.
この両者の結晶の間の熱膨張率の差は大であっても、上
記結晶を形成している支持基板は同一のサファイア基板
を使用しており、このサファイア基板の厚さは両者の結
晶の厚さに比較して温かに大きいために、上記温度変動
の影響はこの支持基板のみが受けるようになり両者の半
導体基板に発生する熱歪の差は生じない。Even though the difference in coefficient of thermal expansion between these two crystals is large, the same sapphire substrate is used as the support substrate forming the above crystals, and the thickness of this sapphire substrate is the same as that of both crystals. Since the temperature is large compared to the thickness, only this supporting substrate is affected by the temperature fluctuation, and there is no difference in thermal strain occurring between the two semiconductor substrates.
また両者の半導体基板に用いる支持基板をそれぞれ熱膨
張率が近接した材料を選択して用いることで両者の素子
を結合している金属バンプの位置ずれが発生しない高信
頼度の半導体装置が得られる。In addition, by selecting and using materials with similar coefficients of thermal expansion for the support substrates used for both semiconductor substrates, a highly reliable semiconductor device can be obtained in which the metal bumps that connect the elements of both devices are not misaligned. .
以下、図面を用いて本発明の一実施例につき詳細に説明
する。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第1図は本発明の半導体装置の一実施例を示す断面図で
ある。FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the present invention.
第1図に図示するように、サファイアより成る支持基板
ll上には、10μ蒙程度の厚さでN型のIn5b結晶
より成る第1の半導体結晶12が気相エピタキシャル成
長方法等を用いて形成されて第1の半導体基板13が形
成され、該基板の所定位置にマグネシウム(Mg)イオ
ンがイオン注入されて、P′″領域14が形成されてい
る。As shown in FIG. 1, a first semiconductor crystal 12 made of N-type In5b crystal with a thickness of about 10 μm is formed on a supporting substrate 11 made of sapphire using a vapor phase epitaxial growth method or the like. A first semiconductor substrate 13 is formed, and magnesium (Mg) ions are implanted into predetermined positions of the substrate to form a P'' region 14.
このサファイアよりなる支持基板11は300°により
80°にの間で0.06%収縮する。The supporting substrate 11 made of sapphire shrinks by 0.06% between 300° and 80°.
そして第1の半導体基板13の表面には硫化亜鉛(Zn
S)膜よりなる絶縁膜15が形成され、該絶縁膜のP″
頭域14上が開口されて、該領域上には接続パッドと成
るInよりなる金属電極16が形成されている。The surface of the first semiconductor substrate 13 is coated with zinc sulfide (Zn
An insulating film 15 made of S) film is formed, and P″ of the insulating film
An opening is formed above the head region 14, and a metal electrode 16 made of In, which serves as a connection pad, is formed on the region.
一方、サファイアより成る他方の支持基板21上には、
N型のSiのエピタキシャル結晶よりなる第2の半導体
結晶22が気相成長方法により形成され、第2の半導体
基板23が形成されている。この第2の半導体基板23
の表面には5i02膜24が形成され、図示しないが電
荷転送装置のトランスファーゲート電極や、転送電極が
形成され、また第2の半導体基板にはP型の不純物が導
入されて電荷転送装置の入力ダイオード25が形成され
ている。そして該入力ダイオード25上が開口されて接
続パッドとなるA2の金属電極26が形成されている。On the other hand, on the other support substrate 21 made of sapphire,
A second semiconductor crystal 22 made of N-type Si epitaxial crystal is formed by a vapor phase growth method, and a second semiconductor substrate 23 is formed. This second semiconductor substrate 23
A 5i02 film 24 is formed on the surface of the second semiconductor substrate, and a transfer gate electrode and a transfer electrode of the charge transfer device (not shown) are formed on the surface of the second semiconductor substrate. A diode 25 is formed. An opening is formed above the input diode 25 to form a metal electrode 26 of A2 which becomes a connection pad.
そしてこれらの接続パッドとなる金属電極16.26上
には、それぞれInよりなる金属バンプ27.28が1
着により形成され、これらの金属バンプ27,28が圧
着接続されている。Metal bumps 27 and 28 made of In are placed on each of the metal electrodes 16 and 26 that serve as connection pads.
These metal bumps 27 and 28 are connected by pressure bonding.
このような本発明の半導体装置によれば、該装置に用い
る半導体基板は同一の材料で形成された支持基板11.
21上にそれぞれの素子形成用の半導体結晶12.22
を、前記支持基板11.21の厚さより極めて薄く形成
しており、上記素子形成用の半導体結晶の熱膨張率の差
の影響を殆ど受けない。According to the semiconductor device of the present invention, the semiconductor substrates used in the device include the supporting substrates 11.
Semiconductor crystals 12 and 22 for forming each element on 21
is formed to be extremely thinner than the thickness of the support substrate 11.21, and is hardly affected by the difference in thermal expansion coefficient of the semiconductor crystal for forming the element.
そのためこの第1、第2の半導体基板を用いて形成した
半導体装置を77°にの温度に冷却して動作させた後、
常温の非動作時の温度にした時の温度履歴による両者の
半導体基板の熱歪の差は無いので、金属バンプの位置ず
れのような現象は生じず、高信顛度の半導体装置が得ら
れる。Therefore, after cooling the semiconductor device formed using the first and second semiconductor substrates to a temperature of 77° and operating it,
Since there is no difference in thermal strain between the two semiconductor substrates due to the temperature history when the temperature is set to the non-operating temperature of room temperature, phenomena such as misalignment of metal bumps do not occur, and a semiconductor device with high reliability can be obtained. .
この半導体基板は前記したサファイアの支持基板にIn
Sb結晶基板、或いはSi結晶基板をエピタキシャル成
長する代わりに接着剤等を用いて貼り付け、この結晶基
板を研磨、或いはエツチングして所定の厚さとしても良
い。This semiconductor substrate is made of Indium on the sapphire support substrate mentioned above.
Instead of epitaxially growing an Sb crystal substrate or a Si crystal substrate, it may be attached using an adhesive or the like, and this crystal substrate may be polished or etched to a predetermined thickness.
また第2実施例として上記支持基板11と21として、
サファイア基板の代わりに、Si、或いはGaAs基板
を支持基板として用いても良い。Further, as a second embodiment, as the support substrates 11 and 21,
Instead of the sapphire substrate, a Si or GaAs substrate may be used as the support substrate.
このSiは300°により80” Kの間で0.03%
、GaAs基板は0.06%収縮する。This Si is 0.03% between 80”K by 300°
, the GaAs substrate shrinks by 0.06%.
また第3実施例として支持基板11としてGaAs基板
を用いてその上にInSb結晶を気相エピタキシャル成
長した半導体基板に光検知素子を形成し、支持基板21
としてサファイア基板を用い、その上にSi結晶を気相
エピタキシャル成長した半導体基板に電荷転送素子を形
成する。そしてこの素子間を金属バンプにて接続するよ
うにしても良い。Further, as a third embodiment, a GaAs substrate is used as the support substrate 11, and a photodetector element is formed on a semiconductor substrate on which InSb crystal is grown by vapor phase epitaxial growth.
A charge transfer element is formed on a semiconductor substrate using a sapphire substrate on which a Si crystal is grown by vapor phase epitaxial growth. The elements may be connected using metal bumps.
この場合は上記GaAs基板とサファイア基板の熱膨張
率が接近しており、この両者の支持基板の熱膨張率の差
は、該支持基板上に形成されるInSb結晶およびSi
結晶の熱膨張率の差より小さくなる。In this case, the coefficients of thermal expansion of the GaAs substrate and the sapphire substrate are close to each other, and the difference in coefficient of thermal expansion of the two supporting substrates is due to the difference between the InSb crystal and the Si substrate formed on the supporting substrate.
It is smaller than the difference in thermal expansion coefficient of crystals.
そのため、素子形成用の半導体結晶を支持基板上に形成
した第1および第2の半導体基板は、温度履歴による熱
歪の影響を受けなくなる。Therefore, the first and second semiconductor substrates on which semiconductor crystals for forming elements are formed are not affected by thermal distortion due to temperature history.
以上述べたように、本発明の半導体装置によれば、光検
知素子としての良好な特性が得られる化合物半導体結晶
に光検知素子を形成し、電荷転送素子の形成が容易なS
i結晶に該電荷転送素子を形成し、両者の結晶の熱膨張
係数が異なる場合でも熱膨張率の近接した支持基板に両
者の結晶を成長して半導体装置を形成することで金属バ
ンプが位置ずれしない高信顛度の半導体装置が得られる
。As described above, according to the semiconductor device of the present invention, a photodetecting element is formed in a compound semiconductor crystal that can obtain good characteristics as a photodetecting element, and a charge transfer element can be easily formed using S.
By forming the charge transfer element on an i-crystal, and forming a semiconductor device by growing both crystals on a support substrate with similar thermal expansion coefficients even if the two crystals have different coefficients of thermal expansion, the metal bumps will not be misaligned. A semiconductor device with high reliability can be obtained.
以上の説明から明らかなように本発明によれば、動作時
と非動作時の温度履歴によっても光検知素子と電荷転送
素子とを結合する金属バンプが位置ずれしない高信輔度
の半導体装置が得られる効果がある。As is clear from the above description, according to the present invention, it is possible to obtain a highly reliable semiconductor device in which the metal bumps that connect the photodetecting element and the charge transfer element do not shift in position even depending on the temperature history during operation and non-operation. It has the effect of
第1図は本発明の半導体装置の実施例を示す断面図、
第2図は従来の半導体装置の実施例を示す断面図である
。
図において、
11.21は支持基板、12は第1の半導体結晶、13
は第1の半導体基板、14はP0M域、15は絶縁膜、
16.26は金属電極、22は第2の半導体結晶、23
は第2の半導体基板、24はSiO□膜、25は入力ダ
イオード、27.28は金属バンプを示す。FIG. 1 is a sectional view showing an embodiment of a semiconductor device of the present invention, and FIG. 2 is a sectional view showing an embodiment of a conventional semiconductor device. In the figure, 11.21 is a support substrate, 12 is a first semiconductor crystal, and 13
is a first semiconductor substrate, 14 is a P0M region, 15 is an insulating film,
16. 26 is a metal electrode, 22 is a second semiconductor crystal, 23
24 is a SiO□ film, 25 is an input diode, and 27 and 28 are metal bumps.
Claims (2)
持基板(11、21)にそれぞれ熱膨張率の異なる半導
体結晶(12、22)を成長、或いは接着して第1の半
導体基板(13)、および第2の半導体基板(23)と
成し、該第1および第2の半導体基板の各々に素子を設
け、該素子間を電気的に接続したことを特徴とする半導
体装置。(1) A first semiconductor substrate ( 13) and a second semiconductor substrate (23), an element is provided on each of the first and second semiconductor substrates, and the elements are electrically connected.
A、Bとし、該支持基板(11、12)上に形成される
半導体結晶の熱膨張率をa、bとした時、下記(1)式
の関係が成り立つようにしたことを特徴とする請求項(
1)記載の半導体装置。 A−B<a−b・・・・・・(1) (但し、A<a、B<b)(2) When the coefficients of thermal expansion of each of the support substrates (11, 12) are A and B, and the coefficients of thermal expansion of the semiconductor crystals formed on the support substrates (11, 12) are a and b, A claim characterized in that the following relationship (1) is satisfied (
1) The semiconductor device described. A-B<a-b...(1) (However, A<a, B<b)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2066016A JP2827414B2 (en) | 1990-03-15 | 1990-03-15 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2066016A JP2827414B2 (en) | 1990-03-15 | 1990-03-15 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03266478A true JPH03266478A (en) | 1991-11-27 |
JP2827414B2 JP2827414B2 (en) | 1998-11-25 |
Family
ID=13303717
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2066016A Expired - Lifetime JP2827414B2 (en) | 1990-03-15 | 1990-03-15 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2827414B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994017557A1 (en) * | 1993-01-19 | 1994-08-04 | Hughes Aircraft Company | Thermally matched readout/detector assembly and method for fabricating same |
US7768048B2 (en) | 2003-09-09 | 2010-08-03 | Asahi Kasei Emd Corporation | Infrared sensor IC, and infrared sensor and manufacturing method thereof |
FR3057706A1 (en) * | 2016-10-19 | 2018-04-20 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | METHOD FOR PRODUCING A MICROELECTRONIC CHIP FOR HYBRIDING A SECOND CHIP |
-
1990
- 1990-03-15 JP JP2066016A patent/JP2827414B2/en not_active Expired - Lifetime
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994017557A1 (en) * | 1993-01-19 | 1994-08-04 | Hughes Aircraft Company | Thermally matched readout/detector assembly and method for fabricating same |
GB2279808A (en) * | 1993-01-19 | 1995-01-11 | Hughes Aircraft Co | Thermally matched readout/detector assembly and method for fabricating same |
GB2279808B (en) * | 1993-01-19 | 1996-11-20 | Hughes Aircraft Co | Thermally matched readout/detector assembly and method for fabricating same |
US7768048B2 (en) | 2003-09-09 | 2010-08-03 | Asahi Kasei Emd Corporation | Infrared sensor IC, and infrared sensor and manufacturing method thereof |
FR3057706A1 (en) * | 2016-10-19 | 2018-04-20 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | METHOD FOR PRODUCING A MICROELECTRONIC CHIP FOR HYBRIDING A SECOND CHIP |
WO2018073517A1 (en) * | 2016-10-19 | 2018-04-26 | Commissariat à l'énergie atomique et aux énergies alternatives | Method for the production of a microelectronic chip to be hybridised to a second chip |
US11165005B2 (en) | 2016-10-19 | 2021-11-02 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for producing a microelectronic chip to be hybridised to a second chip |
Also Published As
Publication number | Publication date |
---|---|
JP2827414B2 (en) | 1998-11-25 |
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