JP3114759B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP3114759B2
JP3114759B2 JP04054668A JP5466892A JP3114759B2 JP 3114759 B2 JP3114759 B2 JP 3114759B2 JP 04054668 A JP04054668 A JP 04054668A JP 5466892 A JP5466892 A JP 5466892A JP 3114759 B2 JP3114759 B2 JP 3114759B2
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substrate
semiconductor
semiconductor device
semiconductor substrate
thermal expansion
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JPH05259430A (en
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正二 土肥
博 大工
正彦 成田
博之 若山
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富士通株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は半導体装置に係り、特に化合物半導体基板に形成した光検知素子と、前記化合物半導体基板と異なる熱膨張係数を有する半導体基板に形成され、前記光検知素子で検知された信号を処理する信号処理素子を金属バンプで接合したハイブリッド型の半導体装置に関する。 The present invention relates relates to a semiconductor device, formed on a semiconductor substrate having a light sensing element formed in particular a compound semiconductor substrate, different thermal expansion coefficients between the compound semiconductor substrate, detected by the light sensing element a signal processing device for processing the signals relating to a hybrid type semiconductor device which is joined by a metal bump.

【0002】従来より、エネルギーギャップが狭く、赤外線に高感度を有する水銀・カドミウム・テルル(Hg [0002] than conventional, narrow energy gap, mercury, cadmium and tellurium having a high sensitivity in the infrared (Hg
1-x Cd x Te)のような化合物半導体基板にフォトダイオードのような光検知素子を形成し、該光検知素子で得られた信号を信号処理する電荷転送素子のような信号処理素子をシリコン(Si)基板に形成し、両者の素子をインジウム(In)のような金属バンプで接合したハイブリッド型の固体撮像素子のような光検知装置が形成されている。 1-x Cd x Te) compound semiconductor substrate to form a light sensing element such as a photodiode, such as, silicon signal processing device such as a charge transfer device for signal processing the signals obtained by the optical sensing element (Si) is formed on the substrate, the light sensing unit is formed as a hybrid type solid-state imaging device formed by joining a metal bump such as both the elements indium (an in).

【0003】このような光検知装置は、高感度化、および高解像度化を図るために、前記した光検知素子を一枚の化合物半導体基板に出来るだけ高密度に形成するとともに、該光検知素子自体の面積も大型化を図ることが望まれ、そのため、前記素子に用いる化合物半導体基板、 [0003] Such an optical sensing device, high sensitivity, and in order to achieve high resolution, with only a high density form can be a light sensing device described above on a single compound semiconductor substrate, the light sensing elements area itself is desirable to reduce the size, therefore, a compound semiconductor substrate used in the element,
或いはSi基板の面積を大型化することが望まれる。 Or it is desired to increase the size of the area of ​​the Si substrate.

【0004】 [0004]

【従来の技術】従来のハイブリッド型の光検知装置の断面図を図2(a)に示す。 The cross-sectional view of a conventional hybrid type optical sensing device shown in FIG. 2 (a). 図示するように、例えばp型のHg As shown, for example, p-type Hg
1-x Cd x Te基板1には、所定のパターンでn型の不純物原子であるボロン(B)原子がイオン注入されてn型層2が形成され、pn接合が形成されてフォトダイオード3が形成されている。 The 1-x Cd x Te substrate 1, boron (B) atom is a n-type impurity atoms at a predetermined pattern is formed ion-implanted with n-type layer 2, a photodiode 3 are pn junction formed It is formed. そして該基板1の表面には硫化亜鉛(ZnS) より成る絶縁膜4が形成されている。 And on the surface of the substrate 1 an insulating film 4 made of zinc sulfide (ZnS) is formed.

【0005】一方、p型のSi基板5には前記フォトダイオードで得られた信号を処理する電荷転送素子が形成され、前記p型のSi基板5に燐等の不純物原子をイオン注入してn型層6を形成して該電荷転送素子の入力ダイオード7が形成されている。 On the other hand, the Si substrate 5 of the p-type charge transfer device for processing a signal obtained by the photodiode is formed, an impurity atom such as phosphorus in the Si substrate 5 of the p-type by ion implantation n input diode 7 of the charge transfer device is formed by forming a mold layer 6.

【0006】そして該基板5上にはSiO 2膜よりなる絶縁膜8が形成されている。 [0006] Then on the substrate 5 is an insulating film 8 made of SiO 2 film is formed. そしてこの絶縁膜4,8 が開口され、フォトダイオード3のn型層2と、入力ダイオードのn型層6同士がInの金属バンプ9,10を用いて接合されている。 And this insulating film 4 and 8 are opened, an n-type layer 2 of the photodiode 3, n-type layer 6 between the input diode is bonded using a metal bump 9 and 10 In.

【0007】 [0007]

【発明が解決しようとする課題】ところで、このような固体撮像素子は熱雑音の影響を避けるために、通常77° [SUMMARY OF THE INVENTION Incidentally, in order such solid-state imaging device to avoid the influence of thermal noise, usually 77 °
K の液体窒素温度で冷却して動作させている。 It is operated by cooling with liquid nitrogen temperature of K. 上記した The above-mentioned
Si基板5とHg 1-x Cd x Te基板1とは熱膨張率が異なっており、動作時の液体窒素温度と、非動作時の室温迄の温度変動で両者の基板1,5 に歪みが生じ、この歪みによる応力が掛り、この応力が両者の基板1,5 間で異なる値を示すので、両者の基板1,5 を接合している金属バンプ9, Si is the substrate 5 and the Hg 1-x Cd x Te substrate 1 have different thermal expansion coefficients, and the liquid nitrogen temperature during operation, distortions in both the substrate 1,5 at a temperature variation of up to room temperature at the time of non-operation occurs, the stress due to the strain consuming, exhibits different values ​​between the substrates 1 and 5 of this stress both metals are joined to both the substrate 1,5 bumps 9,
10に亀裂や、位置ずれを発生したり、或いは甚だしい場合には、金属バンプ9,10が、両者の基板1,5 より剥がれたりする問題がある。 10 cracks and the, or generate a position deviation in the case or an extreme, metal bumps 9 and 10, there is a problem that peels off from both the substrate 1 and 5.

【0008】そのため、動作時に冷却が必要なハイブリッド型の光検知装置においては、Si基板5とHg 1-x Cd x [0008] Therefore, in the hybrid type optical sensing devices required cooling during operation, Si substrate 5 and the Hg 1-x Cd x
Te基板1のような異種半導体基板間の熱膨張係数の差により、熱歪みが生じるため、基板の面積を小さくした小型のハイブリッド型固体撮像素子しか製造できない問題がある。 The difference in thermal expansion coefficient between different types of semiconductor substrates, such as Te substrate 1, the heat distortion occurs, hybrid solid-state imaging device of compact having a small area of ​​the substrate only there is a problem that can not be manufactured.

【0009】従って、ハイブリッド型の光検知装置で素子数の大規模化を図った場合、熱歪みにより金属バンプに応力が加わり接続不良が発生したり、両者の基板が損傷し動作不良が起こり、信頼性を低下する問題を生じていた。 Accordingly, when aimed at the scale of the number of elements in the hybrid type optical sensing device, or stress on the metal bump is joined connection failure caused by thermal strain, the both substrates are damaged malfunction occurs, It had caused the problem of lowering the reliability.

【0010】そのため、本出願人は上記した問題を解決するために、特願平3-179301号に於いて図2(b)に示すように、光検知素子を形成したHg 1-x Cd x Te基板1や、信号処理素子を形成したSi基板5を薄層化し、該薄層化した基板1,5 をサファイア基板11に接着剤12を用いて貼着することで、両者の基板1,5 の熱膨張率差によって金属バンプ9,10が位置ずれするのを防止する方法を提案している。 [0010] Therefore, in order Applicants to solve the problems described above, as shown in FIG. 2 (b) In Japanese Patent Application 3-179301, to form a light-sensing Hg 1-x Cd x Te and the substrate 1, signal processing element is thinned Si substrate 5 formed with, by sticking with an adhesive 12 to the substrate 1 and 5 were thin stratified sapphire substrate 11, both the substrate 1, metal bumps 9 and 10 have proposed a method to prevent the positional displacement by thermal expansion coefficient difference 5.

【0011】また図2(c)に示すように、フォトダイオード3を形成したHg 1-x Cd x Te基板1を薄層化し、該薄層化したHg 1-x Cd x Te基板1をSi基板5に接着剤を用いて貼着して、フォトダイオード3を形成したHg 1-x Cd x Te [0011] As shown in FIG. 2 (c), the Hg 1-x Cd x Te substrate 1 formed with the photodiode 3 is thinned, the Hg 1-x Cd x Te substrate 1 thin layered Si by sticking with an adhesive on the substrate 5, to form a photodiode 3 Hg 1-x Cd x Te
基板1の熱膨張率を信号処理素子13を形成したSi基板5 Si substrate 5 of the thermal expansion of the substrate 1 to form a signal processing device 13
の熱膨張率に見掛け上合致するようにして金属バンプ9, Metal bumps 9 so as to match the apparent thermal expansion coefficient,
10の位置ずれを防止する方法を提案している。 We propose a method of preventing the positional deviation of 10.

【0012】然し、上記した方法は、いずれもSi基板5、或いはHg 1-x Cd x Te基板1を薄層化する必要がある。 [0012] However, the method described above are all Si substrate 5, or the Hg 1-x Cd x Te substrate 1 has to be thinned. そして図2(b)に示すように薄層化するHg 1-x Cd x Te Then Hg thinning as shown in FIG. 2 (b) 1-x Cd x Te
基板1の研磨、或いはエッチングする寸法は、サファイア基板11と接着した場合は、このサファイア基板11と薄層化したHg 1-x Cd x Te基板1を接着した基板の熱膨張量が、相手のSi基板5と熱膨張量が合致する程度の寸法に研磨する必要がある。 Dimensions polishing, the or etching of the substrate 1, when bonded to the sapphire substrate 11, the thermal expansion amount of the substrate to adhere the Hg 1-x Cd x Te substrate 1 and thinning the sapphire substrate 11, the opponent Si substrate 5 and the amount of thermal expansion needs to be polished to a dimension enough to match.

【0013】また図2(c)に示すように、Hg 1-x Cd x Te基板1を薄層化する場合は、該薄層化したHg 1-x Cd x Te基板1とSi基板5を接着した熱膨張量は、相手の信号処理素子13を形成したSi基板5の熱膨張量と等しく成る程度の寸法に研磨、エッチングする必要があり、その作業が複雑で困難である。 [0013] As shown in FIG. 2 (c), when thinning the Hg 1-x Cd x Te substrate 1, the Hg 1-x Cd x Te substrate 1 and the Si substrate 5 was thin stratified bonding thermal expansion amount is polished to a degree of dimension equal to the thermal expansion of Si substrate 5 to form a signal processing device 13 of the opponent, it is necessary to etch, it is complicated and difficult the work.

【0014】本発明は上記した問題点を解決し、例えば [0014] The present invention solves the above problems, for example,
Hg 1-x Cd x Te基板を薄層化して他の支持基板に接着して合成した基板を形成した場合、この合成した基板の熱膨張量が、相手のSi基板の熱膨張量と略等しくなるように、前記支持基板の熱膨張量が制御できるような半導体装置の提供を目的とする。 Hg 1-x Cd x Te substrate by thin case of forming a substrate synthesized adhered to another support substrate, the thermal expansion amount of the synthesized substrate, substantially equal to the thermal expansion amount of the other Si substrate It becomes as an object to provide a semiconductor device such as the thermal expansion amount of the supporting substrate can be controlled.

【0015】 [0015]

【課題を解決するための手段】本発明の半導体装置は、 The semiconductor device of the present invention According to an aspect of the
請求項1に示すように、第1の半導体基板上に形成された半導体装置と、第2の半導体基板上に形成された半導体装置とを、金属電極を用いて電気的に結合するハイブリッド型半導体装置において、第1あるいは第2の何れか一方の半導体基板を薄層化して、該薄層化した半導体基板に、該薄層化していない半導体基板に近い熱膨張係数をもつ支持基板を接着することを特徴とするものである。 As shown in claim 1, a hybrid type semiconductor and a semiconductor device formed on the first semiconductor substrate, and a semiconductor device formed on a second semiconductor substrate, electrically coupled with the metal electrodes in the apparatus, the first or the second one of the semiconductor substrate is thinned, the semiconductor substrate with the thin layered, adhered to a support substrate having a thermal expansion coefficient close to the semiconductor substrate which is not thin stratified it is characterized in.

【0016】更に請求項2に示すように、前記第1、第2の両方の半導体基板を薄層化して、第1、第2の半導体基板の中間の熱膨張係数をもつ支持基板を形成し、該支持基板を前記第1および第2の半導体基板に接着したことを特徴とするものである。 [0016] As further shown in claim 2, wherein the first, the second both the semiconductor substrate and thin, a supporting substrate is formed with a first coefficient of thermal expansion of the middle of the second semiconductor substrate , it is characterized in that it has adhered the supporting substrate to the first and second semiconductor substrates.

【0017】更に請求項3に示すように、前記支持基板を熱膨張係数の小さい半導体基板を構成する元素の粉末、或いは該元素の酸化物を有機樹脂に混合して形成することを特徴とするものである。 [0017] As further shown in claim 3, characterized by forming a mixture of said supporting substrate powder of elements constituting the small semiconductor substrate coefficient of thermal expansion, or the oxides of said elements to the organic resin it is intended.

【0018】 [0018]

【作用】本発明では、図1(a)の如くフォトダイオード3 According to the present invention, a photodiode 3 as shown FIG. 1 (a)
を形成し、薄層化したHg 1-x Cd Forming a thin stratified Hg 1-x Cd x Te基板1に、信号処理素子13を形成したSi基板5に近い熱膨張係数を持ち、Si the x Te substrate 1 has a thermal expansion coefficient close to the Si substrate 5 formed with the signal processing device 13, Si
の粉末、或いは二酸化シリコン( SiO 2 ) よりなる粉末を混合したエポキシ樹脂を固化した支持基板21を、エポキシ樹脂のような接着剤12にて貼着する。 Powder, or the supporting substrate 21 the solidified epoxy resin mixed with powder of silicon dioxide (SiO 2), is stuck with an adhesive 12 such as epoxy resin.

【0019】このようにすると、フォトダイオード3を形成したHg 1-x Cd x Te基板1の熱膨張率は、支持基板21 [0019] Thus, the thermal expansion coefficient of Hg 1-x Cd x Te substrate 1 formed with the photodiode 3, the supporting substrate 21
の熱膨張率が支配的になり、この支持基板21の厚さを変化させることで、支持基板21とHg 1-x Cd x Te基板1とを貼着した合成基板22の熱膨張率は、信号処理素子13を形成したSi基板5の熱膨張率に近くなる。 The thermal expansion coefficient becomes dominant, by changing the thickness of the supporting substrate 21, the thermal expansion coefficient of the supporting substrate 21 and the Hg 1-x Cd x Te substrate 1 and the synthetic substrate 22 was stuck to the close to the thermal expansion coefficient of Si substrate 5 to form a signal processing device 13.

【0020】そしてこの合成基板22の熱膨張率を、Si基板5の熱膨張率に近づけるには、支持基板21の厚さを変動させることにより可能となる。 [0020] Then the coefficient of thermal expansion of the synthetic substrate 22, the closer the thermal expansion coefficient of the Si substrate 5, made possible by varying the thickness of the support substrate 21. つまり、合成基板22の熱膨張率がSi基板5の熱膨張率と隔たっている場合は、 In other words, if the thermal expansion coefficient of the composite substrate 22 is spaced a thermal expansion coefficient of the Si substrate 5,
支持基板21の厚さを厚くする方向に持っていくことで可能となる。 It made possible to bring in a direction to increase the thickness of the supporting substrate 21.

【0021】従って、このHg 1-x Cd x Te基板1と支持基板21を接着した合成基板22とSi基板5を金属バンプ9,10 [0021] Therefore, the Hg 1-x Cd x Te substrate 1 and the synthetic substrate 22 was bonded to the supporting substrate 21 and the Si substrate 5 of the metal bump 9 and 10
で接合して形成した半導体装置が、動作時の液体窒素温度より非動作時の室温保管の温度に到る迄の温度変動が生じても、金属バンプ9,10や両者の基板1,5 に加わる応力が低減されるため、素子数の大規模化を行った場合でも、上記した金属バンプ9,10の位置ずれや、剥離等の現象が防止される。 The semiconductor device is formed by joining in, even when the temperature variation of up to a temperature of room temperature storage during non-operation than the liquid nitrogen temperature during operation, the metal bump 9 and 10 and both the substrate 1,5 to join the stress is reduced, even when a scale of the number of elements, and displacement of the metal bump 9 and 10 described above, the phenomenon such as peeling can be prevented.

【0022】 [0022]

【実施例】以下、図面を用いて本発明の実施例につき詳細に説明する。 EXAMPLES Hereinafter, be described in detail embodiments of the present invention with reference to the drawings. 図1(a)は本発明の第1実施例の半導体装置の断面図であり、フォトダイオード3を形成したHg 1 (a) is a sectional view of a semiconductor device of the first embodiment of the present invention, Hg forming the photodiode 3
1-x Cd x Te基板1は20μm 以下にエッチング、或いは研磨により薄層化されている。 1-x Cd x Te substrate 1 is thinned to 20μm or less etching or by polishing. このように20μm 以下に薄層化する理由は、Si基板に近い熱膨張率を持つ支持基板を形成して、Si基板とHg 1-x Cd x Te基板の熱膨張係数差が小さく保たれるようにするためである。 The reason for thinning the 20μm or less in this way, forms a supporting substrate having a thermal expansion coefficient close to the Si substrate, the thermal expansion coefficient difference of the Si substrate and the Hg 1-x Cd x Te substrate is kept small for the purpose of way is.

【0023】またSi基板5に不純物原子をイオン注入して信号処理素子13を形成する。 [0023] with ion-implanting impurity atoms into the Si substrate 5 to form a signal processing device 13. そしてこの薄層化された And is this thin layer
Hg 1-x Cd x Te基板1には、エポキシ樹脂(商品名:アラルダイト、チバガイギー社製)に粒径が10〜50μm のS The Hg 1-x Cd x Te substrate 1, an epoxy resin (trade name: Araldite, Ciba-Geigy) to a particle size of 10~50μm S
i、或いはSiO 2を混入して固化した厚さが100 μm 程度の支持基板21が、上記エポキシ樹脂より成る接着剤12にて接着されている。 i, or thickness and solidified by mixing SiO 2 is the 100 [mu] m about the supporting substrate 21 are adhered with an adhesive 12 made of the epoxy resin. このようにエポキシ樹脂にSi、或いはSiO 2の粉末を混合するのは、上記した支持基板21にSi Si in such an epoxy resin, or to mix the powder of SiO 2 is, Si in the support substrate 21 as described above
基板5と同様な熱膨張率を持たすようにするために行い、この支持基板21の熱膨張係数の値は1.4 ×10 Performed in order to Motas a similar thermal expansion coefficient as the substrate 5, the value of the thermal expansion coefficient of the supporting substrate 21 is 1.4 × 10
-6 (k -1 ) で、上記したエポキシ樹脂の熱膨張係数は3.4 -6 (k -1), the thermal expansion coefficient of the epoxy resin mentioned above is 3.4
×10 -5 (k -1 ) である。 × a 10 -5 (k -1).

【0024】Hg 1-x Cd x Te基板1の熱膨張係数は3.87× The thermal expansion coefficient of the Hg 1-x Cd x Te substrate 1 is 3.87 ×
10 -6 (K -1 ) であるが、その上にSi粉末、或いはSiO 2粉末を混入したエポキシ樹脂よりなる支持基板の熱膨張係数の値は1.4 ×10 -6 (k -1 ) であり、上記Hg 1-x Cd x Te基板1と支持基板21とを接着することで合成した基板の熱膨張係数は、Siの熱膨張係数の1.21×10 -6 (K -1 ) に近い値を示すようになる。 Is a 10 -6 (K -1), Si powder thereon, or the value of the thermal expansion coefficient of the supporting substrate made of epoxy resin mixed with SiO 2 powder is at 1.4 × 10 -6 (k -1) , the thermal expansion coefficient of the substrate synthesized by bonding the aforementioned Hg 1-x Cd x Te substrate 1 and the supporting substrate 21, a value close to 1.21 × 10 -6 (K -1) of the thermal expansion coefficient of Si It is shown.

【0025】またこの支持基板の厚さを変化させることで、支持基板とHg 1-x Cd x Te基板を接着した合成した合成基板22の熱膨張率を、Si基板の熱膨張率により確実に、近づけることが可能となる。 [0025] The thermal expansion coefficient of the support by changing the thickness of the substrate, the supporting substrate and the Hg 1-x Cd x Te synthetic substrate 22 substrate synthesized adhered to, certainly by the thermal expansion coefficient of the Si substrate , it is possible to close.

【0026】このようにすることで、フォトダイオード3を形成したHg 1-x Cd x Te基板1と、信号処理素子13を形成したSi基板5の両者の基板の熱膨張率が略等しくなり、金属バンプ9,10の位置ずれや、亀裂を発生することが無くなり、高信頼度の半導体装置が得られる効果がある。 [0026] By doing so, the Hg 1-x Cd x Te substrate 1 formed with the photodiode 3, the thermal expansion coefficient of the substrate of both the Si substrate 5 to form a signal processing device 13 becomes substantially equal, and displacement of the metal bump 9 and 10, no longer is possible to generate a crack, the effect obtained is a semiconductor device of high reliability.

【0027】上記実施例の他に、第2実施例として図2 [0027] In addition to the above-described embodiment, the second embodiment of FIG. 2
(b)に示すように、Hg 1-x Cd x Te基板1のみでなく、Si As shown in (b), Hg 1-x Cd x Te substrate 1 not only, Si
基板5をも薄層化して、両者の基板1,5 に共に、上記したエポキシ樹脂にSi、或いはSiO 2の粉末を混入して固化した支持基板21を接着剤12を用いて接着することで、両者の基板1,5 の熱膨張率を支持基板21の熱膨張率に近くすることで、半導体装置の温度変動による基板の熱歪みを緩和してもよい。 Also the substrate 5 by thin layer, together both substrates 1,5, by bonding with adhesive 12 epoxy resin Si, or a supporting substrate 21 which is solidified by mixing a powder of SiO 2 above , by close thermal expansion coefficients of both the substrates 1 and 5 to the thermal expansion coefficient of the support substrate 21 may reduce thermal distortion of the substrate due to temperature variation of the semiconductor device.

【0028】 [0028]

【発明の効果】以上説明したように、本発明によれば異種半導体基板間の熱膨張係数差による熱歪みを緩和でき、形成された固体撮像素子のような光検知装置を77° As described in the foregoing, according to the present invention can reduce thermal distortion due to thermal expansion coefficient difference between the different semiconductor substrate, an optical sensing device 77 °, such as formed solid imaging device
K の低温より、室温の保管温度まで曝した場合でも、両者の素子間を結合する金属バンプに位置ずれや、亀裂を発生する現象が少なくなり、高信頼度のハイブリッド型の光検知装置が得られる効果がある。 Colder K, even when exposed to a storage temperature of room temperature, located in the metal bumps for coupling between both elements shift and, phenomenon occurring cracks is reduced, resulting hybrid type optical sensing device of high reliability there is an effect to be.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】 本発明の半導体装置の断面図である。 1 is a cross-sectional view of a semiconductor device of the present invention.

【図2】 従来の半導体装置の断面図である。 2 is a cross-sectional view of a conventional semiconductor device.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 Hg 1-x Cd x Te基板 3 フォトダイオード 4,8 絶縁膜 5 Si基板 9,10 金属バンプ 12 接着剤 13 信号処理素子 21 支持基板 22 合成基板 1 Hg 1-x Cd x Te substrate 3 photodiodes 4,8 insulation film 5 Si substrate 9, 10 metal bumps 12 adhesive 13 signal processing device 21 the support substrate 22 Synthesis substrate

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl. 7識別記号 FI H01L 31/10 (72)発明者 成田 正彦 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (56)参考文献 特開 平5−36966(JP,A) 特開 平4−199877(JP,A) 特開 昭64−61056(JP,A) IEEE TRANSACTIONS ON ELECTRON DEVIC ES,Vol. ────────────────────────────────────────────────── ─── of the front page continued (51) Int.Cl. 7 identification mark FI H01L 31/10 (72) inventor Masahiko Narita Kanagawa Prefecture, Nakahara-ku, Kawasaki, Kamikodanaka 1015 address Fujitsu within Co., Ltd. (56) reference Patent flat 5-36966 (JP, A) JP flat 4-199877 (JP, A) JP Akira 64-61056 (JP, A) IEEE TRANSACTIONS ON ELECTRON DEVIC ES, Vol. 38,No. 38, No. 5(1991), pp. 5 (1991), pp. 1104−1109 (58)調査した分野(Int.Cl. 7 ,DB名) H01L 27/146 H01L 25/065 H01L 25/07 H01L 25/16 H01L 25/18 H01L 31/10 1104-1109 (58) investigated the field (Int.Cl. 7, DB name) H01L 27/146 H01L 25/065 H01L 25/07 H01L 25/16 H01L 25/18 H01L 31/10

Claims (3)

    (57)【特許請求の範囲】 (57) [the claims]
  1. 【請求項1】 第1の半導体基板(1) 上に形成された半導体装置(3) と、第2の半導体基板(5) 上に形成された半導体装置(13)とを、金属バンプ(9,10)を用いて電気的に結合するハイブリッド型半導体装置において、 第1、あるいは第2の何れか一方の半導体基板(1,5) を薄層化して、該薄層化した半導体基板(1) に、該薄層化していない半導体基板(5) に近い熱膨張係数をもつ支持基板(21)を接着することを特徴とする半導体装置。 1. A semiconductor device formed on the first semiconductor substrate (1) and (3), a semiconductor device formed on a second semiconductor substrate (5) and (13), the metal bumps (9 a hybrid type semiconductor device electrically coupled with 10), the first, or the second one of the semiconductor substrate (1,5) with a thin layer, the semiconductor substrate (1 described thin stratified ), a semiconductor device which is characterized in that bonding the supporting substrate (21) having a thermal expansion coefficient close to the semiconductor substrate (5) that is not thin layered.
  2. 【請求項2】 第1の半導体基板(1) 上に形成された半導体装置(3) と、第2の半導体基板(5) 上に形成された半導体装置(13)とを、金属バンプ(9,10)を用いて電気的に結合するハイブリッド型半導体装置において、 第1、第2両方の半導体基板(1,5) を薄層化して、該第1、第2の半導体基板(1,5) の中間の熱膨張係数をもつ支持基板(21)を形成し、該支持基板(21)を前記第1および第2の半導体基板(1,5) に接着したことを特徴とする半導体装置。 2. A semiconductor device formed on the first semiconductor substrate (1) and (3), a semiconductor device formed on a second semiconductor substrate (5) and (13), the metal bumps (9 a hybrid type semiconductor device electrically coupled with 10), first, the second both of the semiconductor substrate (1,5) with a thin layer, said first, second semiconductor substrate (1, 5 a support substrate having a thermal expansion coefficient of the intermediate (21) formed of a), wherein a said supporting substrate (21) adhered to said first and second semiconductor substrates (1, 5).
  3. 【請求項3】 請求項1、或いは2に記載の支持基板(2 3. The method of claim 1, or a support substrate according to 2 (2
    1)を熱膨張係数が小さい半導体基板(5) を構成する元素の粉末、或いは該元素の酸化物を有機樹脂に混合して形成したことを特徴とする半導体装置。 A semiconductor device 1), characterized in that formed by mixing powders of elements constituting the semiconductor substrate having a small thermal expansion coefficient (5), or an oxide of said elements to the organic resin.
JP04054668A 1992-03-13 1992-03-13 Semiconductor device Expired - Fee Related JP3114759B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3057706A1 (en) * 2016-10-19 2018-04-20 Commissariat Energie Atomique Method for producing a microelectronic chip for hybriding a second chip

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6238805B1 (en) * 1999-10-08 2001-05-29 Agilent Technologies, Inc. Low-stress interface between materials having different coefficients of expansion and method for fabricating same
US6900534B2 (en) * 2000-03-16 2005-05-31 Texas Instruments Incorporated Direct attach chip scale package

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE TRANSACTIONS ON ELECTRON DEVICES,Vol.38,No.5(1991),pp.1104−1109

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3057706A1 (en) * 2016-10-19 2018-04-20 Commissariat Energie Atomique Method for producing a microelectronic chip for hybriding a second chip
WO2018073517A1 (en) * 2016-10-19 2018-04-26 Commissariat à l'énergie atomique et aux énergies alternatives Method for the production of a microelectronic chip to be hybridised to a second chip

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