JP3114759B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3114759B2
JP3114759B2 JP04054668A JP5466892A JP3114759B2 JP 3114759 B2 JP3114759 B2 JP 3114759B2 JP 04054668 A JP04054668 A JP 04054668A JP 5466892 A JP5466892 A JP 5466892A JP 3114759 B2 JP3114759 B2 JP 3114759B2
Authority
JP
Japan
Prior art keywords
substrate
thermal expansion
semiconductor
semiconductor device
thinned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP04054668A
Other languages
Japanese (ja)
Other versions
JPH05259430A (en
Inventor
博之 若山
博 大工
正二 土肥
正彦 成田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP04054668A priority Critical patent/JP3114759B2/en
Publication of JPH05259430A publication Critical patent/JPH05259430A/en
Application granted granted Critical
Publication of JP3114759B2 publication Critical patent/JP3114759B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に係り、特に
化合物半導体基板に形成した光検知素子と、前記化合物
半導体基板と異なる熱膨張係数を有する半導体基板に形
成され、前記光検知素子で検知された信号を処理する信
号処理素子を金属バンプで接合したハイブリッド型の半
導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a photodetector formed on a compound semiconductor substrate and a semiconductor substrate having a different thermal expansion coefficient from that of the compound semiconductor substrate and detected by the photodetector. The present invention relates to a hybrid type semiconductor device in which signal processing elements for processing the processed signals are joined by metal bumps.

【0002】従来より、エネルギーギャップが狭く、赤
外線に高感度を有する水銀・カドミウム・テルル(Hg
1-x Cdx Te)のような化合物半導体基板にフォトダイオ
ードのような光検知素子を形成し、該光検知素子で得ら
れた信号を信号処理する電荷転送素子のような信号処理
素子をシリコン(Si)基板に形成し、両者の素子をイン
ジウム(In)のような金属バンプで接合したハイブリッ
ド型の固体撮像素子のような光検知装置が形成されてい
る。
Conventionally, mercury / cadmium / tellurium (Hg) having a narrow energy gap and high sensitivity to infrared rays
1-x Cd x Te), a photodetector such as a photodiode is formed on a compound semiconductor substrate, and a signal processing element such as a charge transfer element that processes a signal obtained by the photodetector is formed of silicon. A light detection device such as a hybrid type solid-state image pickup device in which both elements are formed on a (Si) substrate and bonded by a metal bump such as indium (In) is formed.

【0003】このような光検知装置は、高感度化、およ
び高解像度化を図るために、前記した光検知素子を一枚
の化合物半導体基板に出来るだけ高密度に形成するとと
もに、該光検知素子自体の面積も大型化を図ることが望
まれ、そのため、前記素子に用いる化合物半導体基板、
或いはSi基板の面積を大型化することが望まれる。
In such a light detecting device, in order to increase the sensitivity and the resolution, the above-described light detecting element is formed on a single compound semiconductor substrate at a density as high as possible. It is desired to increase the area of itself, and therefore, a compound semiconductor substrate used for the device,
Alternatively, it is desired to increase the area of the Si substrate.

【0004】[0004]

【従来の技術】従来のハイブリッド型の光検知装置の断
面図を図2(a)に示す。図示するように、例えばp型のHg
1-x Cdx Te基板1には、所定のパターンでn型の不純物
原子であるボロン(B)原子がイオン注入されてn型層
2が形成され、pn接合が形成されてフォトダイオード
3が形成されている。そして該基板1の表面には硫化亜
鉛(ZnS) より成る絶縁膜4が形成されている。
2. Description of the Related Art FIG. 2A is a cross-sectional view of a conventional hybrid type photodetector. As shown, for example, p-type Hg
Boron (B) atoms, which are n-type impurity atoms, are ion-implanted into a 1-x Cd x Te substrate 1 in a predetermined pattern to form an n-type layer 2, a pn junction is formed, and a photodiode 3 is formed. Is formed. An insulating film 4 made of zinc sulfide (ZnS) is formed on the surface of the substrate 1.

【0005】一方、p型のSi基板5には前記フォトダイ
オードで得られた信号を処理する電荷転送素子が形成さ
れ、前記p型のSi基板5に燐等の不純物原子をイオン注
入してn型層6を形成して該電荷転送素子の入力ダイオ
ード7が形成されている。
On the other hand, a charge transfer element for processing a signal obtained by the photodiode is formed on a p-type Si substrate 5, and an impurity atom such as phosphorus is ion-implanted into the p-type Si substrate 5 to form an n. An input diode 7 of the charge transfer element is formed by forming a mold layer 6.

【0006】そして該基板5上にはSiO2膜よりなる絶縁
膜8が形成されている。そしてこの絶縁膜4,8 が開口さ
れ、フォトダイオード3のn型層2と、入力ダイオード
のn型層6同士がInの金属バンプ9,10を用いて接合され
ている。
An insulating film 8 made of a SiO 2 film is formed on the substrate 5. The insulating films 4 and 8 are opened, and the n-type layer 2 of the photodiode 3 and the n-type layer 6 of the input diode are joined to each other using In metal bumps 9 and 10.

【0007】[0007]

【発明が解決しようとする課題】ところで、このような
固体撮像素子は熱雑音の影響を避けるために、通常77°
K の液体窒素温度で冷却して動作させている。上記した
Si基板5とHg1-x Cdx Te基板1とは熱膨張率が異なって
おり、動作時の液体窒素温度と、非動作時の室温迄の温
度変動で両者の基板1,5 に歪みが生じ、この歪みによる
応力が掛り、この応力が両者の基板1,5 間で異なる値を
示すので、両者の基板1,5 を接合している金属バンプ9,
10に亀裂や、位置ずれを発生したり、或いは甚だしい場
合には、金属バンプ9,10が、両者の基板1,5 より剥がれ
たりする問題がある。
By the way, such a solid-state imaging device usually has a temperature of 77 ° to avoid the influence of thermal noise.
Cooled and operated at K liquid nitrogen temperature. Above
Since the Si substrate 5 and the Hg 1-x Cd x Te substrate 1 have different coefficients of thermal expansion, distortion occurs in both substrates 1 and 5 due to the temperature fluctuation between liquid nitrogen temperature during operation and room temperature during non-operation. Then, a stress due to this distortion is applied, and this stress shows a different value between the two substrates 1 and 5, so that the metal bumps 9,
If cracks or misalignment occurs in the substrate 10, or if it is severe, there is a problem that the metal bumps 9, 10 are peeled off from both substrates 1, 5.

【0008】そのため、動作時に冷却が必要なハイブリ
ッド型の光検知装置においては、Si基板5とHg1-x Cdx
Te基板1のような異種半導体基板間の熱膨張係数の差に
より、熱歪みが生じるため、基板の面積を小さくした小
型のハイブリッド型固体撮像素子しか製造できない問題
がある。
For this reason, in a hybrid type photodetector which requires cooling during operation, the Si substrate 5 and the Hg 1-x Cd x
Since thermal distortion occurs due to a difference in thermal expansion coefficient between different types of semiconductor substrates such as the Te substrate 1, there is a problem that only a small hybrid solid-state imaging device having a reduced substrate area can be manufactured.

【0009】従って、ハイブリッド型の光検知装置で素
子数の大規模化を図った場合、熱歪みにより金属バンプ
に応力が加わり接続不良が発生したり、両者の基板が損
傷し動作不良が起こり、信頼性を低下する問題を生じて
いた。
Therefore, when the number of elements is increased in the hybrid type photodetector, stress is applied to the metal bumps due to thermal strain, and a connection failure occurs, or both substrates are damaged, resulting in an operation failure. There has been a problem that the reliability is reduced.

【0010】そのため、本出願人は上記した問題を解決
するために、特願平3-179301号に於いて図2(b)に示すよ
うに、光検知素子を形成したHg1-x Cdx Te基板1や、信
号処理素子を形成したSi基板5を薄層化し、該薄層化し
た基板1,5 をサファイア基板11に接着剤12を用いて貼着
することで、両者の基板1,5 の熱膨張率差によって金属
バンプ9,10が位置ずれするのを防止する方法を提案して
いる。
[0010] Therefore, in order to solve the above-mentioned problem, the present applicant has disclosed in Japanese Patent Application No. Hei 3-179301 the Hg 1-x Cd x The Te substrate 1 and the Si substrate 5 on which the signal processing element is formed are thinned, and the thinned substrates 1 and 5 are adhered to a sapphire substrate 11 with an adhesive 12 so that A method for preventing the displacement of the metal bumps 9 and 10 due to the difference in thermal expansion coefficient of 5 has been proposed.

【0011】また図2(c)に示すように、フォトダイオー
ド3を形成したHg1-x Cdx Te基板1を薄層化し、該薄層
化したHg1-x Cdx Te基板1をSi基板5に接着剤を用いて
貼着して、フォトダイオード3を形成したHg1-x Cdx Te
基板1の熱膨張率を信号処理素子13を形成したSi基板5
の熱膨張率に見掛け上合致するようにして金属バンプ9,
10の位置ずれを防止する方法を提案している。
As shown in FIG. 2C, the Hg 1-x Cd x Te substrate 1 on which the photodiode 3 is formed is thinned, and the thinned Hg 1-x Cd x Te substrate 1 is Hg 1-x Cd x Te which is attached to the substrate 5 using an adhesive to form the photodiode 3
The coefficient of thermal expansion of the substrate 1 is determined by the Si substrate 5 on which the signal processing element 13 is formed.
Metal bump 9,
It proposes a method to prevent 10 misalignments.

【0012】然し、上記した方法は、いずれもSi基板
5、或いはHg1-x Cdx Te基板1を薄層化する必要があ
る。そして図2(b)に示すように薄層化するHg1-x Cdx Te
基板1の研磨、或いはエッチングする寸法は、サファイ
ア基板11と接着した場合は、このサファイア基板11と薄
層化したHg1-x Cdx Te基板1を接着した基板の熱膨張量
が、相手のSi基板5と熱膨張量が合致する程度の寸法に
研磨する必要がある。
However, any of the above-mentioned methods needs to make the Si substrate 5 or the Hg 1-x Cd x Te substrate 1 thinner. Then, as shown in FIG. 2 (b), Hg 1-x Cd x Te
When the substrate 1 is polished or etched, when the sapphire substrate 11 is bonded, the amount of thermal expansion of the substrate to which the sapphire substrate 11 and the thinned Hg 1-x Cd x Te substrate 1 are bonded is determined. It is necessary to polish the silicon substrate 5 to such a size that the amount of thermal expansion coincides therewith.

【0013】また図2(c)に示すように、Hg1-x Cdx Te基
板1を薄層化する場合は、該薄層化したHg1-x Cdx Te基
板1とSi基板5を接着した熱膨張量は、相手の信号処理
素子13を形成したSi基板5の熱膨張量と等しく成る程度
の寸法に研磨、エッチングする必要があり、その作業が
複雑で困難である。
As shown in FIG. 2C, when the Hg 1-x Cd x Te substrate 1 is thinned, the thinned Hg 1-x Cd x Te substrate 1 and the Si substrate 5 are combined. The adhered thermal expansion must be polished and etched to a size that is equal to the thermal expansion of the Si substrate 5 on which the mating signal processing element 13 is formed, and the operation is complicated and difficult.

【0014】本発明は上記した問題点を解決し、例えば
Hg1-x Cdx Te基板を薄層化して他の支持基板に接着して
合成した基板を形成した場合、この合成した基板の熱膨
張量が、相手のSi基板の熱膨張量と略等しくなるよう
に、前記支持基板の熱膨張量が制御できるような半導体
装置の提供を目的とする。
The present invention solves the above-mentioned problems, and for example,
When the Hg 1-x Cd x Te substrate is thinned and bonded to another supporting substrate to form a synthesized substrate, the thermal expansion of the synthesized substrate is substantially equal to the thermal expansion of the mating Si substrate. It is an object of the present invention to provide a semiconductor device in which the amount of thermal expansion of the support substrate can be controlled.

【0015】[0015]

【課題を解決するための手段】本発明の半導体装置は、
請求項1に示すように、第1の半導体基板上に形成され
た半導体装置と、第2の半導体基板上に形成された半導
体装置とを、金属電極を用いて電気的に結合するハイブ
リッド型半導体装置において、第1あるいは第2の何れ
か一方の半導体基板を薄層化して、該薄層化した半導体
基板に、該薄層化していない半導体基板に近い熱膨張係
数をもつ支持基板を接着することを特徴とするものであ
る。
According to the present invention, there is provided a semiconductor device comprising:
2. A hybrid semiconductor device according to claim 1, wherein the semiconductor device formed on the first semiconductor substrate and the semiconductor device formed on the second semiconductor substrate are electrically coupled by using metal electrodes. In the apparatus, one of the first and second semiconductor substrates is thinned, and a support substrate having a thermal expansion coefficient close to that of the non-thinned semiconductor substrate is bonded to the thinned semiconductor substrate. It is characterized by the following.

【0016】更に請求項2に示すように、前記第1、第
2の両方の半導体基板を薄層化して、第1、第2の半導
体基板の中間の熱膨張係数をもつ支持基板を形成し、該
支持基板を前記第1および第2の半導体基板に接着した
ことを特徴とするものである。
According to a second aspect of the present invention, both the first and second semiconductor substrates are thinned to form a support substrate having a thermal expansion coefficient intermediate between the first and second semiconductor substrates. The support substrate is bonded to the first and second semiconductor substrates.

【0017】更に請求項3に示すように、前記支持基板
を熱膨張係数の小さい半導体基板を構成する元素の粉
末、或いは該元素の酸化物を有機樹脂に混合して形成す
ることを特徴とするものである。
According to a third aspect of the present invention, the support substrate is formed by mixing powder of an element constituting the semiconductor substrate having a small coefficient of thermal expansion or oxide of the element with an organic resin. Things.

【0018】[0018]

【作用】本発明では、図1(a)の如くフォトダイオード3
を形成し、薄層化したHg1-x Cd x Te基板1に、信号処理
素子13を形成したSi基板5に近い熱膨張係数を持ち、Si
の粉末、或いは二酸化シリコン( SiO2) よりなる粉末を
混合したエポキシ樹脂を固化した支持基板21を、エポキ
シ樹脂のような接着剤12にて貼着する。
According to the present invention, as shown in FIG.
Formed and thinned Hg1-xCd xSignal processing on Te substrate 1
It has a thermal expansion coefficient close to that of the Si substrate 5 on which the element 13 is formed, and
Powder or silicon dioxide (SiOTwo)
The support substrate 21 where the mixed epoxy resin is solidified is
Affix with an adhesive 12 such as resin.

【0019】このようにすると、フォトダイオード3を
形成したHg1-x Cdx Te基板1の熱膨張率は、支持基板21
の熱膨張率が支配的になり、この支持基板21の厚さを変
化させることで、支持基板21とHg1-x Cdx Te基板1とを
貼着した合成基板22の熱膨張率は、信号処理素子13を形
成したSi基板5の熱膨張率に近くなる。
Thus, the thermal expansion coefficient of the Hg 1-x Cd x Te substrate 1 on which the photodiode 3 is formed is
The coefficient of thermal expansion of the composite substrate 22 to which the support substrate 21 and the Hg 1-x Cd x Te substrate 1 are adhered is changed by changing the thickness of the support substrate 21. It becomes close to the coefficient of thermal expansion of the Si substrate 5 on which the signal processing element 13 is formed.

【0020】そしてこの合成基板22の熱膨張率を、Si基
板5の熱膨張率に近づけるには、支持基板21の厚さを変
動させることにより可能となる。つまり、合成基板22の
熱膨張率がSi基板5の熱膨張率と隔たっている場合は、
支持基板21の厚さを厚くする方向に持っていくことで可
能となる。
The coefficient of thermal expansion of the composite substrate 22 can be made closer to the coefficient of thermal expansion of the Si substrate 5 by changing the thickness of the supporting substrate 21. That is, when the coefficient of thermal expansion of the composite substrate 22 is separated from the coefficient of thermal expansion of the Si substrate 5,
This is possible by bringing the supporting substrate 21 in the direction of increasing the thickness.

【0021】従って、このHg1-x Cdx Te基板1と支持基
板21を接着した合成基板22とSi基板5を金属バンプ9,10
で接合して形成した半導体装置が、動作時の液体窒素温
度より非動作時の室温保管の温度に到る迄の温度変動が
生じても、金属バンプ9,10や両者の基板1,5 に加わる応
力が低減されるため、素子数の大規模化を行った場合で
も、上記した金属バンプ9,10の位置ずれや、剥離等の現
象が防止される。
Accordingly, the composite substrate 22 in which the Hg 1-x Cd x Te substrate 1 and the supporting substrate 21 are bonded and the Si substrate 5 are connected to the metal bumps 9, 10.
Even if the temperature of the semiconductor device formed by bonding at the temperature changes from the temperature of liquid nitrogen during operation to the temperature of storage at room temperature during non-operation, the metal bumps 9 and 10 and both substrates 1 and 5 can be Since the applied stress is reduced, even when the number of elements is increased, the above-described phenomena such as displacement of the metal bumps 9 and 10 and separation are prevented.

【0022】[0022]

【実施例】以下、図面を用いて本発明の実施例につき詳
細に説明する。図1(a)は本発明の第1実施例の半導体装
置の断面図であり、フォトダイオード3を形成したHg
1-x Cdx Te基板1は20μm 以下にエッチング、或いは研
磨により薄層化されている。このように20μm 以下に薄
層化する理由は、Si基板に近い熱膨張率を持つ支持基板
を形成して、Si基板とHg1-x Cdx Te基板の熱膨張係数差
が小さく保たれるようにするためである。
Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1A is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
The 1-x Cd x Te substrate 1 is thinned by etching or polishing to 20 μm or less. The reason why the thickness is reduced to 20 μm or less is that the supporting substrate having a thermal expansion coefficient close to that of the Si substrate is formed, and the difference in thermal expansion coefficient between the Si substrate and the Hg 1-x Cd x Te substrate is kept small That's why.

【0023】またSi基板5に不純物原子をイオン注入し
て信号処理素子13を形成する。そしてこの薄層化された
Hg1-x Cdx Te基板1には、エポキシ樹脂(商品名:アラ
ルダイト、チバガイギー社製)に粒径が10〜50μm のS
i、或いはSiO2を混入して固化した厚さが100 μm 程度
の支持基板21が、上記エポキシ樹脂より成る接着剤12に
て接着されている。このようにエポキシ樹脂にSi、或い
はSiO2の粉末を混合するのは、上記した支持基板21にSi
基板5と同様な熱膨張率を持たすようにするために行
い、この支持基板21の熱膨張係数の値は1.4 ×10
-6(k-1) で、上記したエポキシ樹脂の熱膨張係数は3.4
×10-5(k-1) である。
The signal processing element 13 is formed by ion-implanting impurity atoms into the Si substrate 5. And this thinned
The Hg 1-x Cd x Te substrate 1 is made of epoxy resin (trade name: Araldite, manufactured by Ciba Geigy) and S particles having a particle size of 10 to 50 μm.
A support substrate 21 having a thickness of about 100 μm solidified by mixing i or SiO 2 is adhered by the adhesive 12 made of the epoxy resin. Mixing Si or SiO 2 powder with the epoxy resin in this manner,
This is performed so as to have the same coefficient of thermal expansion as the substrate 5. The value of the coefficient of thermal expansion of the supporting substrate 21 is 1.4 × 10
-6 (k -1 ), and the thermal expansion coefficient of the above epoxy resin is 3.4
× 10 -5 (k -1 ).

【0024】Hg1-x Cdx Te基板1の熱膨張係数は3.87×
10-6(K-1) であるが、その上にSi粉末、或いはSiO2粉末
を混入したエポキシ樹脂よりなる支持基板の熱膨張係数
の値は1.4 ×10-6(k-1) であり、上記Hg1-x Cdx Te基板
1と支持基板21とを接着することで合成した基板の熱膨
張係数は、Siの熱膨張係数の1.21×10-6(K-1) に近い値
を示すようになる。
The thermal expansion coefficient of the Hg 1-x Cd x Te substrate 1 is 3.87 ×
10 -6 (K -1 ), and the value of the thermal expansion coefficient of the supporting substrate made of epoxy resin mixed with Si powder or SiO 2 powder thereon is 1.4 × 10 -6 (k -1 ). The coefficient of thermal expansion of the substrate synthesized by bonding the Hg 1-x Cd x Te substrate 1 and the supporting substrate 21 has a value close to 1.21 × 10 −6 (K −1 ) of the coefficient of thermal expansion of Si. As shown.

【0025】またこの支持基板の厚さを変化させること
で、支持基板とHg1-x Cdx Te基板を接着した合成した合
成基板22の熱膨張率を、Si基板の熱膨張率により確実
に、近づけることが可能となる。
By changing the thickness of the support substrate, the coefficient of thermal expansion of the composite substrate 22 obtained by bonding the support substrate and the Hg 1-x Cd x Te substrate can be reliably determined by the coefficient of thermal expansion of the Si substrate. , Closer to each other.

【0026】このようにすることで、フォトダイオード
3を形成したHg1-x Cdx Te基板1と、信号処理素子13を
形成したSi基板5の両者の基板の熱膨張率が略等しくな
り、金属バンプ9,10の位置ずれや、亀裂を発生すること
が無くなり、高信頼度の半導体装置が得られる効果があ
る。
By doing so, the thermal expansion coefficients of the Hg 1-x Cd x Te substrate 1 on which the photodiode 3 is formed and the Si substrate 5 on which the signal processing element 13 is formed become substantially equal, The displacement and cracking of the metal bumps 9 and 10 do not occur, so that a highly reliable semiconductor device can be obtained.

【0027】上記実施例の他に、第2実施例として図2
(b)に示すように、Hg1-x Cdx Te基板1のみでなく、Si
基板5をも薄層化して、両者の基板1,5 に共に、上記し
たエポキシ樹脂にSi、或いはSiO2の粉末を混入して固化
した支持基板21を接着剤12を用いて接着することで、両
者の基板1,5 の熱膨張率を支持基板21の熱膨張率に近く
することで、半導体装置の温度変動による基板の熱歪み
を緩和してもよい。
In addition to the above embodiment, a second embodiment shown in FIG.
As shown in (b), not only Hg 1-x Cd x Te substrate 1 but also Si
The substrate 5 is also made thinner, and a support substrate 21 which is obtained by mixing Si or SiO 2 powder with the above epoxy resin and is solidified is bonded to both the substrates 1 and 5 using the adhesive 12. By making the thermal expansion coefficients of the substrates 1 and 5 close to the thermal expansion coefficient of the support substrate 21, thermal distortion of the substrate due to temperature fluctuation of the semiconductor device may be reduced.

【0028】[0028]

【発明の効果】以上説明したように、本発明によれば異
種半導体基板間の熱膨張係数差による熱歪みを緩和で
き、形成された固体撮像素子のような光検知装置を77°
K の低温より、室温の保管温度まで曝した場合でも、両
者の素子間を結合する金属バンプに位置ずれや、亀裂を
発生する現象が少なくなり、高信頼度のハイブリッド型
の光検知装置が得られる効果がある。
As described above, according to the present invention, thermal distortion due to a difference in thermal expansion coefficient between different types of semiconductor substrates can be reduced, and a photodetector such as a formed solid-state image sensor can be used at 77 °.
Even when exposed to a storage temperature of room temperature from a low temperature of K, the displacement and cracking of the metal bumps connecting the two elements are less likely to occur, and a highly reliable hybrid photodetector is obtained. Has the effect.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の半導体装置の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

【図2】 従来の半導体装置の断面図である。FIG. 2 is a cross-sectional view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 Hg1-x Cdx Te基板 3 フォトダイオード 4,8 絶縁膜 5 Si基板 9,10 金属バンプ 12 接着剤 13 信号処理素子 21 支持基板 22 合成基板1 Hg 1-x Cd x Te substrate 3 Photodiode 4,8 Insulating film 5 Si substrate 9,10 Metal bump 12 Adhesive 13 Signal processing element 21 Support substrate 22 Composite substrate

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI H01L 31/10 (72)発明者 成田 正彦 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (56)参考文献 特開 平5−36966(JP,A) 特開 平4−199877(JP,A) 特開 昭64−61056(JP,A) IEEE TRANSACTIONS ON ELECTRON DEVIC ES,Vol.38,No.5(1991), pp.1104−1109 (58)調査した分野(Int.Cl.7,DB名) H01L 27/146 H01L 25/065 H01L 25/07 H01L 25/16 H01L 25/18 H01L 31/10 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification code FI H01L 31/10 (72) Inventor Masahiko Narita 1015 Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) References JP Hei 5-36966 (JP, A) JP-A-4-199877 (JP, A) JP-A-64-61056 (JP, A) IEEE TRANSACTIONS ON ELECTRON DEVIC ES, Vol. 38, No. 5 (1991), p. 1104-1109 (58) Fields investigated (Int.Cl. 7 , DB name) H01L 27/146 H01L 25/065 H01L 25/07 H01L 25/16 H01L 25/18 H01L 31/10

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 第1の半導体基板(1) 上に形成された半
導体装置(3) と、第2の半導体基板(5) 上に形成された
半導体装置(13)とを、金属バンプ(9,10)を用いて電気的
に結合するハイブリッド型半導体装置において、 第1、あるいは第2の何れか一方の半導体基板(1,5) を
薄層化して、該薄層化した半導体基板(1) に、該薄層化
していない半導体基板(5) に近い熱膨張係数をもつ支持
基板(21)を接着することを特徴とする半導体装置。
A semiconductor device (3) formed on a first semiconductor substrate (1) and a semiconductor device (13) formed on a second semiconductor substrate (5) are connected to metal bumps (9). In the hybrid type semiconductor device electrically coupled by using the semiconductor substrate (1), the first or second semiconductor substrate (1, 5) is thinned, and the thinned semiconductor substrate (1) is formed. ), A supporting substrate (21) having a thermal expansion coefficient close to that of the non-thinned semiconductor substrate (5).
【請求項2】 第1の半導体基板(1) 上に形成された半
導体装置(3) と、第2の半導体基板(5) 上に形成された
半導体装置(13)とを、金属バンプ(9,10)を用いて電気的
に結合するハイブリッド型半導体装置において、 第1、第2両方の半導体基板(1,5) を薄層化して、該第
1、第2の半導体基板(1,5) の中間の熱膨張係数をもつ
支持基板(21)を形成し、該支持基板(21)を前記第1およ
び第2の半導体基板(1,5) に接着したことを特徴とする
半導体装置。
2. A semiconductor device (3) formed on a first semiconductor substrate (1) and a semiconductor device (13) formed on a second semiconductor substrate (5) are connected to metal bumps (9). , 10), the first and second semiconductor substrates (1, 5) are made thinner, and the first and second semiconductor substrates (1, 5) are thinned. A semiconductor device characterized in that a supporting substrate (21) having an intermediate thermal expansion coefficient is formed, and the supporting substrate (21) is bonded to the first and second semiconductor substrates (1, 5).
【請求項3】 請求項1、或いは2に記載の支持基板(2
1)を熱膨張係数が小さい半導体基板(5) を構成する元素
の粉末、或いは該元素の酸化物を有機樹脂に混合して形
成したことを特徴とする半導体装置。
3. The support substrate (2) according to claim 1 or 2,
A semiconductor device, wherein 1) is formed by mixing powder of an element constituting the semiconductor substrate (5) having a small coefficient of thermal expansion or oxide of the element with an organic resin.
JP04054668A 1992-03-13 1992-03-13 Semiconductor device Expired - Fee Related JP3114759B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04054668A JP3114759B2 (en) 1992-03-13 1992-03-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04054668A JP3114759B2 (en) 1992-03-13 1992-03-13 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH05259430A JPH05259430A (en) 1993-10-08
JP3114759B2 true JP3114759B2 (en) 2000-12-04

Family

ID=12977159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04054668A Expired - Fee Related JP3114759B2 (en) 1992-03-13 1992-03-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3114759B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3057706A1 (en) * 2016-10-19 2018-04-20 Commissariat A L'energie Atomique Et Aux Energies Alternatives METHOD FOR PRODUCING A MICROELECTRONIC CHIP FOR HYBRIDING A SECOND CHIP

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0817962A (en) * 1994-07-04 1996-01-19 Fujitsu Ltd Semiconductor device and package
JP3412952B2 (en) * 1995-03-17 2003-06-03 株式会社東芝 Hybrid semiconductor device and method of manufacturing the same
US6238805B1 (en) * 1999-10-08 2001-05-29 Agilent Technologies, Inc. Low-stress interface between materials having different coefficients of expansion and method for fabricating same
US6900534B2 (en) * 2000-03-16 2005-05-31 Texas Instruments Incorporated Direct attach chip scale package

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE TRANSACTIONS ON ELECTRON DEVICES,Vol.38,No.5(1991),pp.1104−1109

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3057706A1 (en) * 2016-10-19 2018-04-20 Commissariat A L'energie Atomique Et Aux Energies Alternatives METHOD FOR PRODUCING A MICROELECTRONIC CHIP FOR HYBRIDING A SECOND CHIP
WO2018073517A1 (en) * 2016-10-19 2018-04-26 Commissariat à l'énergie atomique et aux énergies alternatives Method for the production of a microelectronic chip to be hybridised to a second chip
US11165005B2 (en) 2016-10-19 2021-11-02 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for producing a microelectronic chip to be hybridised to a second chip

Also Published As

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