KR102057111B1 - 정전기 방전(esd) 격리형 입력/출력(i/o) 회로들 - Google Patents

정전기 방전(esd) 격리형 입력/출력(i/o) 회로들 Download PDF

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KR102057111B1
KR102057111B1 KR1020187027960A KR20187027960A KR102057111B1 KR 102057111 B1 KR102057111 B1 KR 102057111B1 KR 1020187027960 A KR1020187027960 A KR 1020187027960A KR 20187027960 A KR20187027960 A KR 20187027960A KR 102057111 B1 KR102057111 B1 KR 102057111B1
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South Korea
Prior art keywords
transistor
driver
circuit
switch
receiver
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KR20180127374A (ko
Inventor
유진 로버트 월리
레자 자리리제이나리
슈리커 둔디갈
웬-이 첸
크리슈나 차이탄야 칠라라
태현 강
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퀄컴 인코포레이티드
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00315Modifications for increasing the reliability for protection in field-effect transistor circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507Interface arrangements
    • H03K19/018521Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018592Coupling arrangements; Interface arrangements using field effect transistors only with a bidirectional operation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00Parallel/series conversion or vice versa

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020187027960A 2016-03-31 2017-01-25 정전기 방전(esd) 격리형 입력/출력(i/o) 회로들 Active KR102057111B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/088,035 US10298010B2 (en) 2016-03-31 2016-03-31 Electrostatic discharge (ESD) isolated input/output (I/O) circuits
US15/088,035 2016-03-31
PCT/US2017/014949 WO2017172002A1 (en) 2016-03-31 2017-01-25 Electrostatic discharge (esd) isolated input/output (i/o) circuits

Publications (2)

Publication Number Publication Date
KR20180127374A KR20180127374A (ko) 2018-11-28
KR102057111B1 true KR102057111B1 (ko) 2019-12-18

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KR1020187027960A Active KR102057111B1 (ko) 2016-03-31 2017-01-25 정전기 방전(esd) 격리형 입력/출력(i/o) 회로들

Country Status (10)

Country Link
US (1) US10298010B2 (enExample)
EP (1) EP3437193B1 (enExample)
JP (1) JP6687753B2 (enExample)
KR (1) KR102057111B1 (enExample)
CN (1) CN108886363B (enExample)
BR (1) BR112018069912B1 (enExample)
CA (1) CA3016016C (enExample)
ES (1) ES2883349T3 (enExample)
TW (1) TWI672905B (enExample)
WO (1) WO2017172002A1 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10936333B2 (en) 2018-02-28 2021-03-02 Forcepoint Llc System and method for managing system configuration data models
CN110504251B (zh) * 2018-05-18 2021-12-24 世界先进积体电路股份有限公司 集成电路以及静电放电保护电路
US11088541B2 (en) 2018-09-07 2021-08-10 Vanguard International Semiconductor Corporation Integrated circuit and electrostatic discharge protection circuit thereof
CN110137171B (zh) * 2019-05-16 2024-07-19 北京集创北方科技股份有限公司 指纹传感装置及电子设备
TWI706619B (zh) * 2019-05-16 2020-10-01 大陸商北京集創北方科技股份有限公司 具增強靜電放電保護的指紋感測模塊及電子裝置
DE102020132568A1 (de) * 2020-03-31 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Esd-schutzschaltung zum und zugehöriges betriebsverfahren
JP7408595B2 (ja) * 2021-03-30 2024-01-05 株式会社東芝 保護回路
CN113985163B (zh) * 2021-10-15 2024-04-30 深圳市爱协生科技股份有限公司 Esd检测电路、集成电路及电子设备
CN116203308B (zh) * 2021-11-30 2025-10-31 澜起科技股份有限公司 静电放电和电过载的探测电路
US12439702B2 (en) 2022-05-09 2025-10-07 Nxp B.V. Electrostatic discharge protection for wireless device
US11923764B1 (en) * 2022-08-10 2024-03-05 Texas Instruments Incorporated Electrostatic discharge circuit for switching mode power supply

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130335099A1 (en) 2012-06-14 2013-12-19 International Business Machines Corporation Structure and method for dynamic biasing to improve esd robustness of current mode logic (cml) drivers

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5243623A (en) 1990-09-25 1993-09-07 National Semiconductor Corporation Switchable multi-mode transceiver interface device
US5530612A (en) * 1994-03-28 1996-06-25 Intel Corporation Electrostatic discharge protection circuits using biased and terminated PNP transistor chains
US5780897A (en) * 1995-11-13 1998-07-14 Digital Equipment Corporation ESD protection clamp for mixed voltage I/O stages using NMOS transistors
US6785109B1 (en) 2000-01-10 2004-08-31 Altera Corporation Technique for protecting integrated circuit devices against electrostatic discharge damage
US6624992B1 (en) 2000-10-06 2003-09-23 Qualcomm, Incorporated Electro-static discharge protection circuit
US6552583B1 (en) 2001-10-11 2003-04-22 Pericom Semiconductor Corp. ESD-protection device with active R-C coupling to gate of large output transistor
US7026848B2 (en) * 2004-05-18 2006-04-11 Rambus Inc. Pre-driver circuit
US7221551B2 (en) * 2004-06-11 2007-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Cascaded gate-driven ESD clamp
US7102380B2 (en) * 2004-07-07 2006-09-05 Kao Richard F C High speed integrated circuit
JP4986459B2 (ja) * 2006-01-24 2012-07-25 ルネサスエレクトロニクス株式会社 半導体集積回路装置
KR20070115093A (ko) 2006-05-30 2007-12-05 삼성전자주식회사 정전 방전 감지회로를 구비한 반도체 장치
JP5053579B2 (ja) * 2006-06-28 2012-10-17 寛治 大塚 静電気放電保護回路
US7679878B2 (en) * 2007-12-21 2010-03-16 Broadcom Corporation Capacitor sharing surge protection circuit
JP5363879B2 (ja) * 2009-06-03 2013-12-11 ルネサスエレクトロニクス株式会社 ドライバ回路
US8339757B2 (en) * 2010-04-19 2012-12-25 Faraday Technology Corp. Electrostatic discharge circuit for integrated circuit with multiple power domain
US20130010266A1 (en) * 2011-07-05 2013-01-10 Projectiondesign As Compact Projector Head
US8837564B2 (en) * 2011-10-14 2014-09-16 Broadcom Corporation Multi gigabit modem for mmWave point to point links
US9001479B2 (en) * 2012-02-07 2015-04-07 Mediatek Inc. ESD protection circuit
US8760828B2 (en) 2012-03-08 2014-06-24 Taiwan Semiconductor Manufacturing Co., Ltd. Electro-static discharge clamp (ESD) for NxVDD power rail
US8724271B2 (en) * 2012-03-08 2014-05-13 Globalfoundries Singapore Pte. Ltd. ESD-robust I/O driver circuits
DE102014102714A1 (de) * 2014-02-28 2015-09-03 Infineon Technologies Ag Integrierte Schaltung mit ESD-Schutzstruktur und Photonenquelle
CN105099419B (zh) * 2014-04-16 2018-06-22 钰太芯微电子科技(上海)有限公司 具有静电放电保护功能的功率芯片
KR102140734B1 (ko) * 2014-05-14 2020-08-04 삼성전자주식회사 정전 보호 회로를 포함하는 반도체 장치 및 그것의 동작 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130335099A1 (en) 2012-06-14 2013-12-19 International Business Machines Corporation Structure and method for dynamic biasing to improve esd robustness of current mode logic (cml) drivers

Also Published As

Publication number Publication date
BR112018069912A2 (pt) 2019-02-05
TW201810949A (zh) 2018-03-16
BR112018069912B1 (pt) 2023-12-26
ES2883349T3 (es) 2021-12-07
CA3016016C (en) 2021-02-16
CN108886363A (zh) 2018-11-23
KR20180127374A (ko) 2018-11-28
WO2017172002A1 (en) 2017-10-05
CA3016016A1 (en) 2017-10-05
JP6687753B2 (ja) 2020-04-28
EP3437193B1 (en) 2021-07-28
US10298010B2 (en) 2019-05-21
EP3437193A1 (en) 2019-02-06
CN108886363B (zh) 2022-01-14
TWI672905B (zh) 2019-09-21
US20170288398A1 (en) 2017-10-05
JP2019517127A (ja) 2019-06-20

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