KR102030676B1 - 집적 회로에 금속 규화물 구역을 형성하는 방법들 - Google Patents

집적 회로에 금속 규화물 구역을 형성하는 방법들 Download PDF

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KR102030676B1
KR102030676B1 KR1020147005108A KR20147005108A KR102030676B1 KR 102030676 B1 KR102030676 B1 KR 102030676B1 KR 1020147005108 A KR1020147005108 A KR 1020147005108A KR 20147005108 A KR20147005108 A KR 20147005108A KR 102030676 B1 KR102030676 B1 KR 102030676B1
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South Korea
Prior art keywords
zone
silicide
metal
metal silicide
forming
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Korean (ko)
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KR20140063644A (ko
Inventor
마이클 지. 워드
이고르 브이. 페이도우스
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어플라이드 머티어리얼스, 인코포레이티드
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides

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  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
KR1020147005108A 2011-07-27 2012-07-24 집적 회로에 금속 규화물 구역을 형성하는 방법들 Active KR102030676B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161512226P 2011-07-27 2011-07-27
US61/512,226 2011-07-27
US13/547,527 2012-07-12
US13/547,527 US8987102B2 (en) 2011-07-27 2012-07-12 Methods of forming a metal silicide region in an integrated circuit
PCT/US2012/047986 WO2013016341A2 (en) 2011-07-27 2012-07-24 Methods of forming a metal silicide region in an integrated circuit

Publications (2)

Publication Number Publication Date
KR20140063644A KR20140063644A (ko) 2014-05-27
KR102030676B1 true KR102030676B1 (ko) 2019-10-10

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KR1020147005108A Active KR102030676B1 (ko) 2011-07-27 2012-07-24 집적 회로에 금속 규화물 구역을 형성하는 방법들

Country Status (6)

Country Link
US (1) US8987102B2 (https=)
JP (1) JP5992521B2 (https=)
KR (1) KR102030676B1 (https=)
CN (1) CN103650112A (https=)
TW (1) TWI564993B (https=)
WO (1) WO2013016341A2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140065819A1 (en) * 2012-09-03 2014-03-06 Intermolecular, Inc. Methods and Systems for Low Resistance Contact Formation
US11012461B2 (en) 2016-10-27 2021-05-18 Accenture Global Solutions Limited Network device vulnerability prediction
KR102827622B1 (ko) * 2019-03-20 2025-06-30 도쿄엘렉트론가부시키가이샤 반도체 소자를 위한 금속 규화물을 선택적으로 형성하는 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053017A (ja) * 1999-08-06 2001-02-23 Hitachi Ltd 半導体装置の製造方法
JP2003188274A (ja) 2001-12-19 2003-07-04 Toshiba Corp 半導体装置及びその製造方法
US20100164001A1 (en) * 2008-12-30 2010-07-01 Joodong Park Implant process for blocked salicide poly resistor and structures formed thereby

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106566A (ja) * 1993-10-01 1995-04-21 Nippondenso Co Ltd 半導体装置の製造方法
JPH0923005A (ja) * 1995-07-06 1997-01-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH0964349A (ja) * 1995-08-22 1997-03-07 Sony Corp 高融点シリサイドを持つ半導体装置とその製造方法
KR100273271B1 (ko) * 1998-01-16 2001-02-01 김영환 실리사이드제조방법
US6403472B1 (en) 1999-06-23 2002-06-11 Harris Corporation Method of forming resistive contacts on intergrated circuits with mobility spoiling ions including high resistive contacts and low resistivity silicide contacts
FR2856514A1 (fr) 2003-06-20 2004-12-24 St Microelectronics Sa Procede de formation selective de siliciure sur une plaque de materiau semi-conducteur
JP2005093907A (ja) * 2003-09-19 2005-04-07 Sharp Corp 半導体装置およびその製造方法
JP2006196646A (ja) * 2005-01-13 2006-07-27 Renesas Technology Corp 半導体装置及びその製造方法
JP2007019205A (ja) * 2005-07-07 2007-01-25 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US7576407B2 (en) * 2006-04-26 2009-08-18 Samsung Electronics Co., Ltd. Devices and methods for constructing electrically programmable integrated fuses for low power applications
US7807556B2 (en) * 2006-12-05 2010-10-05 General Electric Company Method for doping impurities
JP2010016302A (ja) * 2008-07-07 2010-01-21 Panasonic Corp 半導体装置及びその製造方法
KR101149043B1 (ko) * 2009-10-30 2012-05-24 에스케이하이닉스 주식회사 매립형 비트라인을 구비하는 반도체 장치 및 그 제조방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053017A (ja) * 1999-08-06 2001-02-23 Hitachi Ltd 半導体装置の製造方法
JP2003188274A (ja) 2001-12-19 2003-07-04 Toshiba Corp 半導体装置及びその製造方法
US20100164001A1 (en) * 2008-12-30 2010-07-01 Joodong Park Implant process for blocked salicide poly resistor and structures formed thereby

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Publication number Publication date
KR20140063644A (ko) 2014-05-27
US20130026617A1 (en) 2013-01-31
JP2014524158A (ja) 2014-09-18
TWI564993B (zh) 2017-01-01
WO2013016341A3 (en) 2013-04-18
US8987102B2 (en) 2015-03-24
TW201306174A (zh) 2013-02-01
CN103650112A (zh) 2014-03-19
JP5992521B2 (ja) 2016-09-14
WO2013016341A2 (en) 2013-01-31

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