KR101881861B1 - 도전 패턴 구조물 및 이의 형성 방법 - Google Patents

도전 패턴 구조물 및 이의 형성 방법 Download PDF

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Publication number
KR101881861B1
KR101881861B1 KR1020110041497A KR20110041497A KR101881861B1 KR 101881861 B1 KR101881861 B1 KR 101881861B1 KR 1020110041497 A KR1020110041497 A KR 1020110041497A KR 20110041497 A KR20110041497 A KR 20110041497A KR 101881861 B1 KR101881861 B1 KR 101881861B1
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KR
South Korea
Prior art keywords
manufacturing
same
pattern structure
electrical pattern
electrical
Prior art date
Application number
KR1020110041497A
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English (en)
Other versions
KR20120123889A (ko
Inventor
김회승
최길현
박지순
이종명
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020110041497A priority Critical patent/KR101881861B1/ko
Priority to US13/440,123 priority patent/US8592979B2/en
Publication of KR20120123889A publication Critical patent/KR20120123889A/ko
Application granted granted Critical
Publication of KR101881861B1 publication Critical patent/KR101881861B1/ko

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/46—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/47—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a floating-gate layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020110041497A 2011-05-02 2011-05-02 도전 패턴 구조물 및 이의 형성 방법 KR101881861B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020110041497A KR101881861B1 (ko) 2011-05-02 2011-05-02 도전 패턴 구조물 및 이의 형성 방법
US13/440,123 US8592979B2 (en) 2011-05-02 2012-04-05 Semiconductor device conductive pattern structures and methods of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110041497A KR101881861B1 (ko) 2011-05-02 2011-05-02 도전 패턴 구조물 및 이의 형성 방법

Publications (2)

Publication Number Publication Date
KR20120123889A KR20120123889A (ko) 2012-11-12
KR101881861B1 true KR101881861B1 (ko) 2018-07-25

Family

ID=47089718

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110041497A KR101881861B1 (ko) 2011-05-02 2011-05-02 도전 패턴 구조물 및 이의 형성 방법

Country Status (2)

Country Link
US (1) US8592979B2 (ko)
KR (1) KR101881861B1 (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101762657B1 (ko) * 2011-01-31 2017-07-31 삼성전자주식회사 도전 패턴 구조물 및 이의 형성 방법
US20170256449A1 (en) * 2016-03-07 2017-09-07 Globalfoundries Inc. Methods of forming conductive structures with different material compositions in a metallization layer

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050047661A (ko) * 2003-11-18 2005-05-23 삼성전자주식회사 구리 배선 및 커패시터를 포함하는 반도체 장치의 제조방법.
US20050191844A1 (en) * 2000-08-15 2005-09-01 Farrar Paul A. Low capacitance wiring layout and method for making same
KR20070013744A (ko) * 2005-07-27 2007-01-31 동부일렉트로닉스 주식회사 반도체 소자의 금속배선 형성방법
JP2009141064A (ja) * 2007-12-05 2009-06-25 Renesas Technology Corp 半導体装置
KR20090080465A (ko) * 2008-01-21 2009-07-24 주식회사 하이닉스반도체 비휘발성 메모리 소자의 금속 배선 형성 방법
JP2009187988A (ja) * 2008-02-01 2009-08-20 Toshiba Corp 半導体装置及びその製造方法
KR20110046921A (ko) * 2009-10-29 2011-05-06 삼성전자주식회사 도전 패턴 구조물 및 그 제조 방법
KR20120088181A (ko) * 2011-01-31 2012-08-08 삼성전자주식회사 도전 패턴 구조물 및 이의 형성 방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4489345B2 (ja) * 2002-12-13 2010-06-23 株式会社ルネサステクノロジ 半導体装置の製造方法
JP4976120B2 (ja) 2006-06-14 2012-07-18 日本エレクトロプレイテイング・エンジニヤース株式会社 ウェハーめっき方法
KR20080019501A (ko) 2006-08-28 2008-03-04 장용호 압축티슈가 수용된 생수병 마개
US7586175B2 (en) 2006-10-23 2009-09-08 Samsung Electronics Co., Ltd. Semiconductor wafer having embedded electroplating current paths to provide uniform plating over wafer surface
JP4989541B2 (ja) 2008-03-31 2012-08-01 ルネサスエレクトロニクス株式会社 めっき方法、半導体装置の製造方法およびめっき処理システム
KR101535653B1 (ko) * 2009-02-09 2015-07-10 삼성전자주식회사 상변화 메모리 소자의 제조방법

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050191844A1 (en) * 2000-08-15 2005-09-01 Farrar Paul A. Low capacitance wiring layout and method for making same
KR20050047661A (ko) * 2003-11-18 2005-05-23 삼성전자주식회사 구리 배선 및 커패시터를 포함하는 반도체 장치의 제조방법.
KR20070013744A (ko) * 2005-07-27 2007-01-31 동부일렉트로닉스 주식회사 반도체 소자의 금속배선 형성방법
JP2009141064A (ja) * 2007-12-05 2009-06-25 Renesas Technology Corp 半導体装置
KR20090080465A (ko) * 2008-01-21 2009-07-24 주식회사 하이닉스반도체 비휘발성 메모리 소자의 금속 배선 형성 방법
JP2009187988A (ja) * 2008-02-01 2009-08-20 Toshiba Corp 半導体装置及びその製造方法
KR20110046921A (ko) * 2009-10-29 2011-05-06 삼성전자주식회사 도전 패턴 구조물 및 그 제조 방법
KR20120088181A (ko) * 2011-01-31 2012-08-08 삼성전자주식회사 도전 패턴 구조물 및 이의 형성 방법

Also Published As

Publication number Publication date
KR20120123889A (ko) 2012-11-12
US8592979B2 (en) 2013-11-26
US20120280391A1 (en) 2012-11-08

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