KR101813905B1 - 반도체 패키지의 쓰루홀 구조의 향상된 배열 - Google Patents

반도체 패키지의 쓰루홀 구조의 향상된 배열 Download PDF

Info

Publication number
KR101813905B1
KR101813905B1 KR1020167004969A KR20167004969A KR101813905B1 KR 101813905 B1 KR101813905 B1 KR 101813905B1 KR 1020167004969 A KR1020167004969 A KR 1020167004969A KR 20167004969 A KR20167004969 A KR 20167004969A KR 101813905 B1 KR101813905 B1 KR 101813905B1
Authority
KR
South Korea
Prior art keywords
edge
rectangular
holes
hole
edges
Prior art date
Application number
KR1020167004969A
Other languages
English (en)
Korean (ko)
Other versions
KR20160039246A (ko
Inventor
웽 홍 테
사라 케이 하니
치 황 림
Original Assignee
인텔 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인텔 코포레이션 filed Critical 인텔 코포레이션
Publication of KR20160039246A publication Critical patent/KR20160039246A/ko
Application granted granted Critical
Publication of KR101813905B1 publication Critical patent/KR101813905B1/ko

Links

Images

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00134Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
    • B81C1/0015Cantilevers
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B3/00Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
    • B81B3/0035Constitution or structural means for controlling the movement of the flexible or deformable elements
    • B81B3/0051For defining the movement, i.e. structures that guide or limit the movement of an element
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00444Surface micromachining, i.e. structuring layers on the substrate
    • B81C1/00468Releasing structures
    • B81C1/00476Releasing structures removing a sacrificial layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00Microstructural systems or auxiliary parts thereof
    • B81B2207/01Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
    • B81B2207/015Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS the micromechanical device and the control or processing electronics being integrated on the same substrate
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00Forming microstructural systems
    • B81C2203/07Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0707Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
    • B81C2203/0714Forming the micromechanical structure with a CMOS process
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00Forming microstructural systems
    • B81C2203/07Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0707Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
    • B81C2203/0735Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00Forming microstructural systems
    • B81C2203/07Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0707Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
    • B81C2203/0757Topology for facilitating the monolithic integration
    • B81C2203/0771Stacking the electronic processing unit and the micromechanical structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Micromachines (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
KR1020167004969A 2013-09-27 2013-09-27 반도체 패키지의 쓰루홀 구조의 향상된 배열 KR101813905B1 (ko)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2013/062457 WO2015047346A1 (en) 2013-09-27 2013-09-27 An improved arrangement of through-hole structures of a semiconductor package

Publications (2)

Publication Number Publication Date
KR20160039246A KR20160039246A (ko) 2016-04-08
KR101813905B1 true KR101813905B1 (ko) 2018-01-02

Family

ID=52744240

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020167004969A KR101813905B1 (ko) 2013-09-27 2013-09-27 반도체 패키지의 쓰루홀 구조의 향상된 배열

Country Status (6)

Country Link
US (1) US20150217995A1 (ja)
EP (1) EP3050116B1 (ja)
JP (1) JP6205496B2 (ja)
KR (1) KR101813905B1 (ja)
CN (1) CN104512858A (ja)
WO (1) WO2015047346A1 (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104865002B (zh) * 2015-05-05 2017-04-12 苏州曼普拉斯传感科技有限公司 一种mems压力传感器装置及封装方法
US9997428B2 (en) 2015-07-14 2018-06-12 Avago Technologies General Ip (Singapore) Pte. Ltd. Via structures for thermal dissipation
US10129972B2 (en) 2015-10-30 2018-11-13 Avago Technologies International Sales Pte. Limited Frame elements for package structures comprising printed circuit boards (PCBs)
US10199424B1 (en) * 2017-07-19 2019-02-05 Meridian Innovation Pte Ltd Thermoelectric-based infrared detector having a cavity and a MEMS structure defined by BEOL metals lines
US20190169020A1 (en) * 2017-12-05 2019-06-06 Intel Corporation Package substrate integrated devices

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005514728A (ja) * 2001-11-07 2005-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション Cmos適合性基板上にマイクロ電気機械スイッチを作製する方法
JP2005300403A (ja) * 2004-04-14 2005-10-27 Denso Corp 半導体力学量センサ
JP2007015035A (ja) 2005-07-05 2007-01-25 Advanced Telecommunication Research Institute International 微小構造体の製造方法
US20100020991A1 (en) * 2008-07-25 2010-01-28 United Microelectronics Corp. Diaphragm of mems electroacoustic transducer
JP2010155306A (ja) * 2008-12-26 2010-07-15 Panasonic Corp Memsデバイス及びその製造方法
US20130056840A1 (en) * 2011-09-02 2013-03-07 Nxp B.V. Acoustic transducers with perforated membranes

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7541214B2 (en) * 1999-12-15 2009-06-02 Chang-Feng Wan Micro-electro mechanical device made from mono-crystalline silicon and method of manufacture therefore
KR100416266B1 (ko) * 2001-12-18 2004-01-24 삼성전자주식회사 막힌 희생층 지지대를 갖는 멤스 구조물 및 그의 제작방법
US20070241655A1 (en) * 2004-03-30 2007-10-18 Kazuto Sakemura Electron Emitting Device and Manufacturing Method Thereof and Image Pick Up Device or Display Device Using Electron Emitting Device
US7178400B2 (en) * 2004-04-14 2007-02-20 Denso Corporation Physical quantity sensor having multiple through holes
JP4215076B2 (ja) * 2006-07-10 2009-01-28 ヤマハ株式会社 コンデンサマイクロホン及びその製造方法
EP1908727A1 (en) * 2006-10-03 2008-04-09 Seiko Epson Corporation Wafer-level MEMS package and manufacturing method thereof
JP4726927B2 (ja) * 2008-06-19 2011-07-20 株式会社日立製作所 集積化マイクロエレクトロメカニカルシステムおよびその製造方法
US8709264B2 (en) * 2010-06-25 2014-04-29 International Business Machines Corporation Planar cavity MEMS and related structures, methods of manufacture and design structures
JP5813471B2 (ja) * 2011-11-11 2015-11-17 株式会社東芝 Mems素子
US9708178B2 (en) * 2011-12-30 2017-07-18 Intel Corporation Integration of laminate MEMS in BBUL coreless package
EP2658288B1 (en) * 2012-04-27 2014-06-11 Nxp B.V. Acoustic transducers with perforated membranes
JP2014155980A (ja) * 2013-02-15 2014-08-28 Toshiba Corp 電気部品およびその製造方法
US8692340B1 (en) * 2013-03-13 2014-04-08 Invensense, Inc. MEMS acoustic sensor with integrated back cavity

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005514728A (ja) * 2001-11-07 2005-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション Cmos適合性基板上にマイクロ電気機械スイッチを作製する方法
JP2005300403A (ja) * 2004-04-14 2005-10-27 Denso Corp 半導体力学量センサ
JP2007015035A (ja) 2005-07-05 2007-01-25 Advanced Telecommunication Research Institute International 微小構造体の製造方法
US20100020991A1 (en) * 2008-07-25 2010-01-28 United Microelectronics Corp. Diaphragm of mems electroacoustic transducer
JP2010155306A (ja) * 2008-12-26 2010-07-15 Panasonic Corp Memsデバイス及びその製造方法
US20130056840A1 (en) * 2011-09-02 2013-03-07 Nxp B.V. Acoustic transducers with perforated membranes

Also Published As

Publication number Publication date
EP3050116A4 (en) 2017-05-03
EP3050116A1 (en) 2016-08-03
US20150217995A1 (en) 2015-08-06
KR20160039246A (ko) 2016-04-08
JP2016531011A (ja) 2016-10-06
CN104512858A (zh) 2015-04-15
EP3050116B1 (en) 2019-02-27
WO2015047346A1 (en) 2015-04-02
JP6205496B2 (ja) 2017-09-27

Similar Documents

Publication Publication Date Title
KR101631191B1 (ko) 기계적 퓨즈를 갖는 반도체 패키지
KR101588723B1 (ko) 실리콘 쓰루 비아를 사용하는 반도체 패키지 공정
KR101813905B1 (ko) 반도체 패키지의 쓰루홀 구조의 향상된 배열
US9200973B2 (en) Semiconductor package with air pressure sensor
KR101863462B1 (ko) 범프리스 빌드업 층을 위한 범프리스 다이 패키지 인터페이스
US9319799B2 (en) Microphone package with integrated substrate
TWI640077B (zh) 在具有埋入晶粒之無凸塊式增層基板上使用貫矽導孔的晶粒堆疊及其形成方法
US20140001583A1 (en) Method to inhibit metal-to-metal stiction issues in mems fabrication
US20170225946A1 (en) Integration of laminate mems in bbul coreless package
TWI580631B (zh) 用於提供半導體封裝之mems結構的裝置、系統及方法
CN115799209A (zh) 实现30微米或更低间距emib的新方法
US20170148719A1 (en) Through-electrode substrate, method for manufacturing same, and semiconductor device in which through-electrode substrate is used
US8736076B2 (en) Multi-chip stacking of integrated circuit devices using partial device overlap
US8039306B2 (en) 3D integration of vertical components in reconstituted substrates

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant