KR101799357B1 - Dram 서브-어레이 레벨 리프레시 - Google Patents

Dram 서브-어레이 레벨 리프레시 Download PDF

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Publication number
KR101799357B1
KR101799357B1 KR1020167002714A KR20167002714A KR101799357B1 KR 101799357 B1 KR101799357 B1 KR 101799357B1 KR 1020167002714 A KR1020167002714 A KR 1020167002714A KR 20167002714 A KR20167002714 A KR 20167002714A KR 101799357 B1 KR101799357 B1 KR 101799357B1
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South Korea
Prior art keywords
sub
dram
refresh
row
array
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English (en)
Korean (ko)
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KR20160030212A (ko
Inventor
시앙유 동
정원 서
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
KR1020167002714A 2013-07-05 2014-05-23 Dram 서브-어레이 레벨 리프레시 Expired - Fee Related KR101799357B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361843110P 2013-07-05 2013-07-05
US61/843,110 2013-07-05
US14/088,098 2013-11-22
US14/088,098 US8982654B2 (en) 2013-07-05 2013-11-22 DRAM sub-array level refresh
PCT/US2014/039385 WO2015002704A1 (en) 2013-07-05 2014-05-23 Dram sub-array level refresh

Publications (2)

Publication Number Publication Date
KR20160030212A KR20160030212A (ko) 2016-03-16
KR101799357B1 true KR101799357B1 (ko) 2017-11-20

Family

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KR1020167002714A Expired - Fee Related KR101799357B1 (ko) 2013-07-05 2014-05-23 Dram 서브-어레이 레벨 리프레시

Country Status (6)

Country Link
US (1) US8982654B2 (enExample)
EP (1) EP3017452B1 (enExample)
JP (1) JP6227774B2 (enExample)
KR (1) KR101799357B1 (enExample)
CN (1) CN105378846B (enExample)
WO (1) WO2015002704A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9524771B2 (en) 2013-07-12 2016-12-20 Qualcomm Incorporated DRAM sub-array level autonomic refresh memory controller optimization
US9721640B2 (en) * 2015-12-09 2017-08-01 Intel Corporation Performance of additional refresh operations during self-refresh mode
US9659626B1 (en) * 2015-12-26 2017-05-23 Intel Corporation Memory refresh operation with page open
US9514800B1 (en) * 2016-03-26 2016-12-06 Bo Liu DRAM and self-refresh method
US9824742B1 (en) 2016-04-28 2017-11-21 Qualcomm Incorporated DRAM access in self-refresh state
CN110556139B (zh) * 2018-05-31 2021-06-18 联发科技股份有限公司 用以控制存储器的电路及相关的方法
US10535393B1 (en) * 2018-07-21 2020-01-14 Advanced Micro Devices, Inc. Configuring dynamic random access memory refreshes for systems having multiple ranks of memory
US10991414B2 (en) * 2019-04-12 2021-04-27 Western Digital Technologies, Inc. Granular refresh rate control for memory devices based on bit position
US10991413B2 (en) * 2019-07-03 2021-04-27 Micron Technology, Inc. Memory with programmable die refresh stagger
US20210064368A1 (en) * 2019-08-28 2021-03-04 Micron Technology, Inc. Command tracking
CN111158585B (zh) * 2019-11-27 2023-08-01 核芯互联科技(青岛)有限公司 一种内存控制器刷新优化方法、装置、设备和存储介质
KR20240067516A (ko) * 2022-11-09 2024-05-17 삼성전자주식회사 메모리 장치 및 그의 동작 방법
US12406716B2 (en) 2023-12-05 2025-09-02 Nxp Usa, Inc. Refresh operations in embedded dynamic random access memories (DRAMs)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110141836A1 (en) 2009-12-16 2011-06-16 Innovative Silicon Isi Sa Techniques for reducing impact of array disturbs in a semiconductor memory device
US20110225355A1 (en) 2010-03-12 2011-09-15 Elpida Memory Inc. Semiconductor device, refresh control method thereof and computer system

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US4344157A (en) * 1978-06-26 1982-08-10 Texas Instruments Incorporated On-chip refresh address generator for dynamic memory
US5313428A (en) * 1987-11-12 1994-05-17 Sharp Kabushiki Kaisha Field memory self-refreshing device utilizing a refresh clock signal selected from two separate clock signals
US5307320A (en) 1992-09-23 1994-04-26 Intel Corporation High integration DRAM controller
KR950014089B1 (ko) * 1993-11-08 1995-11-21 현대전자산업주식회사 동기식 디램의 히든 셀프 리프레쉬 방법 및 장치
JPH09306165A (ja) * 1996-05-16 1997-11-28 Hitachi Commun Syst Inc Ｄｒａｍリフレッシュ制御回路
US5818777A (en) * 1997-03-07 1998-10-06 Micron Technology, Inc. Circuit for implementing and method for initiating a self-refresh mode
US6697909B1 (en) 2000-09-12 2004-02-24 International Business Machines Corporation Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory
JP2002216473A (ja) 2001-01-16 2002-08-02 Matsushita Electric Ind Co Ltd 半導体メモリ装置
US6560155B1 (en) * 2001-10-24 2003-05-06 Micron Technology, Inc. System and method for power saving memory refresh for dynamic random access memory devices after an extended interval
US6721224B2 (en) * 2002-08-26 2004-04-13 Mosel Vitelic, Inc. Memory refresh methods and circuits
US7088632B2 (en) 2004-05-26 2006-08-08 Freescale Semiconductor, Inc. Automatic hidden refresh in a dram and method therefor
JP2006107245A (ja) * 2004-10-07 2006-04-20 Canon Inc メモリコントローラ
US7313047B2 (en) 2006-02-23 2007-12-25 Hynix Semiconductor Inc. Dynamic semiconductor memory with improved refresh mechanism
JP4117323B2 (ja) * 2006-04-18 2008-07-16 エルピーダメモリ株式会社 半導体記憶装置
JP5428687B2 (ja) * 2009-09-14 2014-02-26 株式会社リコー メモリ制御装置
KR101861647B1 (ko) * 2011-05-24 2018-05-28 삼성전자주식회사 메모리 시스템 및 그 리프레시 제어 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110141836A1 (en) 2009-12-16 2011-06-16 Innovative Silicon Isi Sa Techniques for reducing impact of array disturbs in a semiconductor memory device
US20110225355A1 (en) 2010-03-12 2011-09-15 Elpida Memory Inc. Semiconductor device, refresh control method thereof and computer system

Also Published As

Publication number Publication date
EP3017452A1 (en) 2016-05-11
US8982654B2 (en) 2015-03-17
US20150009769A1 (en) 2015-01-08
EP3017452B1 (en) 2017-08-16
WO2015002704A1 (en) 2015-01-08
KR20160030212A (ko) 2016-03-16
JP6227774B2 (ja) 2017-11-08
CN105378846A (zh) 2016-03-02
JP2016526749A (ja) 2016-09-05
CN105378846B (zh) 2018-08-31

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