KR101690376B1 - 구조적 지연 고장 테스트를 위한 커버리지 증대 및 전력 인식 클록 시스템 - Google Patents

구조적 지연 고장 테스트를 위한 커버리지 증대 및 전력 인식 클록 시스템 Download PDF

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Publication number
KR101690376B1
KR101690376B1 KR1020140161033A KR20140161033A KR101690376B1 KR 101690376 B1 KR101690376 B1 KR 101690376B1 KR 1020140161033 A KR1020140161033 A KR 1020140161033A KR 20140161033 A KR20140161033 A KR 20140161033A KR 101690376 B1 KR101690376 B1 KR 101690376B1
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South Korea
Prior art keywords
clock
scan
gating cell
test
clock gating
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English (en)
Korean (ko)
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KR20150058060A (ko
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젠 송 리
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인피니언 테크놀로지스 아게
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318575—Power distribution; Power saving
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
KR1020140161033A 2013-11-19 2014-11-18 구조적 지연 고장 테스트를 위한 커버리지 증대 및 전력 인식 클록 시스템 Expired - Fee Related KR101690376B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/083,624 US9377511B2 (en) 2013-11-19 2013-11-19 Coverage enhancement and power aware clock system for structural delay-fault test
US14/083,624 2013-11-19

Publications (2)

Publication Number Publication Date
KR20150058060A KR20150058060A (ko) 2015-05-28
KR101690376B1 true KR101690376B1 (ko) 2016-12-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020140161033A Expired - Fee Related KR101690376B1 (ko) 2013-11-19 2014-11-18 구조적 지연 고장 테스트를 위한 커버리지 증대 및 전력 인식 클록 시스템

Country Status (4)

Country Link
US (1) US9377511B2 (enExample)
JP (1) JP2015099146A (enExample)
KR (1) KR101690376B1 (enExample)
DE (1) DE102014017099A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230059328A (ko) * 2021-10-26 2023-05-03 연세대학교 산학협력단 로직 비스트 캡쳐 전력 감소 회로 및 방법

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10447461B2 (en) * 2015-12-01 2019-10-15 Infineon Technologies Austria Ag Accessing data via different clocks
CN106992770B (zh) * 2016-01-21 2021-03-30 华为技术有限公司 时钟电路及其传输时钟信号的方法
US12210058B1 (en) * 2022-07-29 2025-01-28 Marvell Asia Pte Ltd Clock gating for power reduction during testing

Citations (3)

* Cited by examiner, † Cited by third party
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US20050138511A1 (en) * 2003-11-24 2005-06-23 Robert Benware Self-timed scan circuit for ASIC fault testing
US20100332928A1 (en) * 2009-06-26 2010-12-30 Wei Li Scalable scan system for system-on-chip design
US20110296265A1 (en) * 2010-05-25 2011-12-01 Freescale Semiconductor, Inc System for testing integrated circuit with asynchronous clock domains

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US8091002B2 (en) * 2001-02-15 2012-01-03 Syntest Technologies, Inc. Multiple-capture DFT system to reduce peak capture power during self-test or scan test
JP4627118B2 (ja) * 2001-04-26 2011-02-09 ルネサスエレクトロニクス株式会社 スキャンテスト用回路
US6880137B1 (en) * 2001-08-03 2005-04-12 Inovys Dynamically reconfigurable precision signal delay test system for automatic test equipment
JP2005032102A (ja) * 2003-07-09 2005-02-03 Matsushita Electric Ind Co Ltd スキャンテスト設計方法、スキャンテスト回路、スキャンフリップフロップ回路、スキャンテスト回路挿入用ｃａｄプログラム、大規模集積回路及び携帯デジタル機器
WO2006064300A1 (en) * 2004-12-13 2006-06-22 Infineon Technologies Ag Circuitry and method for an at-speed scan test
US7613971B2 (en) * 2005-02-08 2009-11-03 Nec Electronics Corporation Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit
TW200801550A (en) * 2006-01-06 2008-01-01 Koninkl Philips Electronics Nv IC testing methods and apparatus
US20080282122A1 (en) * 2007-05-09 2008-11-13 Amar Guettaf Single scan clock in a multi-clock domain
US20100138709A1 (en) * 2008-10-22 2010-06-03 Laung-Terng Wang Method and apparatus for delay fault coverage enhancement
JP5275136B2 (ja) 2009-05-28 2013-08-28 ルネサスエレクトロニクス株式会社 半導体集積回路
JP5845187B2 (ja) * 2010-10-05 2016-01-20 国立研究開発法人科学技術振興機構 故障検出システム、取出装置、故障検出方法、プログラム及び記録媒体
US8862955B2 (en) * 2010-12-29 2014-10-14 Stmicroelectronics S.R.L. Apparatus for at-speed testing, in inter-domain mode, of a multi-clock-domain digital integrated circuit according to BIST or SCAN techniques
JP2013156073A (ja) 2012-01-27 2013-08-15 Renesas Electronics Corp 半導体装置
JP2013224917A (ja) * 2012-03-22 2013-10-31 Renesas Electronics Corp スキャンテスト回路、テストパタン生成制御回路及びスキャンテスト制御方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050138511A1 (en) * 2003-11-24 2005-06-23 Robert Benware Self-timed scan circuit for ASIC fault testing
US20100332928A1 (en) * 2009-06-26 2010-12-30 Wei Li Scalable scan system for system-on-chip design
US20110296265A1 (en) * 2010-05-25 2011-12-01 Freescale Semiconductor, Inc System for testing integrated circuit with asynchronous clock domains

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230059328A (ko) * 2021-10-26 2023-05-03 연세대학교 산학협력단 로직 비스트 캡쳐 전력 감소 회로 및 방법
KR102630258B1 (ko) 2021-10-26 2024-01-25 연세대학교 산학협력단 로직 비스트 캡쳐 전력 감소 회로 및 방법

Also Published As

Publication number Publication date
KR20150058060A (ko) 2015-05-28
DE102014017099A1 (de) 2015-05-21
US9377511B2 (en) 2016-06-28
US20150143189A1 (en) 2015-05-21
JP2015099146A (ja) 2015-05-28

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