KR101682555B1 - Method of manufacturing a fine pattern printed circuit board - Google Patents

Method of manufacturing a fine pattern printed circuit board Download PDF

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Publication number
KR101682555B1
KR101682555B1 KR1020150111343A KR20150111343A KR101682555B1 KR 101682555 B1 KR101682555 B1 KR 101682555B1 KR 1020150111343 A KR1020150111343 A KR 1020150111343A KR 20150111343 A KR20150111343 A KR 20150111343A KR 101682555 B1 KR101682555 B1 KR 101682555B1
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KR
South Korea
Prior art keywords
copper foil
copper
copper plating
plating
manufacturing
Prior art date
Application number
KR1020150111343A
Other languages
Korean (ko)
Inventor
김태진
김범준
윤영모
이정후
Original Assignee
대덕전자 주식회사
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Priority to KR1020150111343A priority Critical patent/KR101682555B1/en
Application granted granted Critical
Publication of KR101682555B1 publication Critical patent/KR101682555B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching

Abstract

In manufacturing an embedded trace substrate having a fine pattern, soft etching is performed before the copper plating so that the copper plating bump is firmly embedded in the copper foil. As a result, it is possible to prevent defects in which chemicals are seeped into the interfaces and the copper plating bumps are lifted off or defects are generated.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a fine pattern manufacturing method,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board, in particular, an embedded trace substrate (ETS), and more particularly to a method of manufacturing a fine pattern on an ETS substrate and a bump structure manufactured according to the method .

ETS method is used to increase the circuit density of printed circuit board. The ETS method is advantageous in miniaturizing the circuit pitch because the copper foil circuit is manufactured in a buried form in the insulating layer instead of forming the copper foil circuit on the surface of the insulating layer.

1A to 1G are views showing a process of manufacturing a copper foil pattern according to the ETS method according to the related art. 1A, a carrier 100 having a copper foil 100c coated with an adhesive 100b on a thick copper foil 100a serving as a support is used as a starting material. Referring to FIG. 1B, a dry film 110 is coated on the carrier 100, and a series of photo operations such as photo, development, etching, and the like are performed to transfer a predetermined circuit pattern to the dry film 110.

Referring to FIG. 1C, when the patterning is performed using the dry film 110 as a plating mask, copper plating bumps 120 are formed on the exposed copper foil 100c. Then, referring to FIG. 1E, when the insulating layer 130 is laminated and laminated by heating and pressing, the copper plating bump 120 is embedded (buried) into the insulating layer. Referring to FIG. 1F, the carrier copper foil 100a, which has been in contact with the structure through the adhesive layer 100b, is separated. Then, when the copper foil 100c is etched away by soft etching, a pattern in which copper plating bumps are embedded in the insulating layer 130 is formed as shown in FIG. 1G.

However, in the prior art, when the pattern size of the copper plating bump 120 is fine to the order of several micrometers, in the state where the adhesion force between the copper plating bump 120 and the copper foil 100c is insufficient, The chemical solution used in the preprocessing process penetrates into the interface between the copper plating and the copper foil, and the copper plating bump 120 may be peeled off or etched to cause undercut.

FIGS. 2A and 2B show that when the ETS process is performed according to the related art, the interface is attacked by the chemical solution during the pretreatment washing process or the brown oxide (BRO) process, and the copper plating bump 120 is peeled off, Or undercut caused by etching.

A first object of the present invention is to provide a method of manufacturing a copper plating bump in manufacturing a fine patterned ETS substrate.

A second object of the present invention is to provide a method of manufacturing a copper plating bump excellent in adhesion even when the pattern length and pitch are reduced to several micrometers.

A method of manufacturing an embedded trace substrate comprising the steps of: (a) preparing a copper foil formed on a digitizable material; (b) applying a dry film on the copper foil and transferring a circuit pattern to form a plating mask; (c) soft-etching (S / E) the surface of the copper foil exposed by the plating mask to clean the copper foil surface; (d) performing copper plating on a copper foil whose surface is exposed using the plating mask as a mask to form a copper plating bump; And (e) peeling off the dry film to expose the copper plating bumps.

The present invention provides soft adhesion at the interface between the copper plating bump and the copper foil because the copper plating bumps are embedded in the copper foil by soft etching before copper plating. As a result, it is possible to prevent defects in which chemicals are seeped into the interfaces and the copper plating bumps are lifted off or defects are generated.

1A to 1G are views showing a process of manufacturing a copper foil pattern according to the ETS method according to the related art.
FIGS. 2A and 2B are diagrams showing a copper plating bump separation problem and an undercut problem when the ETS process is performed according to the related art. FIG.
FIGS. 3A through 3E illustrate a process of manufacturing a copper foil pattern according to the ETS method according to the present invention. FIG.

Hereinafter, a method of manufacturing an ETS substrate according to the present invention will be described in detail with reference to FIGS. 3A to 3E. Referring to FIG. 3A, a carrier 100 having a copper foil 100c coated with an adhesive 100b on a thick copper foil 100a serving as a support is used as a starting material. As another embodiment of the present invention, a detachable core may be used, or a copper clad laminate (CCL) may be laminated with a copper foil. In other words, reference numeral 100a denotes a separable material (core), 100b denotes a copper foil, and 100c denotes an adhesive for temporarily bonding the separable material 100a and the copper foil 100c.

Referring to FIG. 3B, a dry film 110 is coated on the carrier 100, and a series of photo operations such as photo, development, etching, and the like are performed to transfer a predetermined circuit pattern to the dry film 110.

Referring to FIG. 3C, the surface of the exposed copper foil 100c is slightly etched by performing soft etching (S / E) before copper plating is performed. This soft etching process cleans the surface of the copper foil and enhances the adhesion with the copper plating in the subsequent copper plating process.

When copper plating is performed using the dry film 110 transferred with the pattern as a plating mask, copper plating bumps 120 are formed on the exposed copper foil 100c. Referring to FIG. 3E, in the case of the present invention, the effect that the copper plating bump 120 is firmly embedded in the soft-etched copper foil 100c occurs.

Then, the process of laminating the insulating layer 130, heating and pressurizing the laminate, separating the carrier copper foil, and embedding the copper foil circuit in the insulating layer 130 is the same as the process of the prior arts 1F and 1G.

The foregoing has somewhat improved the features and technical advantages of the present invention in order to better understand the claims of the invention described below. Additional features and advantages that constitute the claims of the present invention will be described in detail below. It is to be appreciated by those skilled in the art that the disclosed concepts and specific embodiments of the invention can be used immediately as a basis for designing or modifying other structures to accomplish the invention and similar purposes.

In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures to accomplish the same purpose of the present invention. It will be apparent to those skilled in the art that various modifications, substitutions and alterations can be made hereto without departing from the spirit or scope of the invention as defined in the appended claims.

The present invention provides soft adhesion at the interface between the copper plating bump and the copper foil because the copper plating bumps are embedded in the copper foil by soft etching before copper plating. As a result, it is possible to prevent defects in which chemicals are seeped into the interfaces and the copper plating bumps are lifted off or defects are generated.

Claims (1)

A method of manufacturing an embedded trace substrate,
(a) preparing a copper foil formed on a digitizable material;
(b) applying a dry film on the copper foil and transferring a circuit pattern to form a plating mask;
(c) soft-etching (S / E) the surface of the copper foil exposed by the plating mask to clean the copper foil surface;
(d) performing copper plating on a copper foil whose surface is exposed using the plating mask as a mask to form a copper plating bump;
(e) peeling off the dry film to expose the copper plating bump;
(f) laminating an insulating layer on the exposed copper plating bump and heating and pressing;
(g) exposing the copper foil surface by separating the decatable material from the resultant structure (f); And
(h) forming a copper plating bump embedded in the insulating layer by etching the exposed copper foil in the step (g)
≪ / RTI >
KR1020150111343A 2015-08-07 2015-08-07 Method of manufacturing a fine pattern printed circuit board KR101682555B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020150111343A KR101682555B1 (en) 2015-08-07 2015-08-07 Method of manufacturing a fine pattern printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020150111343A KR101682555B1 (en) 2015-08-07 2015-08-07 Method of manufacturing a fine pattern printed circuit board

Publications (1)

Publication Number Publication Date
KR101682555B1 true KR101682555B1 (en) 2016-12-07

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Family Applications (1)

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KR1020150111343A KR101682555B1 (en) 2015-08-07 2015-08-07 Method of manufacturing a fine pattern printed circuit board

Country Status (1)

Country Link
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110024055A (en) * 2009-09-01 2011-03-09 일진머티리얼즈 주식회사 Embedded copper foil for fine pattern
KR20140110709A (en) * 2013-03-08 2014-09-17 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Package having substrate with embedded metal trace overlapped by landing pad
KR20150087691A (en) * 2014-01-22 2015-07-30 앰코 테크놀로지 코리아 주식회사 Embedded trace substrate and method manufacturing bump of the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110024055A (en) * 2009-09-01 2011-03-09 일진머티리얼즈 주식회사 Embedded copper foil for fine pattern
KR20140110709A (en) * 2013-03-08 2014-09-17 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Package having substrate with embedded metal trace overlapped by landing pad
KR20150087691A (en) * 2014-01-22 2015-07-30 앰코 테크놀로지 코리아 주식회사 Embedded trace substrate and method manufacturing bump of the same

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