KR20070113706A - Method of electrolytic gold plating for printed circuit board - Google Patents

Abstract

A method of electrolytic gold plating on a printed circuit board is provided to perform the electrolytic gold plating by applying a copper plating layer on the printed circuit board performing as a lead line. A method of electrolytic gold plating(15) on a printed circuit board includes the steps of: etching a copper layer from an epoxy resin substrate(10); applying an electroless copper plating(13) on an etched epoxy resin layer; forming a first mask layer for forming a circuit pattern; forming a circuit by performing electrolytic copper plating by using the first mask as a mask; forming a second mask layer defining an area to perform the electrolytic gold plating; performing the electrolytic gold plating by using the second mask as a mask; exfoliating the first and second mask layers; and removing an exposed electroless copper plating layer.

Description

Electrolytic gold plating method of a printed circuit board {METHOD OF ELECTROLYTIC GOLD PLATING FOR PRINTED CIRCUIT BOARD}

1A shows an epoxy substrate before forming a circuit in accordance with the present invention.

Figure 1b is a view showing a state after the electroless copper plating on the epoxy substrate subjected to the etching in accordance with the present invention.

1C is a view showing a state in which a mask circuit is manufactured using a dry film or photosensitive ink to form a circuit according to the present invention.

1D is a view showing a state after electrolytic copper plating to form a circuit according to the present invention.

Figure 1e is a view showing a process of masking the remaining portions leaving only the portion to be electroplated in accordance with the present invention.

Figure 1f is a view showing a state after the electroplated gold plating in accordance with the present invention.

Figure 1g is a view showing the state after peeling off the mask layer for electrolytic gold plating.

Figure 1h is a view showing the state after removing the electroless copper plating layer of the bottom.

<Explanation of symbols for the main parts of the drawings>

10: epoxy layer

11: Electroless Copper Plating Layer

12 photosensitive resist

13: electrolytic copper plating layer

14: mask layer

15: electrolytic gold plated layer

The present invention relates to a method for manufacturing a printed circuit board, and more particularly, to a method for performing electrolytic gold plating without a lead wire. Electrolytic gold plating is commonly used to surface-treat printed circuit boards, and in order to perform electrolytic gold plating, a plating lead wire for electricity supply is required.

However, in recent years, as the circuit density of printed circuit boards increases, difficulty in designing lead wires for electroplating has increased. As a lead wire design method for electrolytic gold plating on a highly integrated circuit board, a method of cutting a plated lead wire by a router or dicing method or a chemical etching method after electrolytic gold plating has been introduced, but a part of the lead wire remains in the final product after cutting. This causes serious noise problems in the frequency of the RF domain.

Accordingly, a first object of the present invention is to provide a printed circuit board manufacturing method capable of performing electrolytic gold plating on a printed circuit board having a high circuit density without a lead wire.

A second object of the present invention is to provide a printed circuit board manufacturing method which solves the noise problem at the RF frequency experienced in the prior art while being applied to a printed circuit board having a high circuit density in addition to the first object.

In order to achieve the above object, the present invention, in the method of manufacturing a printed circuit board, the entire surface of the copper foil of the copper clad laminate laminated copper foil on the epoxy resin layer, and as a result, the epoxy resin layer or copper foil is completely peeled off copper foil Electroless copper plating is applied to the epoxy resin layer. Subsequently, a first mask layer is formed to form a circuit pattern, and electrolytic copper plating is performed using this as a mask to form a circuit.

Then, a second mask layer defining a portion to be subjected to electrolytic gold plating is formed, and electrolytic gold plating is performed using the second mask layer as a mask. Subsequently, both the first mask layer and the second mask layer are peeled off, and the exposed portion of the electroless copper plating layer is removed.

The electrolytic gold plating method according to the present invention is characterized in that the electroless copper plating is performed on the epoxy substrate, and the electrolytic gold plating is performed as a lead wire.

Hereinafter, a preferred embodiment of the electrolytic gold plating method according to the present invention with reference to the accompanying drawings, Figures 1a to 1h.

1A is a view showing an epoxy substrate before forming a circuit. That is, all copper foils of the existing copper clad laminated laminate (CCL) are etched and removed. That is, after etching all of the copper foil, the substrate leaves only the epoxy layer 10. At this time, as another embodiment of the present invention, instead of etching all of the copper foil may be slightly left to about 3㎛ or less.

Figure 1b is a view showing a state after the electroless copper plating on the epoxy substrate subjected to the etching in accordance with the present invention. Referring to FIG. 1B, an electroless copper plating layer 11 is shown on an epoxy substrate 10.

1C is a view showing a state in which a mask circuit is fabricated using a dry film or photosensitive ink to form a circuit according to the present invention. Referring to FIG. 1C, a dry film or photosensitive resist 12 is patterned on the electroless copper plating layer 11 as a mask layer.

Figure 1d is a view showing the state after the electrolytic copper plating to form a circuit according to the present invention. Referring to FIG. 1D, an electrolytic copper plating 13 is formed on an exposed portion where the mask layer 12 is not covered on the electroless copper plating layer 11.

Figure 1e is a view showing a process of masking the remaining portions leaving only the portion to be electroplated according to the present invention. Referring to FIG. 1E, the mask layer 14 is formed using a dry film or photosensitive ink. At this time, the portion covered with the mask layer 14 does not become gold plated during subsequent electrolytic gold plating.

Figure 1f is a view showing a state after the electroplated gold plating according to the present invention. Referring to FIG. 1F, an electrolytic gold plating layer 15 is formed, and in an actual circuit, since there is no lead wire, gold plating cannot be performed. do.

Figure 1g is a view showing a state after peeling off the mask layer for electrolytic gold plating. Referring to FIG. 1G, the electrolytic copper plating 14 and the electrolytic gold plating layer 15 are simultaneously exposed by removing the mask layer 14 made of the dry film or photosensitive ink layer. As a result, gold plating is formed in a part of the circuit, and a circuit is formed in the remaining part.

Figure 1h is a view showing the state after removing the electroless copper plating layer of the bottom. Referring to FIG. 1H, after the electrolytic gold plating 15 is completed, the electroless copper plating layer 11 used as the lead wire is removed through soft etching.

The foregoing has somewhat broadly improved the features and technical advantages of the present invention to better understand the claims that follow. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously evolved, substituted and changed without departing from the spirit or scope of the invention described in the claims.

As described above, the present invention allows the entire surface of the electroless copper plating layer to be applied to the substrate to serve as a lead wire, so that the subsequent electrolytic gold plating process can be easily and reliably performed.

Claims (1)

In a printed circuit board manufacturing method, (a) etching the entire copper foil of the copper clad laminate in which the copper foil is laminated on the epoxy resin layer; (b) applying the electroless copper plating to the epoxy resin layer in which the copper foil has been completely peeled off or partially etched as a result of the step (a); (c) forming a first mask layer to form a circuit pattern; (d) forming a circuit by electrolytic copper plating using the first mask layer as a mask; (e) forming a second mask layer defining a portion to be electroplated; (f) performing electrolytic gold plating using the second mask layer as a mask; (g) peeling off both the first mask layer and the second mask layer; And (h) removing the exposed portion of the electroless copper plating layer Printed circuit manufacturing method comprising a.

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