KR20100107936A - Manufacturing method of ultra-thin package board - Google Patents

Manufacturing method of ultra-thin package board Download PDF

Info

Publication number
KR20100107936A
KR20100107936A KR1020090026310A KR20090026310A KR20100107936A KR 20100107936 A KR20100107936 A KR 20100107936A KR 1020090026310 A KR1020090026310 A KR 1020090026310A KR 20090026310 A KR20090026310 A KR 20090026310A KR 20100107936 A KR20100107936 A KR 20100107936A
Authority
KR
South Korea
Prior art keywords
copper foil
carrier
manufacturing
package substrate
circuit
Prior art date
Application number
KR1020090026310A
Other languages
Korean (ko)
Inventor
고영주
이현준
Original Assignee
아페리오(주)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아페리오(주) filed Critical 아페리오(주)
Priority to KR1020090026310A priority Critical patent/KR20100107936A/en
Publication of KR20100107936A publication Critical patent/KR20100107936A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE: A thin package substrate manufacturing method is provided to reduce the thickness of a package substrate by manufacturing a bonding pad and a ball pad into a single layer structure. CONSTITUTION: A release film, an insulating layer(220), and a copper foil(230) are formed on a carrier. A copper foil circuit, which includes a bonding pad and a ball pad, is formed by selectively etching the copper foil. A chip(260) is mounted after spreading an adhesive(250) on the copper foil circuit. The carrier is separated from a structure. The ball pad surface of the copper foil circuit is exposed. A solder ball(280) is formed on the exposed ball pad surface.

Description

박형 패키지 기판 제조 방법{MANUFACTURING METHOD OF ULTRA-THIN PACKAGE BOARD}MANUFACTURING METHOD OF ULTRA-THIN PACKAGE BOARD

본 발명은 패키지 기판 제조 기술에 관한 것으로, 특히 본딩 패드와 볼 패드를 1층 구조로 제작함으로써 박형 패키지 기판을 제조하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package substrate manufacturing technology, and more particularly, to a technology for manufacturing a thin package substrate by manufacturing a bonding pad and a ball pad in a single layer structure.

도1은 종래기술에 따라 패키지 기판을 제조하는 전형적인 방법을 나타낸 도면이다. 종래기술은 일반적으로 동박 적층 수지층(CCL; copper cladded laminate)에 층간 접속을 위해 비아(via)를 형성하고 동도금을 수행하여 층간 접속을 수행한 후, 기판 상하 양면에 형성되어 있는 동박에 대해 선정된 회로에 따라 사진/현상/식각 등 이미지 공정을 진행하거나 또는 마스크 패턴 하에 도금을 진행하여 동박 회로를 형성한다.1 illustrates an exemplary method for manufacturing a package substrate in accordance with the prior art. The prior art generally forms vias for interlayer connection to a copper clad laminated laminate (CCL) and performs copper plating to select interlayer connections, and then selects copper foils formed on both sides of the substrate. According to the circuit, the image process such as photo / development / etching or plating is performed under a mask pattern to form a copper foil circuit.

이어서, 종래 기술은 솔더 마스크를 형성하고 솔더 볼 접합을 위한 금도금 또는 OSP(Organic Solderability Preservative) 처리를 한 후 패드에 솔더 볼을 접합하는 방법을 채용하고 있다.Subsequently, the prior art employs a method of forming a solder mask, performing gold plating or OSP (Organic Solderability Preservative) treatment for solder ball bonding, and then bonding solder balls to pads.

도1을 참조하면, 종래기술에 따라 제작된 패키지 기판이 도시되어 있는데, 앞서 설명한 바와 같이 에폭시 수지층 또는 섬유질의 절연층(100) 표면에 도포된 동박을 패턴 형성하여 본딩 패드(111)와, 인식 마크(114), 동박 회로 패턴(113), 볼 패드(110)를 형성한다. 패턴 형성한 동박들 위에는 금 도금층(115)을 형성하고 솔더 마스크(112)가 도시되어 있다.Referring to FIG. 1, a package substrate manufactured according to the prior art is illustrated. As described above, a bonding pad 111 is formed by patterning a copper foil coated on an epoxy resin layer or a fibrous insulating layer 100. The recognition mark 114, the copper foil circuit pattern 113, and the ball pad 110 are formed. The gold plating layer 115 is formed on the patterned copper foils and the solder mask 112 is illustrated.

그런데, 종래기술의 리드 프레임의 경우 솔더 조인트는 단위 면적당 I/O 수에 있어서 한계가 있으며, 리드가 동일 평면상에 있어야 하는 제약이 있다. 또한, 종래 패키지 PCB의 경우 와이어 본딩 면과 볼 패드 면이 2 층에 서로 달리 분포하고 있어서 기판의 두께를 박형으로 제작하는데 한계가 있다. However, in the case of the lead frame of the prior art, the solder joint has a limitation in the number of I / Os per unit area, and there is a restriction that the leads must be on the same plane. In addition, in the case of a conventional package PCB, the wire bonding surface and the ball pad surface are differently distributed in two layers, thereby limiting the thickness of the substrate.

따라서, 본 발명의 목적은 패키지 기판을 제조함에 있어서 본딩 패드와 볼 패드를 1층 구조로 하여 기판의 두께를 박형으로 만들 수 있는 패키지 기판 제조 기술을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a package substrate manufacturing technology capable of making the thickness of a substrate thin by using a bonding pad and a ball pad as a single layer structure in manufacturing a package substrate.

상기 목적을 달성하기 위하여, 본 발명은 FR-4와 같은 자재를 캐리어(carrier)로 사용할 수 있도록 접착하고 공정 완료 후에 캐리어를 분리하여 제거함으로써 패키지 기판의 두께를 박형화할 수 있으며, 동박 회로와 수지층에 접착제(adhesive)를 인쇄하여 다이를 접착하고, 동박회로의 절연체로 사용한 레진을 솔더 볼 측면에서 솔더 레지스트로 활용하는 것을 특징으로 한다. 또한, 본 발명은 솔더 볼 접착 부분 수지를 레이저로 제거한다.In order to achieve the above object, the present invention can reduce the thickness of the package substrate by bonding a material such as FR-4 to be used as a carrier (carrier) and separating the carrier after completion of the process, the copper foil circuit and the number The die is bonded by printing an adhesive on the ground layer, and the resin used as an insulator of the copper foil circuit is utilized as a solder resist on the solder ball side. Moreover, this invention removes a solder ball adhesive partial resin with a laser.

본 발명은 기존 퍼리페랄(peripheral) 방식의 솔더 조인트가 단위 면적당 I/O 수의 한계를 지닌다는 종래의 리드 프레임이 겪었던 기술상의 한계를 극복하고, 단층 동박에 볼 패드와 본딩 패드를 구성할 수 있는 장점이 있다. 또한 기존 패키지 기판과 비교할 경우, 종래 패키지 기판이 붙임 면과 볼 면이 2개 층으로 구성되어 있어 층간 절연층에 기인하여 박형화에 한계가 있는데 비해, 본 발명은 본딩 패드와 볼 패드를 같은 층에 형성하므로 박형화 할 수 있는 장점이 있다. The present invention overcomes the technical limitations experienced by the conventional lead frame that conventional peripheral solder joints have a limit of the number of I / Os per unit area. There is an advantage. In addition, compared with the conventional package substrate, the conventional package substrate is composed of two layers of the adhesive surface and the ball surface is limited due to the interlayer insulating layer, the present invention has a limitation of the bonding pad and the ball pad on the same layer There is an advantage that can be made thin.

본 발명은 패키지 기판을 제조하는 방법에 있어서, (a) 캐리어 표면에 이형필름, 절연층, 동박을 형성하고, 상기 동박을 선정된 회로에 따라 선택 식각하여 본딩 패드와 볼 패드를 포함한 동박 회로를 형성하는 단계; (b) 상기 패턴 형성된 동박 회로 위에 칩이 실장될 부위에 접합제를 도포하고 칩을 실장하고 에폭시 몰딩 처리하는 단계; (c) 상기 이형필름을 벗겨내어 상기 캐리어를 분리 제거하는 단계; (d) 상기 캐리어가 박리 제거되어 노출된 상기 절연층에 대해 소정의 회로 패턴에 따라 필요 부위를 선택 식각하여 상기 동박 회로의 볼 패드 표면을 노출하는 단계; 및 (e) 상기 노출된 볼 패드 표면에 솔더 볼을 형성하는 단계를 포함하는 패키지 기판 제조 방법을 제공한다.The present invention provides a method for manufacturing a package substrate, comprising: (a) forming a release film, an insulating layer, and a copper foil on a carrier surface, and selectively etching the copper foil according to a selected circuit to form a copper foil circuit including a bonding pad and a ball pad. Forming; (b) applying a binder to a portion where the chip is to be mounted on the patterned copper foil circuit, mounting the chip, and performing epoxy molding; (c) peeling off the release film to separate and remove the carrier; (d) exposing the ball pad surface of the copper foil circuit by selectively etching a required portion according to a predetermined circuit pattern with respect to the insulating layer in which the carrier is peeled off and exposed; And (e) forming solder balls on the exposed ball pad surface.

이하에서는, 첨부 도면 도2a 내지 도2f를 참조하여 본 발명에 따른 패키지 기판 제조 방법의 양호한 실시예를 상세히 설명한다. 도2a를 참조하면, 캐리어(200) 위에 이형필름(release film; 210)을 정렬하고 절연층(220)과 동박(230)을 상부에 형성한다. DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of a method for manufacturing a package substrate according to the present invention will be described in detail with reference to the accompanying drawings, FIGS. 2A to 2F. Referring to FIG. 2A, a release film 210 is aligned on a carrier 200, and an insulating layer 220 and a copper foil 230 are formed thereon.

본 발명의 양호한 실시예로서, 절연층(220)과 동박(230)은 레진 도포된 동박(RCC; 240)이 사용될 수 있다. 본 발명의 양호한 실시예에 따라, 캐리어(200)는 두께 0.1 ~ 0.3 mm 정도의 FR-4 프리프레그가 사용될 수 있다. 여기서, FR-4 프리프레그는 성형 공정에 의하여 소정의 강도를 갖는 고형의 캐리어가 되고, 이후 PCB 공정과 패키지 공정에서 핸들링을 용이하게 하는 캐리어 역할을 한다.As a preferred embodiment of the present invention, a resin coated copper foil (RCC) 240 may be used for the insulating layer 220 and the copper foil 230. According to a preferred embodiment of the present invention, the carrier 200 may use a FR-4 prepreg having a thickness of about 0.1 to 0.3 mm. Here, the FR-4 prepreg becomes a solid carrier having a predetermined strength by a molding process, and then serves as a carrier for easy handling in the PCB process and the package process.

여기서, 이형필름(210)은 캐리어(200)와 상부의 RCC(240)를 접합하도록 하는 필름으로서, 후속하는 공정을 완료한 후에 캐리어(200)를 구조물로부터 분리하도록 벗겨질 수 있다. 본 발명의 양호한 실시예로서, 절연층(220)은 레진 계열의 수지가 사용될 수 있으며, 그 두께는 10 ~ 30 마이크로미터가 바람직하다. 또한, 동박(230)의 두께는 12 마이크로미터 내외일 수 있다.Here, the release film 210 is a film for bonding the carrier 200 and the upper RCC 240, may be peeled off to separate the carrier 200 from the structure after completing the following process. As a preferred embodiment of the present invention, a resin-based resin may be used as the insulating layer 220, and the thickness thereof is preferably 10 to 30 micrometers. In addition, the thickness of the copper foil 230 may be about 12 micrometers.

도2b를 참조하면, 캐리어 위에 형성된 동박(230)을 주어진 회로 패턴에 따라 사진/노광/현상/식각 공장을 진행하여 동박 회로를 형성한다. 이때에, 후속할 다이 본딩을 위한 본딩 패드가 형성된다. 동박 회로를 형성하는 방법의 기존의 식각 방법을 적용할 수 있다. 물론, 와이어 본딩 패드 또는 다이의 범프와 조인트가 필요한 부분은 별도의 금도금 등의 처리를 할 수 있다. 본 발명의 양호한 실시예로서, 접합제와 회로와의 접합력을 증대하기 위하여 회로부분에 방청처리를 할 수 있다.Referring to FIG. 2B, the copper foil 230 formed on the carrier is subjected to a photo / exposure / developing / etching plant according to a given circuit pattern to form a copper foil circuit. At this time, bonding pads for subsequent die bonding are formed. The conventional etching method of the method of forming a copper foil circuit can be applied. Of course, the portion of the wire bonding pad or die that needs bumps and joints may be treated with a separate gold plating. As a preferred embodiment of the present invention, in order to increase the bonding strength between the bonding agent and the circuit, the circuit portion may be subjected to rust prevention treatment.

이어서, 도2c를 참조하면, 칩을 실장할 부위에 접합제(adhesive; 250)을 도포하고 다이 또는 칩(260)을 실장한다. 즉, 동박 패턴이 있는 부분에 기존의 다이 어태치에서 사용하는 접합제 잉크를 인쇄하고 다이를 올려 놓은 후 경화시키고, 와 이어 본딩 등 기판과 다리를 서로 전기적으로 접속할 수 있다. 이때에, 접합제는 실크 스크린 방식으로 선택 부위에만 도포할 수 있다. 그리고나면, 칩(260)과 동박 회로(230)를 서로 전기적으로 접속하기 위하여 본딩이 실시된다(도시하지 않음). 그리고나면, 기판 위에 절연체(265), 특히 바람직한 실시예로서 에폭시 몰드 컴파운드(EMC)를 도포하여 밀봉한다. Next, referring to FIG. 2C, an adhesive 250 is applied to a portion where the chip is to be mounted, and the die or the chip 260 is mounted. That is, the adhesive ink used in the existing die attach is printed on the portion having the copper foil pattern, the die is placed and cured, and the substrate and the legs such as wire bonding can be electrically connected to each other. At this time, the binder may be applied only to the selected site by the silk screen method. Then, bonding is performed (not shown) to electrically connect the chip 260 and the copper foil circuit 230 to each other. The insulator 265 is then applied and sealed over the substrate, in particular preferred embodiment, an epoxy mold compound (EMC).

이와 같이 하여 에폭시 몰딩이 완료되면 구조물을 지탱하고 있던 캐리어(200)를 구조물로부터 분리한다. 이때에, 이형필름(210)에 약간의 물리적 힘을 인가하면 이형필름이 벗겨지면서 캐리어(200)가 분리된다. 도2d는 이형필름(210)을 벗겨내어 캐리어(200)를 분리한 후의 기판 구조물의 모습을 보여주고 있다.In this manner, when the epoxy molding is completed, the carrier 200 supporting the structure is separated from the structure. At this time, when a slight physical force is applied to the release film 210, the release film is peeled off and the carrier 200 is separated. Figure 2d shows the appearance of the substrate structure after peeling off the release film 210 to separate the carrier 200.

도2e를 참조하면, 구조물의 하부의 절연층(220)은 그 두께가 얇으므로, 예를 들어 RCC 레진인 경우 10 ~ 30 마이크로미터 정도이므로, CO2 레이저 가공에 의해 식각하여 용이하게 홀(270)을 형성할 수 있다. 홀 가공을 통해 볼 패드가 노출되면, 표면 클리닝을 진행하고 도2f에서와 같이 솔더 볼(280)을 형성한다. Referring to FIG. 2E, since the insulating layer 220 at the bottom of the structure is thin, for example, about 10 to 30 micrometers in the case of RCC resin, CO 2 The hole 270 may be easily formed by etching by laser processing. When the ball pads are exposed through hole processing, surface cleaning is performed and solder balls 280 are formed as shown in FIG. 2F.

전술한 내용은 후술할 발명의 특허 청구 범위를 더욱 잘 이해할 수 있도록 본 발명의 특징과 기술적 장점을 다소 폭넓게 개선하였다. 본 발명의 특허 청구 범위를 구성하는 부가적인 특징과 장점들이 이하에서 상술될 것이다. 개시된 본 발명의 개념과 특정 실시예는 본 발명과 유사 목적을 수행하기 위한 다른 구조의 설계나 수정의 기본으로서 즉시 사용될 수 있음이 당해 기술 분야의 숙련된 사람들에 의해 인식되어야 한다. The foregoing has somewhat broadly improved the features and technical advantages of the present invention to better understand the claims that follow. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

또한, 본 발명에서 개시된 발명 개념과 실시예가 본 발명의 동일 목적을 수행하기 위하여 다른 구조로 수정하거나 설계하기 위한 기초로서 당해 기술 분야의 숙련된 사람들에 의해 사용될 수 있을 것이다. 또한, 당해 기술 분야의 숙련된 사람에 의한 그와 같은 수정 또는 변경된 등가 구조는 특허 청구 범위에서 기술한 발명의 사상이나 범위를 벗어나지 않는 한도 내에서 다양한 진화, 치환 및 변경이 가능하다. In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously evolved, substituted and changed without departing from the spirit or scope of the invention described in the claims.

이상과 같이, 본 발명에 따른 패키지 기판 제조 기술은 이층 면에 볼 패드와 본딩 패드를 동시에 제작할 수 있으므로 패키지 기판의 두께를 수십 마이크로미터 수준으로 초박형으로 할 수 있으며, 기존의 리드 프레임이 같는 1층 구조의 패키지 기판을 실현할 수 있게 된다. 본 발명은 종래기술과 달리 2층 양면 기판 형성을 위한 동도금 공정이 필요 없으며 솔더 마스크 공정을 생략할 수 있는 장점이 있다. As described above, the package substrate manufacturing technology according to the present invention can produce a ball pad and a bonding pad at the same time on the two-layer surface, so that the thickness of the package substrate can be made ultra-thin at the level of several tens of micrometers, and the first layer having the same lead frame The package substrate of the structure can be realized. Unlike the prior art, the present invention does not require a copper plating process for forming a two-layer double-sided substrate and has the advantage of eliminating the solder mask process.

도1은 종래기술에 따라 패키지 기판을 제조하는 방법을 나타낸 도면.1 shows a method of manufacturing a package substrate according to the prior art.

도2a 내지 도2f는 본 발명에 따른 패키지 기판 제조 방법을 나타낸 도면.2a to 2f illustrate a method for manufacturing a package substrate according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

200 : 캐리어200 carrier

210 : 이형필름210: release film

220 : 절연층220: insulation layer

230 : 동박230: copper foil

240 : 레진 도포된 동박(RCC)240: resin coated copper foil (RCC)

250 : 접합제250: binder

260 : 칩260 chip

265 : 절연체265: insulator

270 : 홀270: hall

280 : 솔더 볼280: Solder Balls

Claims (1)

패키지 기판을 제조하는 방법에 있어서,In the method of manufacturing a package substrate, (a) 캐리어 표면에 이형필름, 절연층, 동박을 형성하고, 상기 동박을 선정된 회로에 따라 선택 식각하여 본딩 패드와 볼 패드를 포함한 동박 회로를 형성하는 단계;(a) forming a release film, an insulating layer, and a copper foil on a carrier surface, and selectively etching the copper foil according to a selected circuit to form a copper foil circuit including a bonding pad and a ball pad; (b) 상기 패턴 형성된 동박 회로 위에 칩이 실장될 부위에 접합제를 도포하고 칩을 실장하고 에폭시 몰딩 처리하는 단계;(b) applying a binder to a portion where the chip is to be mounted on the patterned copper foil circuit, mounting the chip, and performing epoxy molding; (c) 상기 이형필름을 벗겨내어 상기 캐리어를 분리 제거하는 단계(c) peeling off the release film to separate and remove the carrier; (d) 상기 캐리어가 박리 제거되어 노출된 상기 절연층에 대해 소정의 회로 패턴에 따라 필요 부위를 선택 식각하여 상기 동박 회로의 볼 패드 표면을 노출하는 단계; 및(d) exposing the ball pad surface of the copper foil circuit by selectively etching a required portion according to a predetermined circuit pattern with respect to the insulating layer in which the carrier is peeled off and exposed; And (e) 상기 노출된 볼 패드 표면에 솔더 볼을 형성하는 단계(e) forming solder balls on the exposed ball pad surface 를 포함하는 패키지 기판 제조 방법.Package substrate manufacturing method comprising a.
KR1020090026310A 2009-03-27 2009-03-27 Manufacturing method of ultra-thin package board KR20100107936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090026310A KR20100107936A (en) 2009-03-27 2009-03-27 Manufacturing method of ultra-thin package board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090026310A KR20100107936A (en) 2009-03-27 2009-03-27 Manufacturing method of ultra-thin package board

Publications (1)

Publication Number Publication Date
KR20100107936A true KR20100107936A (en) 2010-10-06

Family

ID=43129582

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090026310A KR20100107936A (en) 2009-03-27 2009-03-27 Manufacturing method of ultra-thin package board

Country Status (1)

Country Link
KR (1) KR20100107936A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101441466B1 (en) * 2012-12-06 2014-11-03 대덕전자 주식회사 Ultra-thin package board and manufacturing method thereof
KR101698278B1 (en) * 2015-10-08 2017-01-19 앰코 테크놀로지 코리아 주식회사 Semiconductor package and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101441466B1 (en) * 2012-12-06 2014-11-03 대덕전자 주식회사 Ultra-thin package board and manufacturing method thereof
KR101698278B1 (en) * 2015-10-08 2017-01-19 앰코 테크놀로지 코리아 주식회사 Semiconductor package and manufacturing method thereof

Similar Documents

Publication Publication Date Title
JP5410660B2 (en) WIRING BOARD AND ITS MANUFACTURING METHOD, ELECTRONIC COMPONENT DEVICE AND ITS MANUFACTURING METHOD
JP5997260B2 (en) Printed circuit board and manufacturing method thereof
US7768116B2 (en) Semiconductor package substrate having different thicknesses between wire bonding pad and ball pad and method for fabricating the same
KR20150092881A (en) Pcb, package substrate and a manufacturing method thereof
KR20160002069A (en) Pcb, package substrate and a manufacturing method thereof
JP7074409B2 (en) Built-in element type printed circuit board
KR101140982B1 (en) Single layer printed circuit board and manufacturing method thereof
JPWO2007126090A1 (en) CIRCUIT BOARD, ELECTRONIC DEVICE DEVICE, AND CIRCUIT BOARD MANUFACTURING METHOD
JP2007281301A (en) Substrate for electronic device and its manufacturing method, as well as electronic device and its manufacturing method
JP2012134396A (en) Wiring board and semiconductor package
JP2016063130A (en) Printed wiring board and semiconductor package
JP4497548B2 (en) Wiring board
JP5302920B2 (en) Manufacturing method of multilayer wiring board
KR20120115034A (en) The printed circuit board and the method for manufacturing the same
KR20150065029A (en) Printed circuit board, manufacturing method thereof and semiconductor package
TWI530240B (en) Printed circuit board and method for manufacturing same
JP5432354B2 (en) Temporary board for manufacturing wiring board and method for manufacturing the same
KR20100107936A (en) Manufacturing method of ultra-thin package board
KR101222828B1 (en) Method of manufacturing coreless substrate
KR101044154B1 (en) A printed circuit board comprising a outer circuit layer burried under a insulating layer and a method of manufacturing the same
JP2011222962A (en) Print circuit board and method of manufacturing the same
KR101158213B1 (en) Printed Circuit Board with Electronic Components Embedded therein and Method for Fabricating the same
KR101305570B1 (en) Fabricating method of printed circuit board
KR101212526B1 (en) Boc package, pcb and method for fabricating the same
KR101194448B1 (en) Method for manufacturing printed circuit board

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application