KR20090101404A - Method of manufacturing coreless printed circuit board - Google Patents

Abstract

PURPOSE: A method for manufacturing a coreless PCB is provided to reduce the process time and cost through a plasma process by reducing the thickness of a solder resist. CONSTITUTION: A method for manufacturing a coreless PCB comprises the following steps of: forming a film type solder resist(110) on upper/lower surfaces of a carrier(10) and then forming a copper foil(111) on the result; selectively etching a dry film layer(120) on which a pattern is formed according to a predetermined circuit pattern to selectively expose the solder resist layer; and then forming a gold/nickel plating layer on the exposed carrier.

Description

Coreless printed circuit board manufacturing method {METHOD OF MANUFACTURING CORELESS PRINTED CIRCUIT BOARD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board (PCB) manufacturing technology, and more particularly to a coreless PCB manufacturing method. More specifically, the present invention relates to a printed circuit board manufacturing to which a flip chip method is applied, and a technique for improving the flatness of a coreless package substrate.

1A to 1Q are diagrams schematically showing a process sequence for manufacturing a coreless substrate according to the prior art. Referring to FIG. 1A, first, a carrier 10 having copper foils 10b and 10c coated on both surfaces thereof is prepared with the insulating layer 10a as the center. At this time, the copper foils 10b and 10c of both sides may be peeled off from the insulating layer 10a.

Subsequently, referring to FIG. 1B, an insulating layer 20 such as a prepreg (PREPREG) is laminated on both sides of the carrier 10, and the prepreg insulating layer 20 is selectively processed to form a pad, thereby opening the opening 30. ) Is formed (Fig. 1C). Next, referring to FIG. 1D, Au / Ni plating is performed on the exposed and exposed copper foil surface to form a gold plating layer 35 and a nickel layer 36.

Then, chemical copper 40 is applied on both sides of the substrate (FIG. 1E), dry film (D / F) is adhered on the chemical copper 40, and a photo / developing / etching process is performed on the selected circuit pattern. Accordingly, the dry film pattern 42 is formed. Subsequently, copper plating is performed as shown in Fig. 1G to form a copper plating layer 44 on the substrate surface.

When the dry film 42 is etched away and then flash etched, as shown in FIG. 1H, the exposed surface of the chemical copper 40 is etched to show that the copper plating layer 44 is formed only on the chemical copper 40. Will be carried. Subsequently, referring to FIG. 1I, the insulating layer 49 and the copper foil 50 are laminated to perform a hot press lamination process.

Subsequently, the laser drilling process is performed to form the opening 52 in accordance with the selected circuit pattern, and chemical copper 53 is performed to form copper foil on the substrate surface (Fig. 1J). Referring again to FIG. 1K, the dry film 55 is patterned by closely attaching the dry film to both surfaces of the substrate and performing a photo / developing / etching process according to a predetermined circuit pattern. Then, copper plating is performed on the selectively removed dry film 55 pattern to form a copper plating layer 56.

Again, the dry film 55 is etched off and subjected to flash etching so that copper plating 56 is formed on the flash etched chemical copper 53, as shown in FIG. Subsequently, referring to FIG. 1M, a first solder resist (PSR) 60 is first applied according to an selectively selected circuit pattern, and nickel 61 and gold 62 are coated on the exposed copper foil not covered with the solder resist. Ni / Au is applied to apply (Fig. 1N).

Subsequently, the substrate is individually cut by using a router to peel off the substrate so that the substrate is separated into two upper and lower portions based on the intermediate insulating layer 10a of the carrier 10 as shown in FIG. That is, referring to FIG. 1O, the substrate is separated into two substrates.

Referring to FIG. 1P, the prior art performs an alkali etching to peel off the carrier copper foils 10b and 10c, and selectively applies a solder resist (PSR) 65 to the second circuit pattern on the surface of the substrate from which the carrier copper foil is peeled off. Apply with tea (Fig. 1q).

However, when the printed circuit board is formed according to the prior art shown in FIGS. 1A to 1Q, problems may occur during die bonding since the surface flatness is not good due to the step difference of the solder resist formed on the substrate surface.

In addition, in the prior art, a solder resist ink is applied to apply a solder resist, and a semi cure procedure, exposure, development, and post cure procedure must be performed. This is a big disadvantage. Moreover, the prior art requires that the solder resist application process be performed twice (Figs. 1M and 1Q). As a result, there is a problem that coreless substrate manufacturing time and cost increase.

Accordingly, it is a first object of the present invention to provide a coreless printed circuit board manufacturing method having a solder resist having good flatness.

A second object of the present invention is to provide a method for manufacturing a coreless printed circuit board in which solder resist formation can be performed simply and at low cost, in addition to the first object.

In order to achieve the above object, the present invention is characterized by applying a film type solder resist of the exposure method, and to perform a plasma processing instead of expensive laser processing to form a pad.

In the present invention, since the thickness of the solder resist can be reduced, unlike the prior art, plasma processing can be performed instead of laser processing for pad formation, thereby saving processing time and consequently reducing processing costs. In addition, since the film type solder resist has better flatness than the epoxy type solder resist, defects can be minimized during die bonding. In addition, the present invention has the advantage that can be plated on the solder resist film because the laminate including the copper foil at the time of the first application of the coreless process.

1A to 1Q schematically show a process sequence for manufacturing a coreless substrate according to the prior art.

2A-2V illustrate a method of fabricating a coreless printed circuit board in accordance with a preferred embodiment of the present invention.

Figure 3 shows a copper foil surface after plasma etching and a cross section after performing Ni / Au plating according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

              10: carrier

          20, 49: insulation layer

      30, 52,141: opening

    35, 130, 174: gold plated layer

    36, 131, 173: nickel layer

     40, 53, 135: chemical copper

42, 55, 120, 136: dry film

             110: film type solder resist

The present invention provides a method for manufacturing a coreless printed circuit board which separates and removes a carrier from the laminated structure after fabricating a laminated structure of a conductive layer and an insulating layer on both surfaces of the carrier using a carrier as a core. a) forming a film type solder resist on the carrier upper and lower surfaces, and forming copper foil thereon; (b) selectively etching the copper foil layer of the film type solder resist using a dry film layer patterned on the surface according to a predetermined circuit pattern as a mask, thereby selectively exposing the solder resist layer, and forming the patterned dry film mask. Selectively exposing the carrier surface by etching the exposed solder resist layer, and forming a gold / nickel plating layer on the exposed carrier surface; (c) peeling off the patterned dry film and performing chemical copper plating on the entire surface of the substrate to form copper foil on the surface; (d) Dry film is patterned according to a predetermined circuit pattern on the copper foil on the surface of the substrate, and copper plating is performed using the patterned dry film as a mask to fill copper only on the chemical copper exposed to the mask to form a flat copper foil. Forming a pad by exposing the solder resist at a position where the dry film was selectively formed by peeling and removing the dry film and flash etching after forming a layer; And (e) cutting the substrate with a router to separate the carrier from the substrate by peeling off the carrier, separating the carrier into two upper and lower substrates, and performing an alkali etching to peel off and remove the carrier copper foil from the two substrates. Provided is a circuit board manufacturing method.

In a preferred embodiment of the present invention, subsequent to the step (d), further comprising the step of laminating an insulating layer and a copper foil on the surface of the substrate and repeating the etching and plating process according to a predetermined circuit pattern to form a laminated structure. It provides a printed circuit board manufacturing method comprising the. The forming of the laminate structure of the present invention may include: (da) laminating an insulating layer and a copper foil on the substrate surface, and selectively etching opening the insulating layer and the copper foil according to a predetermined circuit pattern to form a copper foil layer under the solder resist. Allowing the surface to be exposed and performing chemical copper so that the surface copper foil and the inner layer copper foil layer are connected to each other; (db) A flat copper foil is formed by patterning a dry film on a copper foil on the surface of the substrate according to a predetermined circuit pattern and copper plating using the patterned dry film as a mask to fill copper only on the chemical copper exposed to the mask. Etching away the chemical copper at the position where the dry film was selectively formed by peeling and removing the dry film and flash etching after forming a layer; And (d-c) forming a pad by selectively forming a solder resist on the substrate surface and forming a nickel / gold plating layer on the exposed copper foil surface.

Hereinafter, with reference to the accompanying drawings Figures 2 and 3 will be described in detail a preferred embodiment of the present invention.

Referring to FIG. 2A, first, the copper foils 10b and 10c start with the carrier 10 coated on both surfaces of the insulating layer 10a. Referring to FIG. 2B, a film type solder resist (SR) 110 and a copper foil 111 are laminated on the entire surface of the carrier 10 both surfaces. That is, the soldering resist 110 and the copper foil 111 are coat | covered and formed on the surface of carrier copper foil 10b, 10c. Here, the copper foil 111 formed on the film-type soldering resist 110 may be formed by laminating or plating a copper foil foil.

Subsequently, the dry film (D / F) 120 is brought into close contact with the surface and the exposure / developing / etching process is performed according to the selected circuit pattern to form the dry film pattern 120. Referring to FIG. 2D, the patterned dry film pattern 120 is exposed and plasma etching is performed on the portion, thereby selectively etching the exposed copper foil 111 and the solder resist layer 110 below. At this time, in the case of the present invention, since the thickness of the solder resist 110 layer is thin, a cheap plasma etching process may be performed instead of laser drilling. Of course, laser processing may be performed instead of plasma etching.

Next, referring to FIG. 2E, the Au layer 130 and the Ni layer 131 are formed by performing gold plating and nickel plating. Referring to FIG. 2F, the dry film pattern 120 used to selectively plate the Ni / Au layer on the pad copper foil surface is peeled off. Referring to Figure 2g, the chemical copper 135 is plated and applied to the entire surface of the substrate.

Referring to FIG. 2H, the dry film (D / F) 136 is brought into close contact with the entire surface of the substrate, and the dry film is patterned by photographing / developing / etching the dry film according to a predetermined circuit pattern. Subsequently, when copper plating is performed, the patterned dry film 136 is formed while the copper foil 137 is filled on the surface exposed without masking (see FIG. 2I).

Then, the dry film 136 used is peeled off (FIG. 2J), and flash etching is performed as shown in FIG. 2K to slightly etch away the surface copper foil. As a result, as shown in Fig. 2K, the chemical copper exposed by dry film peeling and the copper foil on the bottom thereof are removed due to flash etching to expose the solder resist.

Subsequently, the resin-based insulating layer 138 and the copper foil 140 are laminated and laminated (FIG. 2L), and the laser drill process is performed to form the openings 141 (FIG. 2M). Then, the copper plating layer 149 is formed by performing chemical copper on the entire surface of the inner surface copper foil and the upper surface copper foil exposed by the opening 141 in the step of FIG. 2M.

Referring to FIG. 2O, the dry film is closely adhered to each other and the dry film is photographed / developed / etched according to the selected circuit to form the dry film pattern 150. Subsequently, the copper foil layer 160 is filled with copper on the exposed conductive layer to form copper foil layer 160 (FIG. 2P), and the dry film 150 is peeled off to form a cross section as illustrated in FIG. 2Q. Subsequently, when flash etching is carried out, the dry film is peeled off to remove the chemical copper of the exposed portion (see Fig. 2R).

Referring to FIG. 2S, the solder resist 170 and the copper foil 172 are laminated on the substrate on which the flash etching is performed. As a preferred embodiment of the present invention, the solder resist 170 may use PSR or film type SR.

Subsequently, Ni / Au plating is performed to form the nickel layer 173 and the gold plating layer 174. Then, the carrier is finally peeled off from the substrate by separating the substrate using a router (Fig. 2u). Then, the copper foil that constituted the carrier is peeled off by alkali etching (Fig. 2V).

3 is a view showing a copper foil surface after performing plasma etching and a cross section after performing Ni / Au plating according to a preferred embodiment of the present invention. Referring to FIG. 3, it can be seen that the surface roughness after performing plasma etching on the openings to form the pads is relatively uniform.

The foregoing has somewhat broadly improved the features and technical advantages of the present invention to better understand the claims that follow. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously evolved, substituted and changed without departing from the spirit or scope of the invention described in the claims.

The present invention solves the problem encountered in bonding due to the height of the surface during die bonding since the film type solder resist is used instead of the ink type solder resist having poor flatness on the surface. In addition, the present invention can omit the process of ink application → semi-cure → exposure → development → post cure which is essential when applying an ink type solder resist, thereby reducing process time and cost.

Claims (7)

In the method of manufacturing a coreless printed circuit board for manufacturing a laminated structure of a conductive layer and an insulating layer on both surfaces of the carrier after the carrier as a core, the carrier is separated and removed from the laminated structure, (a) forming a film type solder resist on the upper and lower surfaces of the carrier and forming a copper foil thereon; (b) selectively etching the copper foil layer of the film type solder resist using a dry film layer patterned on the surface according to a predetermined circuit pattern as a mask, thereby selectively exposing the solder resist layer, and forming the patterned dry film mask. Selectively exposing the carrier surface by etching the exposed solder resist layer, and forming a gold / nickel plating layer on the exposed carrier surface; (c) peeling off the patterned dry film and performing chemical copper plating on the entire surface of the substrate to form copper foil on the surface; (d) Dry film is patterned according to a predetermined circuit pattern on the copper foil on the surface of the substrate, and copper plating is performed using the patterned dry film as a mask to fill copper only on the chemical copper exposed to the mask to form a flat copper foil. Forming a pad by exposing the solder resist at a position where the dry film was selectively formed by peeling and removing the dry film and flash etching after forming a layer; And (e) cutting the substrate with a router to separate the carrier from the substrate by peeling off and separating the carrier into two substrates, and performing alkali etching to peel and remove the carrier copper foil from the two substrates. Printed circuit board manufacturing method comprising a. The method of claim 1, wherein the copper foil formed on the film type solder resist of step (a) is formed by performing copper plating on the solder resist or by laminating copper foil. The method of claim 1, subsequent to step (d). Laminating an insulating layer and copper foil on the surface of the substrate, and repeating etching and plating processes according to a predetermined circuit pattern to form a laminated structure; Printed circuit board manufacturing method further comprising. The method of claim 3, wherein forming the laminate structure (d) laminating an insulating layer and copper foil on the substrate surface, selectively etching opening the insulating layer and copper foil according to a predetermined circuit pattern to expose the surface of the copper foil layer under the solder resist, and performing chemical copper Allowing the surface copper foil and the inner layer copper foil layer to be connected to each other; (db) A flat copper foil is formed by patterning a dry film on a copper foil on the surface of the substrate according to a predetermined circuit pattern and copper plating using the patterned dry film as a mask to fill copper only on the chemical copper exposed to the mask. Etching away the chemical copper at the position where the dry film was selectively formed by peeling and removing the dry film and flash etching after forming a layer; And (d-c) forming a pad by selectively forming a solder resist on the substrate surface and forming a nickel / gold plating layer on the exposed copper foil surface; Printed circuit board manufacturing method comprising a. The method of manufacturing a printed circuit board according to any one of claims 1 to 4, wherein the carrier has an insulating layer in the center and a copper foil / insulating layer / copper structure in which copper foil is coated on both surfaces of the insulating layer. The method of claim 4, wherein the step of selectively forming the solder resist of the step (dc) comprises laminating a film type solder resist and peeling copper foil or selectively applying PSR. . A package substrate manufactured according to the printed circuit board manufacturing method according to any one of claims 1 to 4.