KR101548664B1 - 집적 회로의 mol 층들 내로 기판 관통 비아들을 통합하는 반도체 디바이스 - Google Patents

집적 회로의 mol 층들 내로 기판 관통 비아들을 통합하는 반도체 디바이스 Download PDF

Info

Publication number
KR101548664B1
KR101548664B1 KR1020147022299A KR20147022299A KR101548664B1 KR 101548664 B1 KR101548664 B1 KR 101548664B1 KR 1020147022299 A KR1020147022299 A KR 1020147022299A KR 20147022299 A KR20147022299 A KR 20147022299A KR 101548664 B1 KR101548664 B1 KR 101548664B1
Authority
KR
South Korea
Prior art keywords
substrate
layer
isolation layer
semiconductor device
tsv
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020147022299A
Other languages
English (en)
Korean (ko)
Other versions
KR20140117521A (ko
Inventor
비드야 라마찬드라
시쿤 구
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20140117521A publication Critical patent/KR20140117521A/ko
Application granted granted Critical
Publication of KR101548664B1 publication Critical patent/KR101548664B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0265—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the sidewall insulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
KR1020147022299A 2012-01-13 2013-01-12 집적 회로의 mol 층들 내로 기판 관통 비아들을 통합하는 반도체 디바이스 Active KR101548664B1 (ko)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201261586463P 2012-01-13 2012-01-13
US61/586,463 2012-01-13
US201261671607P 2012-07-13 2012-07-13
US61/671,607 2012-07-13
US13/724,038 US8975729B2 (en) 2012-01-13 2012-12-21 Integrating through substrate vias into middle-of-line layers of integrated circuits
US13/724,038 2012-12-21
PCT/US2013/021342 WO2013106796A1 (en) 2012-01-13 2013-01-12 Integrating through substrate vias into middle-of-line layers of integrated circuits

Publications (2)

Publication Number Publication Date
KR20140117521A KR20140117521A (ko) 2014-10-07
KR101548664B1 true KR101548664B1 (ko) 2015-09-01

Family

ID=48779411

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020147022299A Active KR101548664B1 (ko) 2012-01-13 2013-01-12 집적 회로의 mol 층들 내로 기판 관통 비아들을 통합하는 반도체 디바이스

Country Status (7)

Country Link
US (1) US8975729B2 (https=)
EP (2) EP2803081B1 (https=)
JP (1) JP6012763B2 (https=)
KR (1) KR101548664B1 (https=)
CN (1) CN104067383B (https=)
ES (1) ES2829898T3 (https=)
WO (1) WO2013106796A1 (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9245790B2 (en) * 2013-01-23 2016-01-26 GlobalFoundries, Inc. Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via
CN104637861A (zh) * 2013-11-11 2015-05-20 上海华虹宏力半导体制造有限公司 硅通孔工艺方法
US9620454B2 (en) * 2014-09-12 2017-04-11 Qualcomm Incorporated Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods
US20160079167A1 (en) * 2014-09-12 2016-03-17 Qualcomm Incorporated Tie-off structures for middle-of-line (mol) manufactured integrated circuits, and related methods
US9653399B2 (en) 2015-02-13 2017-05-16 Qualcomm Incorporated Middle-of-line integration methods and semiconductor devices
KR102411064B1 (ko) * 2015-03-10 2022-06-21 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그의 제조방법
US10748906B2 (en) 2015-05-13 2020-08-18 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
KR102366804B1 (ko) 2015-05-13 2022-02-25 삼성전자주식회사 반도체 소자의 제조 방법
US9728501B2 (en) * 2015-12-21 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming trenches
US9761509B2 (en) * 2015-12-29 2017-09-12 United Microelectronics Corp. Semiconductor device with throgh-substrate via and method for fabrication the semiconductor device
KR102495587B1 (ko) 2016-01-12 2023-02-03 삼성전자주식회사 관통 비아 구조체를 갖는 반도체 소자
US10199315B2 (en) 2016-08-29 2019-02-05 Globalfoundries Inc. Post zero via layer keep out zone over through silicon via reducing BEOL pumping effects
US10049981B2 (en) * 2016-09-08 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Through via structure, semiconductor device and manufacturing method thereof
US9768133B1 (en) * 2016-09-22 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
KR102406583B1 (ko) 2017-07-12 2022-06-09 삼성전자주식회사 반도체 장치
CN107958194B (zh) * 2017-08-17 2021-11-19 柳州梓博科技有限公司 光电传感装置及电子设备
US11987493B2 (en) 2018-10-31 2024-05-21 Hamamatsu Photonics K.K. Damascene interconnect structure, actuator device, and method of manufacturing damascene interconnect structure
EP3876266A4 (en) 2018-10-31 2022-08-17 Hamamatsu Photonics K.K. METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING DAMASZEN WIRING STRUCTURE, SEMICONDUCTOR SUBSTRATE AND DAMASZEN WIRING STRUCTURE
US11495559B2 (en) * 2020-04-27 2022-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits
US11355464B2 (en) * 2020-11-10 2022-06-07 Nanya Technology Corporation Semiconductor device structure with bottle-shaped through silicon via and method for forming the same
KR102856349B1 (ko) 2021-04-16 2025-09-04 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5545581A (en) 1994-12-06 1996-08-13 International Business Machines Corporation Plug strap process utilizing selective nitride and oxide etches
US7473630B2 (en) 2004-09-22 2009-01-06 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20090269905A1 (en) 2007-05-16 2009-10-29 Chen-Shien Chen Tapered Through-Silicon Via Structure

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0926726A1 (en) 1997-12-16 1999-06-30 STMicroelectronics S.r.l. Fabrication process and electronic device having front-back through contacts for bonding onto boards
JP4322508B2 (ja) 2003-01-15 2009-09-02 新光電気工業株式会社 半導体装置の製造方法
US7892972B2 (en) 2006-02-03 2011-02-22 Micron Technology, Inc. Methods for fabricating and filling conductive vias and conductive vias so formed
US7615480B2 (en) 2007-06-20 2009-11-10 Lam Research Corporation Methods of post-contact back end of the line through-hole via integration
EP2306506B1 (en) 2009-10-01 2013-07-31 ams AG Method of producing a semiconductor device having a through-wafer interconnect
JP5537197B2 (ja) 2010-03-12 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8405222B2 (en) 2010-06-28 2013-03-26 Globalfoundries Singapore Pte. Ltd. Integrated circuit system with via and method of manufacture thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5545581A (en) 1994-12-06 1996-08-13 International Business Machines Corporation Plug strap process utilizing selective nitride and oxide etches
US7473630B2 (en) 2004-09-22 2009-01-06 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20090269905A1 (en) 2007-05-16 2009-10-29 Chen-Shien Chen Tapered Through-Silicon Via Structure
US7816227B2 (en) 2007-05-16 2010-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. Tapered through-silicon via structure

Also Published As

Publication number Publication date
EP2803081A1 (en) 2014-11-19
JP6012763B2 (ja) 2016-10-25
US20130181330A1 (en) 2013-07-18
EP2803081B1 (en) 2020-08-12
KR20140117521A (ko) 2014-10-07
ES2829898T3 (es) 2021-06-02
EP3731265B1 (en) 2023-03-08
EP3731265A1 (en) 2020-10-28
JP2015505171A (ja) 2015-02-16
CN104067383B (zh) 2017-04-12
US8975729B2 (en) 2015-03-10
CN104067383A (zh) 2014-09-24
WO2013106796A1 (en) 2013-07-18

Similar Documents

Publication Publication Date Title
KR101548664B1 (ko) 집적 회로의 mol 층들 내로 기판 관통 비아들을 통합하는 반도체 디바이스
KR101580941B1 (ko) 스트레인-완화된 tsv에 대한 구조 및 방법
KR101610323B1 (ko) 저-ｋ 배선 층을 관통하여 기판 관통 비아들을 패터닝하기 위한 저-ｋ 유전체 보호 스페이서를 형성하는 방법 및 상기 방법에 의해 형성된 스페이서를 포함하는 반도체 다이
KR101654794B1 (ko) 집적 회로들의 웨이퍼 후면 층들로부터 기판 관통 비아들의 통합
US9142490B2 (en) Integrated circuit device having through-silicon-via structure and method of manufacturing the integrated circuit device
US20100164062A1 (en) Method of manufacturing through-silicon-via and through-silicon-via structure
US9666660B2 (en) Semiconductor structures including metal insulator metal capacitor

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

A201 Request for examination
A302 Request for accelerated examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PA0302 Request for accelerated examination

St.27 status event code: A-1-2-D10-D17-exm-PA0302

St.27 status event code: A-1-2-D10-D16-exm-PA0302

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20180628

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20190624

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000