KR101313473B1 - 역 t 채널 트랜지스터를 포함하는 다수의 디바이스 타입및 그 방법 - Google Patents

역 t 채널 트랜지스터를 포함하는 다수의 디바이스 타입및 그 방법 Download PDF

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KR101313473B1
KR101313473B1 KR1020087009819A KR20087009819A KR101313473B1 KR 101313473 B1 KR101313473 B1 KR 101313473B1 KR 1020087009819 A KR1020087009819 A KR 1020087009819A KR 20087009819 A KR20087009819 A KR 20087009819A KR 101313473 B1 KR101313473 B1 KR 101313473B1
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transistor
active region
pull
fin
transistors
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KR20080061375A (ko
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병 더블유. 민
제임스 디. 버넷
레오 매튜
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프리스케일 세미컨덕터, 인크.
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices
    • H10B10/12Static random access memory [SRAM] devices comprising a MOSFET load element
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/62Fin field-effect transistors [FinFET]

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  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020087009819A 2005-10-25 2006-10-10 역 t 채널 트랜지스터를 포함하는 다수의 디바이스 타입및 그 방법 Expired - Fee Related KR101313473B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/257,972 US7452768B2 (en) 2005-10-25 2005-10-25 Multiple device types including an inverted-T channel transistor and method therefor
US11/257,972 2005-10-25
PCT/US2006/039651 WO2007050288A2 (en) 2005-10-25 2006-10-10 Multiple device types including an inverted-t channel transistor and method therefor

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KR20080061375A KR20080061375A (ko) 2008-07-02
KR101313473B1 true KR101313473B1 (ko) 2013-10-01

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US (2) US7452768B2 (https=)
EP (1) EP1943671A4 (https=)
JP (1) JP5283507B2 (https=)
KR (1) KR101313473B1 (https=)
TW (1) TWI420603B (https=)
WO (1) WO2007050288A2 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070166971A1 (en) * 2006-01-17 2007-07-19 Atmel Corporation Manufacturing of silicon structures smaller than optical resolution limits
US20070166903A1 (en) * 2006-01-17 2007-07-19 Bohumil Lojek Semiconductor structures formed by stepperless manufacturing
KR101108711B1 (ko) * 2007-08-23 2012-01-30 삼성전자주식회사 액티브 패턴 구조물 및 그 형성 방법, 비휘발성 메모리소자 및 그 제조 방법.
US8158484B2 (en) * 2007-10-03 2012-04-17 Freescale Semiconductor, Inc. Method of forming an inverted T shaped channel structure for an inverted T channel field effect transistor device
US7820512B2 (en) * 2007-12-28 2010-10-26 Intel Corporation Spacer patterned augmentation of tri-gate transistor gate length
US9245805B2 (en) 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
US20110291188A1 (en) * 2010-05-25 2011-12-01 International Business Machines Corporation Strained finfet
US8987831B2 (en) 2012-01-12 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM cells and arrays
CN103367432B (zh) * 2012-03-31 2016-02-03 中芯国际集成电路制造(上海)有限公司 多栅极场效应晶体管及其制造方法
US9583398B2 (en) 2012-06-29 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having FinFETS with different fin profiles
JP2015053477A (ja) * 2013-08-05 2015-03-19 株式会社半導体エネルギー研究所 半導体装置および半導体装置の作製方法
US9373550B2 (en) 2014-04-23 2016-06-21 International Business Machines Corporation Selectively degrading current resistance of field effect transistor devices
US9391065B1 (en) 2015-06-29 2016-07-12 Globalfoundries Inc. Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode
US9893171B2 (en) 2016-06-03 2018-02-13 International Business Machines Corporation Fin field effect transistor fabrication and devices having inverted T-shaped gate
US10396075B2 (en) * 2017-05-01 2019-08-27 International Business Machines Corporation Very narrow aspect ratio trapping trench structure with smooth trench sidewalls
US10741566B2 (en) 2018-06-26 2020-08-11 Micron Technology, Inc. Integrated arrangements of pull-up transistors and pull-down transistors, and integrated static memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1174378A (ja) * 1997-06-24 1999-03-16 St Microelectron Inc Sramセル及びその製造方法
JP2003229575A (ja) * 2002-02-04 2003-08-15 Hitachi Ltd 集積半導体装置及びその製造方法
US20040099885A1 (en) * 2002-11-26 2004-05-27 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS SRAM cell configured using multiple-gate transistors
US20050023633A1 (en) * 2003-08-01 2005-02-03 Yee-Chia Yeo Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5738731A (en) * 1993-11-19 1998-04-14 Mega Chips Corporation Photovoltaic device
JP2571004B2 (ja) * 1993-12-22 1997-01-16 日本電気株式会社 薄膜トランジスタ
JPH0878537A (ja) * 1994-09-02 1996-03-22 Fujitsu Ltd スタティック型半導体記憶装置
KR0144165B1 (ko) 1995-05-12 1998-07-01 문정환 인버스 티(t)형 트랜지스터의 개선된 제조방법
US6034417A (en) 1998-05-08 2000-03-07 Micron Technology, Inc. Semiconductor structure having more usable substrate area and method for forming same
US20020036347A1 (en) 1998-10-28 2002-03-28 Theodore W Houston Local interconnect structures and methods
US6630712B2 (en) * 1999-08-11 2003-10-07 Advanced Micro Devices, Inc. Transistor with dynamic source/drain extensions
US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6475890B1 (en) 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
US20040059703A1 (en) 2002-09-23 2004-03-25 Jerry Chappell Cascading behavior of package generation/installation based on variable parameters
CN100351994C (zh) * 2002-12-19 2007-11-28 国际商业机器公司 使用反向FinFET薄膜晶体管的FinFET SRAM单元
JP2004214413A (ja) 2002-12-27 2004-07-29 Toshiba Corp 半導体装置
JP2005005465A (ja) 2003-06-11 2005-01-06 Toshiba Corp 半導体記憶装置及びその製造方法
US6867433B2 (en) * 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US6909147B2 (en) * 2003-05-05 2005-06-21 International Business Machines Corporation Multi-height FinFETS
US7192876B2 (en) * 2003-05-22 2007-03-20 Freescale Semiconductor, Inc. Transistor with independent gate structures
KR100496891B1 (ko) 2003-08-14 2005-06-23 삼성전자주식회사 핀 전계효과 트랜지스터를 위한 실리콘 핀 및 그 제조 방법
JP4904815B2 (ja) * 2003-10-09 2012-03-28 日本電気株式会社 半導体装置及びその製造方法
KR100935988B1 (ko) 2003-12-08 2010-01-08 인터내셔널 비지네스 머신즈 코포레이션 증가된 노드 커패시턴스를 갖는 반도체 메모리 장치
US7388258B2 (en) * 2003-12-10 2008-06-17 International Business Machines Corporation Sectional field effect devices
US7385247B2 (en) 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
US7060539B2 (en) 2004-03-01 2006-06-13 International Business Machines Corporation Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
WO2005094254A2 (en) 2004-03-17 2005-10-13 The Board Of Trustees Of The Leland Stanford Junior University Crystalline-type device and approach therefor
KR100549008B1 (ko) 2004-03-17 2006-02-02 삼성전자주식회사 등방성식각 기술을 사용하여 핀 전계효과 트랜지스터를제조하는 방법
KR100541054B1 (ko) 2004-03-23 2006-01-11 삼성전자주식회사 하드마스크 스페이서를 채택하여 3차원 모오스 전계효과트랜지스터를 제조하는 방법
US7098477B2 (en) 2004-04-23 2006-08-29 International Business Machines Corporation Structure and method of manufacturing a finFET device having stacked fins
US7122412B2 (en) 2004-04-30 2006-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a necked FINFET device
US6972461B1 (en) * 2004-06-30 2005-12-06 International Business Machines Corporation Channel MOSFET with strained silicon channel on strained SiGe
US7193279B2 (en) 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
US7589387B2 (en) 2005-10-05 2009-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. SONOS type two-bit FinFET flash memory cell
KR100653711B1 (ko) 2005-11-14 2006-12-05 삼성전자주식회사 쇼트키 배리어 핀 펫 소자 및 그 제조방법
US7564081B2 (en) 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1174378A (ja) * 1997-06-24 1999-03-16 St Microelectron Inc Sramセル及びその製造方法
JP2003229575A (ja) * 2002-02-04 2003-08-15 Hitachi Ltd 集積半導体装置及びその製造方法
US20040099885A1 (en) * 2002-11-26 2004-05-27 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS SRAM cell configured using multiple-gate transistors
US20050023633A1 (en) * 2003-08-01 2005-02-03 Yee-Chia Yeo Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors

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US7452768B2 (en) 2008-11-18
JP5283507B2 (ja) 2013-09-04
WO2007050288A2 (en) 2007-05-03
JP2009514214A (ja) 2009-04-02
US8643066B2 (en) 2014-02-04
EP1943671A4 (en) 2009-12-30
US20090039418A1 (en) 2009-02-12
KR20080061375A (ko) 2008-07-02
TW200733245A (en) 2007-09-01
US20070093054A1 (en) 2007-04-26
WO2007050288A3 (en) 2008-01-03
EP1943671A2 (en) 2008-07-16
TWI420603B (zh) 2013-12-21

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