KR101106832B1 - 스트레인 완화 범프 설계를 구비한 반도체 장치 - Google Patents

스트레인 완화 범프 설계를 구비한 반도체 장치 Download PDF

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Publication number
KR101106832B1
KR101106832B1 KR1020067002029A KR20067002029A KR101106832B1 KR 101106832 B1 KR101106832 B1 KR 101106832B1 KR 1020067002029 A KR1020067002029 A KR 1020067002029A KR 20067002029 A KR20067002029 A KR 20067002029A KR 101106832 B1 KR101106832 B1 KR 101106832B1
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South Korea
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delete delete
passivation layer
layer
redistribution conductor
redistribution
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KR20060054382A (ko
Inventor
제임스 전-호 왕
진-욱 장
알프레도 멘도자
라자시 룬톤
러셀 숨웨이
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프리스케일 세미컨덕터, 인크.
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9223—Bond pads being integral with underlying chip-level interconnections with redistribution layers [RDL]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H10W80/743—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having disposition changed during the connecting

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
KR1020067002029A 2003-07-31 2004-07-13 스트레인 완화 범프 설계를 구비한 반도체 장치 Expired - Fee Related KR101106832B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/631,102 US6790759B1 (en) 2003-07-31 2003-07-31 Semiconductor device with strain relieving bump design
US10/631,102 2003-07-31
PCT/US2004/022433 WO2005013319A2 (en) 2003-07-31 2004-07-13 Semiconductor device with strain relieving bump design

Publications (2)

Publication Number Publication Date
KR20060054382A KR20060054382A (ko) 2006-05-22
KR101106832B1 true KR101106832B1 (ko) 2012-01-19

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KR1020067002029A Expired - Fee Related KR101106832B1 (ko) 2003-07-31 2004-07-13 스트레인 완화 범프 설계를 구비한 반도체 장치

Country Status (6)

Country Link
US (2) US6790759B1 (enExample)
JP (1) JP2007502530A (enExample)
KR (1) KR101106832B1 (enExample)
CN (1) CN1926674A (enExample)
TW (1) TWI354362B (enExample)
WO (1) WO2005013319A2 (enExample)

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US7141883B2 (en) * 2002-10-15 2006-11-28 Silicon Laboratories Inc. Integrated circuit package configuration incorporating shielded circuit element structure
JP3678239B2 (ja) * 2003-06-30 2005-08-03 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
TWI260078B (en) * 2003-08-21 2006-08-11 Advanced Semiconductor Eng Chip structure
US7425759B1 (en) * 2003-11-20 2008-09-16 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped terminal and filler
DE102004035080A1 (de) * 2004-05-27 2005-12-29 Infineon Technologies Ag Anordnung zur Verringerung des elektrischen Übersprechens auf einem Chip
US7423346B2 (en) * 2004-09-09 2008-09-09 Megica Corporation Post passivation interconnection process and structures
US7394158B2 (en) * 2004-10-21 2008-07-01 Siliconix Technology C.V. Solderable top metal for SiC device
US7812441B2 (en) 2004-10-21 2010-10-12 Siliconix Technology C.V. Schottky diode with improved surge capability
US9419092B2 (en) * 2005-03-04 2016-08-16 Vishay-Siliconix Termination for SiC trench devices
US7834376B2 (en) 2005-03-04 2010-11-16 Siliconix Technology C. V. Power semiconductor switch
JP2006303452A (ja) * 2005-03-25 2006-11-02 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US20060264021A1 (en) * 2005-05-17 2006-11-23 Intel Corporation Offset solder bump method and apparatus
US7319043B2 (en) 2005-09-26 2008-01-15 Advanced Chip Engineering Technology Inc. Method and system of trace pull test
US7501924B2 (en) * 2005-09-30 2009-03-10 Silicon Laboratories Inc. Self-shielding inductor
US8368165B2 (en) * 2005-10-20 2013-02-05 Siliconix Technology C. V. Silicon carbide Schottky diode
DE102005055402A1 (de) * 2005-11-17 2007-05-31 Infineon Technologies Ag Verfahren zur Herstellung einer Umverdrahtung auf Substraten/einem Wafer
US7831434B2 (en) * 2006-01-20 2010-11-09 Microsoft Corporation Complex-transform channel coding with extended-band frequency coding
JP2007258438A (ja) * 2006-03-23 2007-10-04 Fujitsu Ltd 半導体装置及びその製造方法
US20070246805A1 (en) * 2006-04-25 2007-10-25 Ligang Zhang Multi-die inductor
US9627552B2 (en) 2006-07-31 2017-04-18 Vishay-Siliconix Molybdenum barrier metal for SiC Schottky diode and process of manufacture
JP4354469B2 (ja) * 2006-08-11 2009-10-28 シャープ株式会社 半導体装置および半導体装置の製造方法
US7524731B2 (en) * 2006-09-29 2009-04-28 Freescale Semiconductor, Inc. Process of forming an electronic device including an inductor
CN101190132B (zh) 2006-11-28 2010-12-08 深圳迈瑞生物医疗电子股份有限公司 超声成像的预处理方法与装置
US7834449B2 (en) * 2007-04-30 2010-11-16 Broadcom Corporation Highly reliable low cost structure for wafer-level ball grid array packaging
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US9345148B2 (en) * 2008-03-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
US7759137B2 (en) * 2008-03-25 2010-07-20 Stats Chippac, Ltd. Flip chip interconnection structure with bump on partial pad and method thereof
US8809182B2 (en) 2008-05-01 2014-08-19 International Business Machines Corporation Pad cushion structure and method of fabrication for Pb-free C4 integrated circuit chip joining
CN101969053B (zh) * 2008-05-16 2012-12-26 精材科技股份有限公司 半导体装置及其制造方法
TWI450371B (zh) * 2008-05-16 2014-08-21 精材科技股份有限公司 半導體裝置及其製造方法
US9165841B2 (en) * 2008-09-19 2015-10-20 Intel Corporation System and process for fabricating semiconductor packages
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Also Published As

Publication number Publication date
US7208841B2 (en) 2007-04-24
WO2005013319A3 (en) 2006-09-08
US6790759B1 (en) 2004-09-14
TW200518308A (en) 2005-06-01
JP2007502530A (ja) 2007-02-08
WO2005013319A2 (en) 2005-02-10
TWI354362B (en) 2011-12-11
US20050023680A1 (en) 2005-02-03
CN1926674A (zh) 2007-03-07
KR20060054382A (ko) 2006-05-22

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