KR101038355B1 - 플래시 메모리 소자 및 그의 제조 방법 - Google Patents

플래시 메모리 소자 및 그의 제조 방법 Download PDF

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Publication number
KR101038355B1
KR101038355B1 KR1020090006800A KR20090006800A KR101038355B1 KR 101038355 B1 KR101038355 B1 KR 101038355B1 KR 1020090006800 A KR1020090006800 A KR 1020090006800A KR 20090006800 A KR20090006800 A KR 20090006800A KR 101038355 B1 KR101038355 B1 KR 101038355B1
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KR
South Korea
Prior art keywords
film
layer
device isolation
groove
dielectric
Prior art date
Application number
KR1020090006800A
Other languages
English (en)
Korean (ko)
Other versions
KR20090118816A (ko
Inventor
조휘원
소남우
정철모
김정근
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to US12/464,947 priority Critical patent/US8138077B2/en
Priority to JP2009116165A priority patent/JP2009278098A/ja
Publication of KR20090118816A publication Critical patent/KR20090118816A/ko
Application granted granted Critical
Publication of KR101038355B1 publication Critical patent/KR101038355B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67075—Apparatus for fluid treatment for etching for wet etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
KR1020090006800A 2008-05-13 2009-01-29 플래시 메모리 소자 및 그의 제조 방법 KR101038355B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/464,947 US8138077B2 (en) 2008-05-13 2009-05-13 Flash memory device and method of fabricating the same
JP2009116165A JP2009278098A (ja) 2008-05-13 2009-05-13 フラッシュメモリ素子及びその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20080044117 2008-05-13
KR1020080044117 2008-05-13

Publications (2)

Publication Number Publication Date
KR20090118816A KR20090118816A (ko) 2009-11-18
KR101038355B1 true KR101038355B1 (ko) 2011-06-01

Family

ID=41364491

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090006800A KR101038355B1 (ko) 2008-05-13 2009-01-29 플래시 메모리 소자 및 그의 제조 방법

Country Status (2)

Country Link
KR (1) KR101038355B1 (zh)
CN (1) CN101582429A (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101215976B1 (ko) * 2011-03-07 2012-12-27 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 그 제조 방법
CN104078410B (zh) * 2013-03-27 2017-02-08 中芯国际集成电路制造(上海)有限公司 自对准浅槽隔离的形成方法
CN108807408B (zh) * 2017-05-02 2020-12-11 旺宏电子股份有限公司 半导体结构的制造方法
US10756113B2 (en) 2017-11-23 2020-08-25 Yangtze Memory Technologies Co., Ltd. Protective structure and fabrication methods for the peripheral circuits of a three-dimensional memory
CN107946312B (zh) * 2017-11-23 2019-01-29 长江存储科技有限责任公司 防止外围电路受损的方法及结构
CN111640703A (zh) 2019-07-02 2020-09-08 福建省晋华集成电路有限公司 半导体结构及其形成方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6548336B2 (en) * 2000-03-30 2003-04-15 Advanced Micro Devices, Inc. Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation
KR20060008555A (ko) * 2004-07-21 2006-01-27 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR20080035356A (ko) * 2006-10-19 2008-04-23 삼성전자주식회사 비휘발성 메모리 장치 및 그 형성 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6548336B2 (en) * 2000-03-30 2003-04-15 Advanced Micro Devices, Inc. Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation
KR20060008555A (ko) * 2004-07-21 2006-01-27 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR20080035356A (ko) * 2006-10-19 2008-04-23 삼성전자주식회사 비휘발성 메모리 장치 및 그 형성 방법

Also Published As

Publication number Publication date
CN101582429A (zh) 2009-11-18
KR20090118816A (ko) 2009-11-18

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