KR101035177B1 - Array substrate and the fabrication method for lcd - Google Patents

Abstract

The present invention relates to an array substrate of a liquid crystal display device and a method of manufacturing the same. An array substrate of a liquid crystal display according to the present invention includes: a data line and a gate line formed to cross each other on a transparent substrate; A data shorting bar and a gate shorting bar respectively formed at edges of the transparent substrate in the same direction as the data line and the gate line; A plurality of data pads and dummy data pads branched from the data shorting bar and a plurality of gate pads and dummy gate pads branched from the gate shorting bar; The data pad and the data line, the gate pad and the gate line is connected, characterized in that it comprises a dummy data link unit connected to the dummy data pad and a dummy gate link unit connected to the dummy gate pad. .

The array substrate of the liquid crystal display device and the manufacturing method thereof according to the present invention can be improved in reliability by removing the static electricity remaining in the dummy link portion formed for the step on the array substrate of the liquid crystal display device.

Dummy data pad, dummy data link part, dummy gate pad, dummy gate link part

Description

ARRAY SUBSTRATE AND THE FABRICATION METHOD FOR LCD

1 is a view schematically showing a structure of a conventional array substrate for a liquid crystal display device.

2 is an enlarged view of a portion A of FIG. 1;

3 is a schematic view showing a pad structure of an array substrate of a liquid crystal display according to the present invention.

4 is an enlarged view of a portion B of FIG. 3.

5 is an enlarged view of a portion C of FIG. 3.

<Description of the code for the main part of the drawing>

301 --- Data Shorting Bar 302 --- Gate Shorting Bar

401 --- Data Pad 402 --- Dummy Data Pad

403 --- Data Line 404 --- Dummy Data Link Section

501 --- Gate Pad 502 --- Dummy Gate Pad

503 --- Gate line 504 --- Dummy gate link

The present invention relates to a liquid crystal display device for preventing static electricity, in particular an array substrate of a liquid crystal display device that can be improved in reliability by removing the static electricity remaining in the dummy link portion formed for the step on the array substrate of the liquid crystal display device and It relates to a manufacturing method.

Recently, as the information society has progressed rapidly, a display field for processing and displaying a large amount of information has been developed.

Recently, the need for a flat panel display (plate panel display) has emerged in order to meet the era of thinning, light weight, low power consumption. Accordingly, a thin film transistor-liquid crystal display (hereinafter referred to as TFT-LCD) having excellent color reproducibility has been developed.

In general, a liquid crystal display (LCD) displays an image corresponding to a data signal on a panel by adjusting light transmittance of liquid crystal cells arranged in a matrix form on a liquid crystal panel with a video data signal supplied thereto. do.

To this end, the liquid crystal display device includes electrodes for applying an electric field to the liquid crystal layer, a thin film transistor (hereinafter referred to as TFT) for switching data supply for each liquid crystal cell, and data supplied from the outside of the liquid crystal cell. And signal wiring for supplying control signals to TFTs and control signals for TFTs.

The LCD is a manufacturing process of the upper and lower panels of the panel accompanied with the process of forming a liquid crystal cell forming a pixel unit, the formation and rubbing process of the alignment film for the alignment of the liquid crystal, the bonding process of the upper and lower plates, the bonded upper and It is completed through a number of processes, such as the process of injecting and encapsulating the liquid crystal between the lower plate. Here, the manufacturing process of the lower plate includes the formation of TFTs and the formation of other electrode portions by applying and etching electrode materials, semiconductor layers and insulating films on the substrate.

After the liquid crystal injection and encapsulation process, an IPT (In Process Test) of the liquid crystal panel is performed. This is performed by forming a shorting bar on the outer portion of the liquid crystal panel in order to facilitate defect inspection due to disconnection of the completed TFT-LCD array.

In addition, the shorting bar prevents static electricity generated during the process of the liquid crystal display device from being applied to the TFT-LCD array to destroy internal elements (thin film transistors, etc.).

In more detail, the shorting bar includes one shorting bar connected to each gate line and another shorting bar connected to each data line, and a shorting line to which each gate line is connected to check whether the gate line is shorted when inspecting the array. The power is applied to the bar and checked on the opposite side of each gate line to check whether the gate line is short-circuited, and the data line is checked in the same manner.

As described above, the shorting bar is not used at all in driving the actual TFT-LCD, but is used at the time of antistatic and array inspection as described above, and finally removed.

1 is a view schematically showing a structure of a conventional array substrate for a liquid crystal display device, and FIG. 2 is an enlarged view of a portion A of FIG. 1. This will be described with reference to FIGS. 1 and 2.

1 and 2, in the array substrate 100 of the liquid crystal display, a data shorting bar 101 is formed at one edge of the transparent substrate, and the data shorting bar 101 is formed. ), A plurality of data pads 201 and dummy data pads 202 are formed, and a data line 203 connected to the data pads 201 is integrally formed.

In addition, the gate shorting bar 102 and the gate shorting bar 102 branch to another edge portion of the transparent substrate to form a gate pad (not shown) and a dummy gate pad (not shown). Is formed in plurality, and a gate line (not shown) connected to the gate pad crosses the data line 203 to form a matrix.

The data line 203 is connected to the data shorting bar 101 through the data pad 201. The dummy data pad 202 is connected to the data shorting bar 101. In this case, a dummy link portion 204 is formed between the data pad 201 and the other data pad 201 to overcome the step difference of the substrate except for the portion where the data line 203 is connected. .

The data shorting bar 101, the data pad 201, the dummy data pad 202, the data line 203, and the dummy link part 204 are formed by depositing a metal film and then patterning the same.

In the meantime, although the data shortening bar 101 is formed in the center, the gate shorting bar, the gate pad, the dummy gate pad, the gate line, and the dummy gate link part also deposit a metal film and simultaneously pattern the same. To form.

Through the data shorting bar 101 and the gate shorting bar 102 formed in the liquid crystal display as described above, an IPT test (In Process Test) is performed during the manufacturing process, and the panel is prevented from being damaged due to static electricity. .

However, the static electricity generated in the dummy data link unit and the dummy gate link unit formed to overcome the step may cause static electricity to remain in the glass and the liquid crystal panel because a loop is not formed. .

SUMMARY OF THE INVENTION An object of the present invention is to provide an array substrate of a liquid crystal display device and a method of manufacturing the same, which may improve reliability by removing static electricity remaining on a dummy link portion formed for a step on the array substrate of the liquid crystal display device.

In order to achieve the above object, the array substrate of the liquid crystal display device according to the present invention,

A data line and a gate line formed to cross each other on the transparent substrate;

A data shorting bar and a gate shorting bar respectively formed at edges of the transparent substrate in the same direction as the data line and the gate line;

A plurality of data pads and dummy data pads branched from the data shorting bar and a plurality of gate pads and dummy gate pads branched from the gate shorting bar;

The data pad and the data line, the gate pad and the gate line is connected, characterized in that it comprises a dummy data link unit connected to the dummy data pad and a dummy gate link unit connected to the dummy gate pad. .

In this case, the dummy data pad and the dummy data link unit and the dummy gate pad and the dummy gate link unit are formed in one pattern.

In addition, in order to achieve the above object, a method of manufacturing an array substrate of a liquid crystal display device according to the present invention,

Depositing a metal film on a transparent substrate, and forming a pattern to connect a gate line, a gate pad, and a gate shorting bar, and to connect the gate shorting bar, the dummy gate pad, and the dummy gate link part;

Forming an insulating film on the resultant product;

After depositing a metal film on the insulating film, a data line, a data pad, and a data shorting bar are connected to each other, and the data shortening bar, a dummy data pad, and a dummy data link part include forming a pattern to be connected. have.

In particular, a thin film transistor and a pixel electrode are further formed on the resultant material formed on the insulating film.

In particular, a thin film transistor, a pixel electrode and a common electrode are further formed on the resultant formed on the insulating film.                     

According to the present invention, the reliability can be improved by removing the static electricity remaining in the dummy link portion formed for the step on the array substrate of the liquid crystal display device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram schematically illustrating a pad structure of an array substrate of a liquid crystal display according to the present invention, and FIGS. 4 and 5 are enlarged views of a portion of FIG. 3.

An array substrate of a liquid crystal display according to the present invention will be described with reference to FIGS. 3 to 5.

3 to 5, the array substrate 300 of the liquid crystal display device includes: a data line 403 and a gate line 503 formed to cross each other on a transparent substrate; A data shorting bar 301 and a gate shorting bar 302 formed at edges of the transparent substrate in the same direction as the data line 403 and the gate line 503, respectively; A plurality of data pads 401 and a dummy data pad 402 branched from the data shorting bar 301 and a plurality of gate pads 501 and dummy gate pads 502 branched from the gate shorting bar 302. )Wow; The data pad 401 and the data line 403, the gate pad and the gate line are connected to each other, and are connected to the dummy data link unit 404 and the dummy gate pad connected to the dummy data pad 402. Its feature is that it includes a dummy gate link portion.

In particular, the gate shorting bar 302 and the data shorting bar 301 are formed to be perpendicular to each other at the edge portion of the transparent substrate.

In addition, the gate pads 501 branched from the gate shorting bar 302 are connected to the gate line 503 formed on the array substrate and branched from the data shorting bar 301. The data pad 401 is connected to the data line 403.

Accordingly, the static electricity generated in the array substrate is discharged through the data shorting bar 301 and the gate shorting bar 302 connected to the data line 403 and the gate line 503.

The dummy data pad 402 and the dummy data link unit 404 are formed in an integrated pattern and connected to the data shorting bar 301. In addition, the dummy gate pad 503 and the dummy gate link unit 504 are also formed in an integrated pattern and are connected to the gate shorting bar 302.

The data shorting bar 301 and the gate may discharge the static electricity remaining in the dummy gate pad 502, the dummy gate link unit 504, the dummy data pad 402, and the dummy data link unit 404. It is connected to the shorting bar 302.

In more detail, the dummy gate pad 502, the dummy gate link unit 504, the dummy data pad 402, and the dummy data link unit 404 may include the gate line 503 patterned on the array substrate, It is formed to overcome the step with the gate pad 501, the data line 403, and the data pad 401.

That is, when the gate line 503, the gate pad 501, the data line 403, and the data pad 401 are formed on the array substrate, the gate lines 503, the gate pad 501, the data line 403, and the data pad 401 are formed on the array substrate. Will appear.                     

Therefore, the dummy gate pad 502, the dummy gate link unit 504, the dummy data pad 402, and the dummy data link unit 404 are further formed to remove this.

Meanwhile, a method of manufacturing the array substrate of the liquid crystal display device according to the present invention will be described. According to the method of manufacturing an array substrate of a liquid crystal display device according to the present invention, first, a metal film is deposited on a transparent substrate, and then a gate line 503, a gate pad 501, and a gate shorting bar 302 are connected. A pattern is formed to connect the gate shorting bar 302, the dummy gate pad 502, and the dummy gate link unit 504.

In more detail, the gate shorting bar 302, the gate pad 501, the gate line 503, the dummy gate pad 502, and the dummy gate link part 504 are formed by depositing a metal film on the transparent substrate. Then, a photoresist is applied on the metal film, and exposure and development are performed using an exposure mask having a predetermined pattern. According to the developed pattern, the metal film is etched using a predetermined etchant and then removed by removing the photoresist remaining on the metal film.

An insulating film is formed on the resultant product.

Then, after depositing a metal film on the insulating film again, the data line 403, the data pad 401, the data shorting bar 301 is connected, the data shorting bar 301, the dummy data pad 402 The dummy data link unit 404 is connected to form a pattern.

Here, the data line 403, the data pad 401, the data shorting bar 301, the dummy data pad 402, and the dummy data link unit 404 are the gate shorting bar 302 and the The gate pad 501, the gate line 503, the dummy gate pad 502, and the dummy gate link unit 504 may be formed in the same manner as the method of forming the gate pad 501, the gate line 503, the dummy gate link 502, and the dummy gate link unit 504.

After depositing a metal film on the insulating film, a thin film transistor and a pixel electrode are sequentially formed on the formed resultant.

In more detail, when the liquid crystal driving mode of the liquid crystal display device is the TN mode, the pixel electrode is formed on the array substrate, and the common electrode is formed on the upper plate.

On the other hand, when the liquid crystal driving mode of the liquid crystal display device is the IPS mode, since the pixel electrode and the common electrode are formed on the same substrate, after depositing a metal film on the insulating film, the thin film transistor, the pixel electrode and the common on the formed resultant Further electrodes are formed.

Although the present invention has been described with reference to the embodiments illustrated in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the array substrate of the liquid crystal display device and the method of manufacturing the same according to the present invention may improve reliability by removing static electricity remaining in the dummy link portion formed for the step on the array substrate of the liquid crystal display device.

Claims (6)

A plurality of data lines and a plurality of gate lines formed to cross each other on the transparent substrate; A data shorting bar and a gate shorting bar respectively formed at edges of the transparent substrate in the same direction as the data line and the gate line; A plurality of first and second data pads and dummy data pads formed in a plurality of branches in the data shorting bar, each having a rectangular shape; A plurality of first and second gate pads and a dummy gate pad formed on a plurality of branches in the gate shorting bar, each having a quadrangular shape; A dummy data link unit disposed between the data line connected to the first data pad and the data line connected to the second data pad and electrically connected to the dummy data pad; A dummy gate link unit disposed between the gate line connected to the first gate pad and the gate line connected to the second gate pad and electrically connected to the dummy gate pad; The dummy data pad has at least the same width as the dummy data link unit between the first and second data pads. And the dummy gate pad has at least the same width as the dummy gate link portion between the first and second gate pads. The method of claim 1, And the dummy data pad and the dummy data link unit or a pattern in which the dummy gate pad and the dummy gate link unit are connected to each other. The method of claim 1, The dummy data link unit and the dummy data pad are connected to the data shorting bar, and the dummy gate link part and the dummy gate pad are connected to the gate shorting bar, thereby eliminating static electricity on a substrate. Array substrate of the device. After depositing a metal film on the transparent substrate, a plurality of gate lines, first and second gate pads and dummy gate pads connected to the plurality of gate lines, gate shorting bars connected to the first and second gate pads and the first Forming a dummy gate link portion between the gate line connected to the first gate pad and the gate line connected to the second gate pad; Forming an insulating film on the gate line, the first and second gate pads, the dummy gate pad, the gate shorting bar, and the dummy gate link part; After depositing a metal film on the insulating layer, a plurality of data lines, first and second data pads and dummy data pads connected to the plurality of data lines, data shorting bars connected to the first and second data pads, and the first data pads. Forming a dummy data link unit between a data line connected to the first data pad and a data line connected to the second data pad; The dummy gate link unit is electrically connected to the dummy gate pad, The dummy data link unit is electrically connected to the dummy data pad, The first and second gate pads, the dummy gate pad, the first second data pad and the dummy data pad each have a quadrangular shape. The dummy data pad has at least the same width as the dummy data link unit between the first and second data pads. And the dummy gate pad has at least the same width as the dummy gate link portion between the first and second gate pads. The method of claim 4, wherein And forming a pixel electrode on the data line, the first and second data pads, the dummy data pad, the data shorting bar, and the dummy data link unit. Manufacturing method. The method of claim 4, wherein And forming a pixel electrode and a common electrode on the data line, the first and second data pads, the dummy data pad, the data shorting bar, and the dummy data link unit. Method for producing an array substrate.

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