JP2004317885A - Display panel forming plate and display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display panel forming plate and a display panel that are deterred from corroding from their inspection input terminals. <P>SOLUTION: The display panel forming plate 20 is constituted by arraying and integrating a plurality of display panels each of which has a gate bus line 1 and a source bus line 2 and inspection wiring connected thereto; and the inspection wiring of the respective display panels crosses parts to be parted between the display panel and adjacent display panels contiguous thereto, inspection input terminals 21 are provided at their ends, and the parts to be parted constitute flexible printed wiring board fitting parts 22 of the display panels. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display panel forming plate and a display panel.
[0002]
[Prior art]
In recent years, liquid crystal display devices, which have been attracting attention as display media, take advantage of their features of being thin and low power consumption, OA equipment such as a personal computer, a camera-integrated VTR equipped with a liquid crystal monitor, and a mobile phone or PDA. (Personal Digital Assistant) is widely used in portable information devices and the like.
[0003]
Meanwhile, some liquid crystal display devices include an active matrix substrate in which a plurality of pixel electrodes are arranged in a matrix, a counter substrate provided with a common electrode, and a liquid crystal layer sandwiched between the two substrates. . Such a liquid crystal display device applies a predetermined voltage to a liquid crystal capacitor composed of a liquid crystal layer between a pixel electrode and a common electrode by writing a predetermined charge to a pixel electrode, and optically controls the liquid crystal layer in accordance with the voltage. Image display is performed by utilizing the occurrence of modulation.
[0004]
In such a liquid crystal display device, a lighting test is performed before mounting a mounting component such as a driver IC chip (when a liquid crystal panel is completed).
[0005]
Patent Literature 1 discloses a general inspection method. The method of inspecting the liquid crystal panel will be described below with reference to the drawings.
[0006]
FIG. 10 shows a liquid crystal panel.
[0007]
This liquid crystal panel includes an active matrix substrate 40 and a counter substrate, and a liquid crystal layer sandwiched between the two substrates.
[0008]
The active matrix substrate 40 has a display area 19 at the center thereof. In the display area 19, a plurality of gate bus lines 1 extending in parallel with each other and a plurality of source bus lines 2 extending in parallel with each other in a direction orthogonal to the gate bus lines 1 are provided. I have.
[0009]
An odd-numbered gate bus line 1 is connected to a region outside the display region 19, that is, a left side portion of the liquid crystal panel in the non-display region so as to extend in parallel with each other along the source bus line 2. A test gate signal input line (odd number) 1a and a test gate signal input line (even number) 1b to which the even-numbered gate bus line 1 is connected are provided. In the lower left portion of the liquid crystal panel, a test input terminal GO at the end of the test gate signal input line (odd) 1a and a test input terminal GE at the end of the test gate signal input line (even) 1b are provided, respectively. I have. Further, on the upper side of the liquid crystal panel, a test source signal input line (red) 2a to which a source bus line 2 related to red display is connected so as to extend in parallel with the gate bus line 1 and a green color An inspection source signal input line (green) 2b to which the source bus line 2 for display is connected, and an inspection source signal input line (blue) 2c to which the source bus line 2 for blue display is connected are provided. I have. In the upper left portion of the liquid crystal panel, the test input terminal R at the end of the test source signal input line (red) 2a, the test input terminal G at the end of the test source signal input line (green) 2b, and the test source signal An inspection input terminal B at the end of the input line (blue) 2c is provided. A gate driver IC chip mounting portion 16 for mounting a gate driver IC chip is disposed on the right side of the liquid crystal panel, and a source driver IC chip mounting portion 17 for mounting the source driver IC chip is disposed on the lower side. Is provided. Further, an inspection common electrode wiring 9 connected to the common electrode 11b of the opposite substrate is provided so as to surround the display area 19. An inspection input terminal C at the end of the inspection common electrode wiring 9 is provided in the lower right portion of the liquid crystal panel.
[0010]
In the inspection of the liquid crystal panel, first, while inputting a certain common electrode inspection signal to the inspection input terminal C connected to the common electrode 11b, the inspection input terminal GO or the inspection input terminal GE connected to the gate bus line 1 is input. To input a predetermined gate inspection signal to turn on the TFT 10 connected to the gate bus line 1. Then, a predetermined source test signal is input to one of the test input terminal R, test input terminal G, and test input terminal B connected to the source bus line 2, and the predetermined source test signal is supplied to the specific pixel electrode 11a via the drain electrode. Is written. At this time, a predetermined voltage is applied to the liquid crystal capacitance formed between the pixel electrode 11a and the common electrode 11b, and the pixel formed by the pixel electrode 11a is turned on (displayed). As described above, by selectively inputting the gate test signal to the test input terminal GO and the test input terminal GE and the source test signal to the test input terminal R, the test input terminal G and the test input terminal B, and appropriately lighting the pixels. A lighting inspection of the liquid crystal panel is performed.
[0011]
After performing such an inspection, the liquid crystal panel is cut by means such as dicing or laser cutting, and the left side and the upper side where the inspection wiring and the inspection input terminal are provided are cut off.
[0012]
However, according to this method, in addition to the problem that a step related to division is required, there is a problem that a new defect may be generated due to a broken wiring pattern, glass chips, or the like caused by the division. Therefore, Patent Document 2 discloses an example of a means for avoiding an increase in the number of steps for cutting, in which a wiring for supplying an inspection signal is not completely electrically conducted, and a switching of a TFT or the like is performed in that part. A method is disclosed in which elements are arranged and a signal for turning on the switching elements is supplied as needed at the time of inspection. The method of inspecting the liquid crystal panel will be described below with reference to the drawings.
[0013]
FIG. 11 shows a liquid crystal panel using a TFT as a switching element. Note that components having substantially the same functions as those shown in FIG. 10 are denoted by common reference numerals, and description thereof will be omitted.
[0014]
In this liquid crystal panel, in addition to the configuration of FIG. 10, an inspection control signal line 5 is provided outside the display area along the gate bus line 1 and the source bus line 2 as the inspection wiring. An inspection input terminal SW at the end of the inspection control signal line 5 is provided in the lower left portion of the liquid crystal panel. Further, a test TFT 3 is provided at each end of the plurality of gate bus lines 1 and source bus lines 2.
[0015]
The inspection TFT 3 provided on the gate bus line 1 has a gate electrode connected to the inspection control signal line 5, a source electrode connected to the gate bus line 1, and a drain electrode connected to the inspection gate signal input line (odd number) 1a or the inspection gate. It is connected to the signal input line (even number) 1b.
[0016]
The inspection TFT 3 provided in the source bus line 2 has a gate electrode to the inspection control signal line 5, a source electrode to the source bus line 2, a drain electrode to the inspection source signal input line (red) 2a, and an inspection source. It is connected to one of the signal input line (green) 2b and the inspection source signal input line (blue) 2c.
[0017]
In testing the liquid crystal panel, a test input terminal C connected to the common electrode 11b, a test input terminal SW connected to the test control signal line 5, a test input terminal GO connected to the gate bus line 1, and By selectively inputting a test signal to the test input terminal GE and the test input terminals R, G, and B connected to the source bus line 2, the pixels are appropriately turned on.
[0018]
A specific inspection method will be described based on the timing charts illustrated in FIGS.
[0019]
The lighting inspection of the liquid crystal panel is performed according to the following inspection patterns I, II and III.
[0020]
(A) Inspection pattern I
First, as shown in FIG. 6, a control test signal having a potential of +25 V is input to the test control signal line 5 (SW) to turn on the test TFT 3. As a result, the inspection gate signal input line (odd number) 1a (GO) and the inspection gate signal input line (even number) 1b (GE) are connected to each gate bus line 1 and the inspection source signal input line (red) 2a (R). ), The inspection source signal input line (green) 2 b (G) and the inspection source signal input line (blue) 2 c (B) are electrically connected to each source bus line 2. A gate of a +15 V pulse voltage having a bias voltage of −10 V, a cycle of 16.7 msec, and a pulse width of 50 μsec is applied to the inspection gate signal input line (odd number) 1 a (GO) and the inspection gate signal input line (even number) 1 b (GE). An inspection signal is input to turn on all the TFTs 10 in the display area 19. Further, the polarity of the test source signal input line (red) 2a (R), the test source signal input line (green) 2b (G), and the test source signal input line (blue) 2c (B) is changed every 16.7 msec. Is input, a charge corresponding to ± 2 V is written to the pixel electrode 11 a via the source electrode and the drain electrode of each TFT 10. At the same time, a common electrode inspection signal having a potential of -1 V is input to the inspection common electrode wiring 9 (C). As a result, a voltage is applied to the liquid crystal capacitance formed between the pixel electrode 11a and the common electrode 11b, and the pixel formed by the pixel electrode 11a is turned on (displayed). The display is displayed. In this case, in a pixel having a defective portion where the wiring is disconnected between the drain electrode and the pixel electrode, a predetermined charge cannot be written to the pixel electrode, and the pixel is turned off (bright point). Conversely, in a pixel having a defective portion in which a leak occurs between the gate bus line and the drain electrode, the charge from the gate bus line is always written to the pixel electrode, and the pixel is turned on (black dot). . This makes it possible to detect a disconnection of the wiring and a leak between the gate bus line and the drain electrode.
[0021]
(B) Inspection pattern II
First, as shown in FIG. 7, a control inspection signal having a potential of +25 V is input to the inspection control signal line 5 (SW) to turn on the inspection TFT 3. Then, a gate inspection signal a having a bias voltage of −10 V, a pulse voltage of +15 V having a period of 33.4 msec and a pulse width of 50 μsec is input to the inspection gate signal input line (even number) 1 b (GE), and the inspection gate signal input line is provided. A gate test signal b similar to the gate test signal a and shifted by 16.7 msec from the gate test signal a is input to (odd) 1a (GO). At this time, the TFTs 10 connected to the odd-numbered gate bus lines 1 and the TFTs 10 connected to the even-numbered gate bus lines 1 are alternately turned on at a period of 16.7 msec. Further, a source having a potential of ± 2 V whose polarity is inverted every 16.7 msec is applied to the test source signal input line (red) 2a, the test source signal input line (green) 2b, and the test source signal input line (blue) 2c. An inspection signal is input, and a charge corresponding to ± 2 V is written to the pixel electrode 11 a via the source electrode and the drain electrode of each TFT 10. At the same time, a common electrode inspection signal having a potential of -1 V is input to the inspection common electrode wiring 9 (C). As a result, a predetermined voltage is applied to the liquid crystal capacitance, and the pixels corresponding to the odd-numbered gate bus lines 1 and the pixels corresponding to the even-numbered gate bus lines 1 are alternately turned on at a period of 16.7 msec. Therefore, a leak between the adjacent gate bus lines 1 can be detected.
[0022]
(C) Inspection pattern III
First, as shown in FIG. 8, a control test signal having a potential of +25 V is input to the test control signal line 5 (SW) to turn on the test TFT 3. A gate of a +15 V pulse voltage having a bias voltage of −10 V, a cycle of 16.7 msec, and a pulse width of 50 μsec is applied to the inspection gate signal input line (odd number) 1 a (GO) and the inspection gate signal input line (even number) 1 b (GE). An inspection signal is input to turn on all the TFTs 10 in the display area 19. At the same time, a common electrode inspection signal having a potential of -1 V is input to the inspection common electrode wiring 9 (C). Further, for example, a source test signal a having a potential of ± 1 V whose polarity is inverted every 16.7 msec is input to the test source signal input line (red) 2 a (R), and the test source signal input line (green) is input. A source test signal b having a potential of ± 5 V whose polarity is inverted every 16.7 msec is input to 2b (G) and the test source signal input line (blue) 2c (B). Accordingly, if there is a leak between the source bus line 2 displaying red and another adjacent source bus line 2, the leaking source bus line 2 is displayed in a different red color. By inputting these test signals, it is possible to detect a leak between the source bus line 2 displayed in red and another source bus line 2 adjacent thereto. Further, the inspection source signal input line (green) 2b (G) and the inspection source signal input line (blue) 2c (B) are similar to the inspection source signal input line (red) 2a (R). If the inspection is performed according to the procedure, a leak between the adjacent source bus lines 2 can be detected.
[0023]
Patent Document 2 also discloses a method of performing a liquid crystal panel inspection for each strip substrate on which a plurality of liquid crystal panels are arranged in rows in the same direction.
[0024]
FIG. 12 shows a general manufacturing process for manufacturing the liquid crystal panel 100 via the mother substrate 50 and the strip substrate 20. FIG. 13 shows a configuration of each liquid crystal panel 100 in the strip substrate 20.
[0025]
The method of inspecting the strip substrate 20 will be described below.
[0026]
The strip substrate 20 is a strip-shaped substrate in which the mother substrate 50 is cut along the horizontal cutting lines 6a. In the strip substrate 20, the plurality of liquid crystal panels 100 are arranged via the vertical dividing lines 6b such that the direction in which the gate bus line 1 of each liquid crystal panel extends is the arrangement direction. The test input terminals 7 (test input terminals GE, GO, and SW) and 8 (test input terminals R, G, B, and C) of each liquid crystal panel 100 are arranged on the lower side of each liquid crystal panel 100 on the strip substrate 20. Has been established. Note that the upper and lower sides of the mother substrate 50 and the left and right side portions of the strip substrate 20 at the end regions of the substrates are discarded substrates without the liquid crystal panel 100 disposed.
[0027]
When inspecting the strip substrate 20, the strip substrate 20 is set in an inspection apparatus, and an inspection probe is applied to each of the inspection input terminals 7 and 8 of each liquid crystal panel 100. As shown in III, by selectively inputting a test signal to the test input terminal C, the test input terminal SW, the test input terminal GO, the test input terminal GE, the test input terminal R, the test input terminal G, and the test input terminal B. Then, the pixels are appropriately turned on. Thereby, the inspection efficiency of the liquid crystal panel 100 can be improved. In particular, this is an effective means for improving the inspection efficiency of small and medium-sized liquid crystal panels 100 such as liquid crystal panels for vehicles and mobile phones.
[0028]
However, usually, a metal which is easily corroded (oxidized) such as aluminum is often used for the wiring and the inspection wiring in the substrate. In this case, the terminals of the test input terminal 7 (test input terminals GE, GO, and SW) and the test input terminal 8 (test input terminals R, G, B, and C) that are in contact with the outside air are corroded, and the corrosion is caused by the terminal. From the liquid crystal panel 100 to the display area 19 of the liquid crystal panel 100, which may hinder image display on the liquid crystal panel 100. In order to prevent corrosion from the test input terminals 7 and 8, it is conceivable to apply a resin to the surfaces of the test input terminals 7 and 8. Is costly and unrealistic.
[0029]
As shown in FIGS. 14A and 14B, in a COG (Chip On Glass) type liquid crystal panel 100 in which a driver IC chip for driving a liquid crystal is directly mounted on the liquid crystal panel 100, the display of the liquid crystal panel 100 is performed. A resin application step of attaching an FPC (Flexible Printed Circuit) 15 to the surface of the FPC terminal 14 for inputting power in the region 19 and applying the resin 18 to the end surface 14a of the FPC terminal 14 is indispensable.
[0030]
Therefore, by utilizing the resin coating step indispensable during this manufacturing process, the test input terminals 7 and 8 are arranged in the FPC area 22 to which the FPC 15 is attached as shown in FIG. It is conceivable to prevent the corrosion of No. 8.
[0031]
According to this, after the inspection and division of the liquid crystal panel 100, the surfaces of the inspection input terminals 7 and 8 including the FPC terminal 14 are covered with the film substrate of the FPC 15 and do not come into contact with the atmosphere. 7 and 8 do not corrode. However, in this corrosion prevention measure, the corrosion prevention effect occurs only by covering the portion to be corroded.
[0032]
[Patent Document 1]
JP-A-7-5481
[Patent Document 2]
JP-A-11-338376
[0033]
[Problems to be solved by the invention]
The present invention has been made in view of such a point, and an object of the present invention is to provide a display panel forming plate and a display panel in which the progress of corrosion from an inspection input terminal is suppressed.
[0034]
[Means for Solving the Problems]
The display panel forming plate of the present invention is a display panel forming plate in which a plurality of display panels each having a display wiring and an inspection wiring connected to the display wiring are arranged in a line and integrated. The inspection wiring of each of the display panels crosses a portion to be divided between the display panel and an adjacent display panel adjacent thereto, and an inspection input terminal is provided at an end thereof, and the portion to be divided is The display panel is characterized by constituting a flexible printed wiring board mounting portion.
[0035]
According to the above configuration, the inspection wiring of each display panel is provided so as to cross the part to be divided. Therefore, when the display panel forming plate is divided into each display panel at the part to be divided, the inspection wiring is formed. The inspection input terminal is separated into the display panel side and the corrosion is prevented from progressing from the inspection input terminal into the display panel. Further, the portion to be divided constitutes the flexible printed wiring board mounting portion, and the end surface generated by the division of the inspection wiring coincides with the end surface of the flexible printed wiring board mounting portion. The layer covers the divided end faces of the inspection wiring at the same time, so that corrosion can be prevented.
[0036]
In the display panel forming plate of the present invention, an in-panel inspection input terminal connected to the inspection wiring of the display panel may be provided on the flexible printed wiring board mounting portion of the display panel.
[0037]
According to the above configuration, an in-panel inspection input terminal for inputting an inspection signal into the display panel is provided in the flexible printed wiring board mounting portion. Therefore, even in the state of the display panel after the division, each of the display panels can be inspected again via the in-panel inspection input terminal. As a result, a display panel that has become defective due to a defect between the in-panel inspection input terminal and the inspection input terminal can be made a non-defective product if the re-inspection results in a pass. Can be improved.
[0038]
The display panel forming plate of the present invention is provided so as to extend along the arrangement direction of the plurality of display panels, and may include a common inspection wire to which the respective inspection wires of the plurality of liquid crystal panels are connected. Good.
[0039]
According to the above configuration, each inspection wiring of the display panel constituting the display panel forming plate is connected to the common inspection wiring. Thus, if an inspection input signal is input to the common inspection wiring, all the display panels connected to the common inspection wiring can be inspected at once, and the inspection efficiency can be improved. .
[0040]
In the display panel forming plate of the present invention, the inspection input terminal may be formed of aluminum and / or molybdenum.
[0041]
According to the above configuration, since the test input terminal is formed of a material which is easily corroded by aluminum and / or molybdenum, it is possible to more effectively suppress the progress of corrosion from the test input terminal.
[0042]
The display panel of the present invention may be a liquid crystal display panel.
[0043]
According to the above configuration, when a liquid crystal display panel is used as the display panel, high-definition display with low power consumption is performed.
[0044]
The display panel of the present invention is characterized in that the display panel forming plate of the present invention is divided along a portion to be divided.
[0045]
According to the above configuration, the display panel forming plate to be divided is prevented from progressing into the display panel due to corrosion from the inspection input terminal of the display panel which is a component of the display panel forming plate. Corrosion of the divided display panel is suppressed.
[0046]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a display panel forming plate and a display panel according to the present invention will be described in detail with reference to the drawings. In the following embodiments, a liquid crystal display panel in which a TFT is used as a switching element will be described as an example of a display panel. However, the display panel of the present invention is not limited to this, and can be applied to an active drive type liquid crystal display panel using a switching element other than a TFT. Further, the present invention can be applied not only to an active drive type liquid crystal display panel but also to a passive (multiplex) drive type liquid crystal display panel. Furthermore, the display panel of the present invention can be applied to other display panels such as an organic electroluminescence (EL) display panel and an inorganic EL display panel other than the liquid crystal display panel.
[0047]
(Embodiment 1)
Hereinafter, the liquid crystal display panel forming plate and the liquid crystal display panel according to the first embodiment of the present invention will be described with reference to FIGS. 1, 2, 9A, and 12. FIG. FIG. 1 shows a liquid crystal display panel forming plate 20 according to Embodiment 1 of the present invention, and FIG. 9A shows a pixel region of an active matrix substrate 40 of a general liquid crystal display panel 100. FIG. 2 is a schematic cross-sectional view taken along line AB in FIG. 9A, showing a cross section of the TFT 10. FIG. 12 is a cross-sectional view of a liquid crystal display panel forming mother plate (mother substrate) 50 and a liquid crystal display panel forming substrate. A general manufacturing process for manufacturing the liquid crystal display panel 100 via a plate (strip substrate) 20 will be described.
[0048]
As shown in FIG. 12, a liquid crystal display panel forming plate (hereinafter, referred to as a “strip substrate”) 20 is a horizontal dividing plate in which a liquid crystal display panel forming mother plate (hereinafter, referred to as a “mother substrate”) 50 is to be divided. It is a strip-shaped substrate divided along the disconnection line 6a, in which a plurality of liquid crystal display panels 100 are arranged in a row through vertical divisional disconnection lines 6b which are scheduled to be divided. Note that the upper and lower sides of the mother substrate 50 and the left and right sides of the strip substrate 20 are discarded without the liquid crystal display panel 100 disposed in the end regions of the respective substrates.
[0049]
Each liquid crystal display panel 100 of the strip substrate 20 includes an active matrix substrate portion 40 having a plurality of pixel electrodes 11a arranged in a matrix and a counter substrate portion having a common electrode 11b, and a display medium is provided between the two substrate portions. Is sandwiched. The active matrix substrate section 40 of each liquid crystal display panel 100 of the strip substrate 20 is an integrated substrate and constitutes a common active matrix substrate 40, and its opposing substrate section is an integral substrate and has a common opposing substrate. Constitutes a substrate.
[0050]
The display region 19 is formed in the center of the active matrix substrate section 40. In the display area 19, a plurality of gate bus lines 1 extending in parallel with each other along the vertical dividing lines 6b and the horizontal dividing lines 6a and 6a 'intersecting the gate bus lines 1 are provided as display wirings. A plurality of source bus lines 2 extending in parallel with each other are provided with TFTs 10 provided at each intersection of the gate bus line 1 and the source bus line 2 as switching elements.
[0051]
The gate bus line 1 is composed of a laminated film such as a titanium nitride film 31a / aluminum film 31b / titanium film 31c. Further, auxiliary capacitance electrodes 12 are also provided between the respective gate bus lines 1 so as to extend from each other. Further, a gate insulating film 32 made of silicon nitride or the like is provided so as to cover the gate bus line 1 and the storage capacitor electrode 12.
[0052]
The source bus line 2 is formed of a laminated film such as an aluminum film 35a / titanium film 35b and is provided on the gate insulating film 32.
[0053]
The TFT 10 includes a gate electrode 31 having a protrusion protruding laterally from the gate bus line 1, a semiconductor film 33, and a source electrode 35 having a protrusion protruding laterally from the source bus line 2 on the semiconductor film 33. And a drain electrode 34 also provided on the semiconductor film 33 so as to face the source electrode 35. Further, a first interlayer insulating film 36 made of silicon nitride or the like is provided so as to cover the TFT 10, and a second interlayer insulating film 37 made of resin is provided so as to cover the first interlayer insulating film 36.
[0054]
The semiconductor film 33 is provided on the gate electrode 31 with the gate insulating film 32 interposed therebetween, and is composed of an intrinsic amorphous silicon layer 33a and n + amorphous silicon 33b doped with phosphorus from the gate electrode 31 side.
[0055]
The pixel electrode 11a is made of ITO (Indium Tin Oxide) or the like, and is connected to the drain electrode 34 of the TFT 10 via a contact hole 39.
[0056]
In addition, in a non-display area outside the active matrix substrate section 40, a test gate composed of a test gate signal input line (odd number) 1a and a test gate signal input line (even number) 1b is formed as a test wiring. The signal input lines extend in parallel to each other along the source bus line 2 at the upper side of the liquid crystal display panel 100, cross the flexible printed wiring board mounting portion 22 described later, and reach the display area 19 of the adjacent liquid crystal display panel 100. The liquid crystal display panel 100 is provided so as to bend downward in the front position and extend in parallel with each other along the gate bus line 1. The inspection source signal input line (red) 2a, the inspection source signal input line (green) 2b, and the inspection source signal input line (blue) 2c are connected to the inspection source signal input line of the liquid crystal display panel 100. On the right side, they extend in parallel with each other along the gate bus line 1, bend in the direction of the adjacent liquid crystal display panel 100 around the display area 19, cross the flexible printed wiring board mounting portion 22 described later, and are adjacent to each other. At a position before reaching the display area 19 of the liquid crystal display panel 100, the liquid crystal display panel 100 is provided so as to bend again in the downward direction and extend in parallel with each other along the gate bus line 1. Further, the inspection control signal line 5 composed of the gate bus line inspection control signal line 5a and the source bus line inspection control signal line 5b is mutually parallel to the upper side of the liquid crystal display panel 100 along the source bus line 2. And bends in the direction of the adjacent liquid crystal display panel 100 around the display area 19, crosses the flexible printed wiring board mounting portion 22 described later, and reaches the display area 19 of the adjacent liquid crystal display panel 100. Are bent downward in the lower direction of the liquid crystal display panel 100 at the position, and extend in parallel with each other along the gate bus line 1. In addition, the inspection common electrode wiring 9 extends in parallel to the lower side of the liquid crystal display panel 100 along the source bus line 2, crosses a flexible printed wiring board mounting portion 22 described later, At the position before reaching the display area 19, the liquid crystal display panel 100 is provided so as to bend again in the downward direction and extend in parallel with each other along the gate bus line 1. Further, as a switching element for inspection, an inspection TFT 3 is provided at each end of the plurality of gate bus lines 1 on the upper side of the liquid crystal display panel 100 and at each end of the plurality of source bus lines 2 on the right side of the liquid crystal display panel 100. Have been.
[0057]
The inspection gate signal input line (odd number) 1a is formed of the same material in the same layer as the source bus line 2 and is connected to all odd-numbered gate bus lines 1 via contact holes (not shown). An inspection input terminal GO, which is the terminal, is provided on the left side of a gate driver IC chip mounting area 16 to be described later of the adjacent liquid crystal display panel 100.
[0058]
The inspection gate signal input line (even number) 1b is formed in the same layer as the source bus line 2 from the same material, and is connected to all even-numbered gate bus lines 1 via contact holes (not shown). An inspection input terminal GE, which is the terminal, is provided on the left side of a gate driver IC chip mounting area 16 to be described later of the adjacent liquid crystal display panel 100.
[0059]
Here, the inspection gate signal input line (odd number) 1a and the inspection gate signal input line (even number) 1b connected to the gate bus line 1 are for detecting a leak between the adjacent gate bus lines 1 by lighting inspection. For example, a connection structure as shown in FIG. 16A is formed, and the inspection gate signal input line (odd number) 1 a is provided so as to straddle the gate bus line 1. However, for example, as shown in FIG. 16B, the strip substrate 20 on which the inspection gate signal input lines 1t connected to all the gate bus lines 1 in one pixel region are arranged (for example, FIG. 17). In this case, it becomes impossible to detect a leak between the adjacent gate bus lines 1 by the lighting inspection.
[0060]
The inspection source signal input line (red) 2a is formed of the same material in the same layer as the gate bus line 1 and is connected to the source bus line 2 related to red display via a contact hole (not shown). An inspection input terminal R, which is the terminal, is provided on the left side of a gate driver IC chip mounting area 16 described later of the liquid crystal display panel 100.
[0061]
The inspection source signal input line (green) 2b is formed of the same material in the same layer as the gate bus line 1 and is connected to the source bus line 2 related to green display via a contact hole (not shown). A test input terminal G at the end of the gate driver IC chip mounting area 16 to be described later is provided on the left side of the liquid crystal display panel 100 to be described later.
[0062]
The inspection source signal input line (blue) 2c is formed of the same material in the same layer as the gate bus line 1, and is connected to the source bus line 2 related to blue display via a contact hole (not shown). On the left side of a gate driver IC chip mounting area 16 to be described later of the adjacent liquid crystal display panel 100, an inspection input terminal B is provided at the end.
[0063]
The gate bus line inspection control signal line 5a is formed of the same material on the same layer as the source bus line 2, and the source bus line inspection control signal line 5b is formed of the same material on the same layer as the gate bus line 1. An inspection input terminal SW at the end of the gate driver IC chip mounting area 16 to be described later is provided on the left side of the adjacent liquid crystal display panel 100. The gate bus line inspection control signal line 5a and the source bus line inspection control signal line 5b are connected via a contact hole (not shown) at the intersection.
[0064]
The inspection common electrode wiring 9 is formed in the same layer and the same material as the source bus line 2, is connected to the common electrode 11 b, and is located on a left portion of a gate driver IC chip mounting area 16 of the adjacent liquid crystal display panel 100, which will be described later. Is provided with a test input terminal C at the terminal.
[0065]
The inspection TFT 3 is formed of the same material and in the same layer as the display TFT 10 in the display area 19 of the active matrix substrate section 40.
[0066]
In the inspection TFT 3 provided in the gate bus line 1, the gate electrode 31 is connected to the gate bus line inspection control signal line 5 a via a contact hole (not shown), and the source electrode 35 is connected to the gate bus line 1. The drain electrode 34 is connected to an inspection gate signal input line (odd number) 1a or an inspection gate signal input line (even number) 1b.
[0067]
In the inspection TFT 3 provided in the source bus line 2, the gate electrode 31 is connected to the source bus line inspection control signal line 5b, the source electrode 35 is connected to the source bus line 2, and the drain electrode 34 is connected to the inspection source signal. Each of the input line (red) 2a, the inspection source signal input line (green) 2b, and the inspection source signal input line (blue) 2c is connected via a contact hole (not shown).
[0068]
In this embodiment, the test input terminal 21 is used as a generic name of the test input terminal GO, the test input terminal GE, the test input terminal R, the test input terminal G, the test input terminal B, the test input terminal SW, and the test input terminal C. I have. Each input terminal of the inspection input terminal 21 constitutes a titanium film 35b constituting the source bus line 2 and a pixel electrode 11a on the titanium nitride film 31a / aluminum film 31b / titanium film 31c constituting the gate bus line 1. It is formed from a laminated film on which an ITO film is formed, and is disposed corresponding to an inspection prober used in an inspection apparatus for the strip substrate 20, and its terminal size is about 0.8 mm square. As described above, since the test input terminal 21 is provided in the non-display area of the adjacent liquid crystal display panel 100, the test input terminal 21 and the test input terminal can be tested by dividing the liquid crystal display panel 100 after the test. Since the liquid crystal display panel 100 to which the signal is input is separated, the progress of corrosion from the test input terminal 21 into the liquid crystal display panel 100 is suppressed. Further, when each input terminal of the test input terminal 21 is formed of a material which is easily corroded by aluminum and / or molybdenum, the progress of corrosion from the test input terminal 21 can be more effectively suppressed.
[0069]
Similarly, in the non-display area on the outer side of the active matrix substrate section 40, a gate driver IC chip mounting area 16 is provided on the lower side of the liquid crystal display panel 100 as an area for mounting components, and a source driver IC chip mounting area 17 is provided. The flexible printed wiring board mounting portion 22 is provided on the right side portion of the liquid crystal display panel 100 on the display region 19 side on the right side portion of the liquid crystal display panel 100 on the side of the vertical dividing line 6b. In addition, as a wiring for countermeasures against static electricity, a short-circuit wiring 23 is parallel to each other along the arrangement direction of the liquid crystal display panel 100 in a region outside the inspection input terminal 21 and the gate driver IC chip mounting region 16 on the lower side of the strip substrate 20. Is provided so as to extend.
[0070]
The gate driver IC chip mounting area 16 and the source driver IC chip mounting area 17 are areas where the gate driver IC chip and the source driver IC chip are mounted, respectively. The gate bus line 1 is connected to the gate driver IC chip, and the source bus line 2 is connected to the source driver IC chip.
[0071]
The periphery of the right side of the flexible printed wiring board mounting portion 22 coincides with the vertical dividing line 6b which is a portion to be divided, and a terminal for inputting power into the liquid crystal display panel 100 (hereinafter, referred to as an “FPC terminal”) ) 14 are provided. The FPC terminal 14 is formed by forming a titanium film 35b constituting the source bus line 2 and an ITO film constituting the pixel electrode 11a on the titanium nitride film 31a / aluminum film 31b / titanium film 31c constituting the gate bus line 1. It is formed from a laminated film formed.
[0072]
In addition to the FPC terminals 14, the above-described inspection gate signal input lines (1a, 1b), inspection source signal input lines (2a, 2b, 2c), and control signal The inspection wiring of the line 5 and the inspection common electrode wiring 9 is disposed so as to cross the flexible printed wiring board mounting portion 22. Therefore, the inspection input terminal and the liquid crystal display panel 100 are separated by the division after the inspection of the liquid crystal display panel 100, and the divided end surface of each inspection wiring is exposed. However, since the divided end face of the inspection wiring coincides with the end face of the FPC terminal 14, the divided end face of the inspection wiring is simultaneously formed by the application of the resin 18 on the end face of the FPC terminal 14, as shown in FIG. Coated. Thereby, corrosion of the divided end surface of the inspection wiring is also suppressed.
[0073]
The short-circuit wiring 23 is formed of the same material in the same layer as the gate bus line 1 and is formed of the same material, and each active matrix substrate of the adjacent strip substrate 20 (the liquid crystal display panel 100) via the horizontal dividing line 6a existing in the state of the mother substrate 50. The plurality of gate bus lines 1 on the unit 40 are all connected.
[0074]
Incidentally, the active matrix substrate 40 constituting the liquid crystal display panel 100 is manufactured by repeating a process of forming various thin films on the glass substrate 30 and patterning the thin films by etching. In the manufacturing process of the liquid crystal panel including the active matrix substrate 40, since the substrate material is an insulator such as glass, friction between the substrate handling and mechanical operation with air, rubbing of the substrate surface in a rubbing process, etc. Static electricity is generated by friction between each other. Functional parts such as the TFT 10 formed of the laminated thin film are easily broken by the static electricity. Therefore, all of the gate bus lines 1 formed of the lowermost film among the conductive films on the active matrix substrate 40 are short-circuited using the inspection wiring, and the inspection wiring is formed even when the substrate is charged. Means are commonly used to release static electricity to the outside through the device and prevent a potential difference from occurring between wirings.
[0075]
However, in the mother board 50 according to the embodiment of the present invention, since the inspection wiring and the gate bus line 1 are connected via the inspection TFT 3, the short-circuit wiring 23 for the countermeasure against static electricity is provided separately from the inspection wiring. Is provided.
[0076]
The auxiliary capacitance electrode 12 is formed in the same layer and the same material as the gate bus line 1 and is connected to the drain electrode 34 of the TFT 10 to constitute an auxiliary capacitance. Normally, if the pixel capacitance holding the charge is only the liquid crystal capacitance, the operation of the image is often insufficient or the influence of the parasitic capacitance is often caused. The operation is more complete.
[0077]
The opposing substrate portion has a common electrode 11b made of ITO or the like provided on almost the entire display region 19 and a color filter layer.
[0078]
The liquid crystal layer is made of a nematic liquid crystal material having electro-optical characteristics.
[0079]
In the liquid crystal display panel 100, one pixel is formed for each pixel electrode 11a, and when a gate signal is sent from the gate bus line 1 to turn on the TFT 10 in each pixel, the source bus line 2, a predetermined source signal is sent to write electric charges to the pixel electrode 11a, and a voltage applied to a liquid crystal capacitor formed between the pixel electrode 11a and the common electrode 11b is controlled. The image display is configured by adjusting the light transmittance by changing the orientation state of the molecules.
[0080]
Next, a method for manufacturing the strip substrate 20 according to the first embodiment of the present invention will be described.
[0081]
First, a description will be given of a method of manufacturing the mother substrate 50 which is a preceding stage. The following manufacturing method is a representative example, and the present invention is not limited to this.
[0082]
<Active matrix substrate mother substrate manufacturing process>
The manufacturing process of the active matrix substrate mother substrate will be described based on a schematic cross-sectional view around the TFT 10 shown in FIG.
[0083]
First, a titanium film 31c, an aluminum film (about 2,000 mm thick) 31b, and a titanium nitride film 31a are sequentially formed on a glass substrate 30 made of non-alkali glass by a sputtering method. After that, a pattern is formed by a photolithography technique (hereinafter, referred to as “PEP technique”), and the gate bus line 1, the gate electrode 31, and the auxiliary capacitance electrode 12 are not displayed in the display area 19. In the area, a test source signal input line (red) 2a, a test source signal input line (green) 2b, a test source signal input line (blue) 2c, a source bus line test control signal line 5b, and a short-circuit line 23 are formed. I do.
[0084]
Next, the gate bus line 1, the gate electrode 31, the auxiliary capacitance electrode 12, the test source signal input line (red) 2a, the test source signal input line (green) 2b, the test source signal input line (blue) 2c, the source On the control signal line 5b for bus line inspection and the short-circuit wiring 23, a gate insulating film (thickness of about 4000 °) 32 made of a silicon nitride film is formed by a plasma CVD (Chemical Vapor Deposition) method.
[0085]
Next, an intrinsic amorphous silicon layer (about 1500 ° thick) 33a and an n + amorphous silicon layer (about 400 ° thick) doped with phosphorus 33b are successively formed on the gate insulating film 32 by a plasma CVD method. Then, a semiconductor film 33 composed of an intrinsic amorphous silicon layer 33a and an n + amorphous silicon layer (thickness of about 400 °) 33b is formed by forming an island-shaped pattern by PEP technology.
[0086]
Next, on the gate insulating film 32 on which the semiconductor film 33 is formed, the titanium films 34b and 35b and the aluminum films (thickness of about 1000 °) 34a and 35a are successively formed by a sputtering method, and are stacked to have a thickness of about 1500 °. After the film is formed, the pattern is formed by the PEP technique, and the source bus line 22, the source electrode 35 and the drain electrode 34 are formed in the display area 19, and the gate signal input line for inspection (odd number) 1a and the gate for inspection are formed in the non-display area. The signal input line (even number) 1b, the control signal line 5a for gate bus line inspection, the common electrode wiring 9 for inspection, and the inspection input terminal 21 are formed.
[0087]
Next, the n + amorphous silicon layer 33b formed in an island shape is etched by a dry etcher to form a channel portion of the TFT.
[0088]
Next, the source bus line 22, the source electrode 35, the drain electrode 34, the inspection gate signal input line (odd number) 1a, the inspection gate signal input line (even number) 1b, the gate bus line inspection control signal line 5a, and the inspection common signal On the electrode wiring 9, a first interlayer insulating film (thickness of about 2000 °) made of a silicon nitride film is formed by a plasma CVD method.
[0089]
Next, a photosensitive acrylic resin (about 4 μm thick) is applied on the first interlayer insulating film 36 by a printing method. After that, the second interlayer insulating film 37 is formed by pattern formation by the PEP technique.
[0090]
Next, after forming an ITO film (thickness of about 1000 °) on the second interlayer insulating film 37 by a sputtering method, a pattern is formed by the PEP technique to form the pixel electrode 11a.
[0091]
Next, a polyimide resin is applied to the entire surface of the substrate by a printing method so as to cover the pixel electrodes 11a. Thereafter, an alignment process is performed on the surface by a rubbing method to form an alignment film.
[0092]
Note that the inspection TFT 3 is formed simultaneously with the TFT 10 in the display area 19.
[0093]
As described above, the active matrix substrate mother substrate is manufactured.
[0094]
<Counter substrate mother substrate manufacturing process>
First, a color filter layer (about 3 μm in thickness) is formed on a glass substrate 30 made of non-alkali glass using a pigment dispersion method or the like.
[0095]
Next, an acrylic resin or the like is applied on the color filter layer by a printing method to form an overcoat film (about 2 μm in thickness).
[0096]
Next, after forming an ITO film (thickness of about 1000 °) on the overcoat film by a sputtering method, a pattern is formed by the PEP technique to form the common electrode 11b.
[0097]
Next, a polyimide resin is applied to the entire surface of the substrate by a printing method so as to cover the common electrode 11b, and an alignment process is performed on the surface by a rubbing method to form an alignment film.
[0098]
As described above, the opposing substrate mother substrate is manufactured.
[0099]
<Mother substrate manufacturing process>
First, a sealing material made of a thermosetting epoxy resin or the like is applied to the outer peripheral portion of the display region 19 of each liquid crystal display panel portion 100 on the mother substrate of the active matrix substrate by a printing method to form a frame-shaped pattern lacking a liquid crystal injection port. Apply to.
[0100]
Next, spherical plastic beads having a diameter corresponding to the thickness of the liquid crystal layer and made of a polymer such as polystyrene are sprayed on the mother substrate of the opposing substrate.
[0101]
Next, the active matrix substrate mother substrate and the opposing substrate mother substrate are bonded with high accuracy so that the respective components are combined.
[0102]
As described above, the mother board 50 is manufactured. In addition, all the gate bus lines 1 of the active matrix substrate unit 40 of the liquid crystal display panel unit serving as the liquid crystal display panel 100 constituting the mother substrate 50 are connected to the short-circuit lines 23 extending along the horizontal dividing lines 6a. Therefore, the static electricity charged on the substrate is released to the outside via the short wiring 23. This prevents functional parts such as the TFT 10 in the liquid crystal display panel from being destroyed by static electricity.
[0103]
Next, a method for manufacturing the strip substrate 20 according to the first embodiment of the present invention will be described.
[0104]
First, the mother board 50 is set in a cutting device, and cut along the horizontal cutting line 6a. At this time, the short-circuit wiring 23 and the gate bus line 1, which have been connected for the purpose of preventing static electricity, are cut off, and the short-circuit wiring 23 does not act on the liquid crystal display panel 100 via the gate bus line 1.
[0105]
Next, only the opposing substrate side of the mother substrate 50 is divided along the horizontal dividing line 6a 'to form a region where the test input terminals 21 are provided and the gate driver IC chip mounting region 16.
[0106]
Next, a liquid crystal material is injected from the liquid crystal injection port between the active matrix substrate section 40 and the opposing substrate section by a decompression method. Thereafter, a UV curable resin is applied to the liquid crystal injection port, the UV curable resin is cured by UV irradiation, and the liquid crystal injection port is sealed.
[0107]
As described above, the strip substrate 20 of the present invention is manufactured.
[0108]
Next, a method of inspecting the strip substrate 20 according to the first embodiment of the present invention will be described.
[0109]
The strip substrate 20 is set on the inspection device, and the inspection prober of the inspection device is brought into contact with the inspection input terminal 21 of the liquid crystal display panel 100 adjacent to each liquid crystal display panel 100 of the strip substrate 20, and the inspection input terminal 21 is connected from the inspection prober. An inspection signal is supplied to each of the liquid crystal display panels 100 via the LCD panel 100 for inspection. The inspection signal is input according to the inspection method (inspection patterns I, II, and III) described in the related art.
[0110]
Specifically, using the test pattern I shown in FIG. 6, a control test signal is input via the test input terminal SW, and the test TFT 3 is turned on. While inputting a common electrode inspection signal via the inspection input terminal C, a gate inspection signal is input via the inspection input terminal GO and the inspection input terminal GE, and the display TFT 10 is turned on. Further, a source test signal is input via a test input terminal R, a test input terminal G, and a test input terminal B. Thereby, for example, as shown in FIG. 9B, if the wiring is broken between the drain electrode 34 such as the defective portion 51 and the pixel electrode 11a in the pixel of the liquid crystal display panel, the pixel electrode A predetermined charge cannot be written to 11a, and the pixel is turned off (bright point). If a leak occurs between the gate bus line 1 and the pixel electrode 11a as in the defective portion 52, the charge from the gate bus line 1 is always written to the pixel electrode 11a, and the pixel is turned on (black dot). ). As a result, it is possible to detect a display defect of a pixel due to a disconnection or a leak of the gate bus line 1 and the source bus line 2.
[0111]
Further, a control test signal is input via the test input terminal SW using the test pattern II shown in FIG. 7, and the test TFT 3 is turned on. While the common electrode inspection signal is input through the inspection input terminal C, the gate inspection signal a is input through the inspection input terminal GO, and the gate inspection signal b is input through the inspection input terminal GE. 1 and the display TFTs 10 connected to the even-numbered gate bus lines 1 are turned on alternately. Further, a source test signal is input via a test input terminal R, a test input terminal G, and a test input terminal B. Thus, a leak between the adjacent gate bus lines 1 can be detected.
[0112]
Similarly, a control test signal is input via the test input terminal SW using the test pattern II shown in FIG. 8, and the test TFT 3 is turned on. While inputting the common electrode inspection signal through the inspection input terminal C, the gate inspection signal is input through the inspection input terminal GO and the inspection input terminal GE, and all the display TFTs 10 are turned on. Further, for example, a source test signal a is input via a test input terminal R input to the source bus line 2 for red display, a test input terminal G for input to the source bus line 2 for green display, and a source bus line for blue display. 2, a source test signal b is input via a test input terminal B. At this time, if there is a leak between the red source bus line 2 and another adjacent source bus line 2, the leaking source bus line 2 will be displayed in a different red color. Also, when the display of green and the display of blue are performed in the same manner as the procedure of the above-described red display, a leak between the adjacent source bus lines 2 can be detected.
[0113]
Next, a method for manufacturing the liquid crystal display panel 100 according to the first embodiment of the present invention will be described.
[0114]
First, the strip substrate 20 is set in a cutting device, and cut along the vertical cutting line 6b.
[0115]
Next, only the opposing substrate side of the strip substrate 20 is divided along the horizontal dividing line 6b 'to form the flexible printed wiring board mounting portion 22 and the source driver IC chip mounting region 17.
[0116]
Next, the FPC 15 is attached to the surface of the FPC terminal 14 on the flexible printed wiring board mounting portion 22, and a UV curable resin is applied to the end surface 14a of the FPC terminal 14. Further, in order to prevent corrosion of the divided end surface of the short-circuit wiring 23, a UV curing resin is applied to the end surface of the liquid crystal display panel 100 corresponding to the upper side of the strip substrate 20. After that, the UV curable resin is cured by UV irradiation to form the resin layer 18.
[0117]
As described above, the liquid crystal display panel 100 of the present invention is manufactured.
[0118]
As described above, the inspection input terminal 21 and the liquid crystal display panel to which the inspection signal is input from the inspection input terminal 21 due to the division along the vertical division line 6b which is the part to be divided after the inspection of the liquid crystal display panel 100. 100, the progress of corrosion from the test input terminal 21 into the liquid crystal display panel 100 is suppressed. Further, each of the inspection wirings of the inspection gate signal input lines (1a, 1b), the inspection source signal input lines (2a, 2b, 2c), the inspection control signal line 5, and the inspection common electrode wiring 9 is a flexible print. Since it is arranged together with the FPC terminal 14 in the wiring board mounting portion 22, the end surface of each inspection wiring generated by the division along the vertical dividing line 6b is also formed by the resin layer 18 on the end surface 14a of the FPC terminal 14. Because of the coating, the corrosion of the end face caused by the division of each inspection wiring is also suppressed.
[0119]
(Embodiment 2)
Hereinafter, a liquid crystal display panel forming plate and a liquid crystal display panel according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 3 schematically shows a liquid crystal display panel forming plate (strip substrate) 20 according to the second embodiment of the present invention, and corresponds to FIG. 1 in the first embodiment.
[0120]
In each of the liquid crystal display panels 100 of the strip substrate 20, the inspection gate signal input lines (1a, 1b) and the inspection source signal input lines that traverse the flexible printed wiring board mounting portion 22 are attached to the flexible printed wiring board mounting portion 22. (2a, 2b, 2c), an in-panel inspection input terminal 24 is provided corresponding to each of the inspection control signal line 5 and the inspection common electrode line 9. The in-panel inspection input terminal 24 is preferably provided corresponding to an inspection prober used in the inspection apparatus. Therefore, even after the liquid crystal display panel 100 is inspected and divided along the vertical dividing line 6b, the individual liquid crystal display panel 100 can be inspected again via the in-panel inspection input terminal 24. As a result, the liquid crystal display panel 100 which has become defective due to the defect of the inspection wiring portion 25 outside the panel between the in-panel inspection input terminal 24 and the inspection input terminal 21 on the adjacent liquid crystal display panel 100 is re-inspected. If it passes, a non-defective product can be obtained, and the non-defective product ratio of the liquid crystal display panel 100 can be improved. Furthermore, since the FPC 15 is attached to the surface of the in-panel inspection input terminal 24 after the inspection of the liquid crystal display panel 100, corrosion from the in-panel inspection input terminal 24 is also suppressed. Other configurations are the same as those of the first embodiment, are denoted by the same reference numerals, and detailed description is omitted.
[0121]
(Embodiment 3)
Hereinafter, a liquid crystal display panel forming plate and a liquid crystal display panel according to Embodiment 3 of the present invention will be described with reference to FIG. FIG. 4 schematically shows a liquid crystal display panel forming plate (strip substrate) 20 according to Embodiment 3 of the present invention, and corresponds to FIG. 1 in Embodiment 1 and FIG. 3 in Embodiment 2.
[0122]
In each of the liquid crystal display panels 100 of the strip substrate 20, instead of providing the test input terminal 21 at the end of the test wiring of each liquid crystal display panel 100 as in the first embodiment, the test wiring is The lower side portion is individually connected to a plurality of common inspection wirings 27 extending in parallel with each other along the short wiring 23 in a region between the gate driver IC chip mounting area 16 and the short wiring 23. Further, a common test input terminal 26 at the end of the common test wiring 27 is provided in a region which does not belong to the liquid crystal display panel 100 in a lower left portion of the strip substrate 20, that is, in a discarded substrate portion. Accordingly, when the liquid crystal display panel 100 is inspected on the strip substrate 20, if an inspection signal is input to the common inspection input terminal 26, the inspection of all the liquid crystal display panels 100 connected thereto is collectively performed. The inspection efficiency of the liquid crystal display panel 100 can be improved. Further, since the common inspection input terminal 26 is provided on the discarded substrate portion of the strip substrate 20, the common inspection input terminal 26 and the common inspection input terminal 26 are divided by the vertical division line 6b after the inspection of the liquid crystal display panel 100. Since the liquid crystal display panel 100 to which the test signal is input from the test input terminal 26 is separated, the progress of corrosion from the common test input terminal 26 into the liquid crystal display panel 100 is suppressed.
[0123]
(Embodiment 4)
Hereinafter, a liquid crystal display panel forming plate and a liquid crystal display panel according to Embodiment 4 of the present invention will be described with reference to FIG. FIG. 5 schematically shows a liquid crystal display panel forming plate (strip substrate) 20 according to the fourth embodiment of the present invention, which is shown in FIG. 1 in the first embodiment, FIG. 3 in the second embodiment, and FIG. It corresponds to FIG.
[0124]
In each of the liquid crystal display panels 100 of the strip substrate 20, in addition to the configuration of the third embodiment, the inspection gate signal input lines (1a, 1b), an in-panel inspection input terminal 24 is provided corresponding to each of the inspection source signal input lines (2a, 2b, 2c), the inspection control signal line 5, and the inspection common electrode wiring 9. Therefore, when inspecting the liquid crystal display panel 100 on the strip substrate 20, an inspection signal is input to the common inspection input terminal 26, and all the liquid crystal display panels 100 connected thereto are inspected at the same time. Only the liquid crystal display panel 100 determined to be defective after the disconnection along the disconnection lines 6b and 6b 'can be re-inspected via the in-panel inspection input terminal 24. Thereby, the inspection efficiency and the non-defective rate of the liquid crystal display panel 100 can be simultaneously improved.
[0125]
Note that the present invention is not limited to this embodiment, and may have another configuration.
[0126]
【The invention's effect】
As described above, according to the present invention, the test input terminal is provided on the adjacent display panel, and the test panel is divided by the test panel after the test, and the test panel receives the test signal from the test input terminal and the test input terminal. Are separated from each other, so that the progress of corrosion from the inspection input terminal is suppressed.
[Brief description of the drawings]
FIG. 1 is a schematic plan view schematically showing a strip substrate 20 for a liquid crystal display element according to Embodiment 1 of the present invention.
FIG. 2 is a schematic cross-sectional view schematically showing the periphery of a TFT 10, and corresponds to a cross section taken along a line AB in FIG. 9A.
FIG. 3 is a schematic plan view schematically showing a strip substrate 20 according to Embodiment 2 of the present invention.
FIG. 4 is a schematic plan view schematically showing a strip substrate 20 according to Embodiment 3 of the present invention.
FIG. 5 is a schematic plan view schematically showing a strip substrate 20 according to a fourth embodiment of the present invention.
6 is a schematic diagram showing a timing chart of an inspection signal (inspection pattern I) for inspecting the liquid crystal display panel 100 of the strip substrate 20. FIG.
FIG. 7 is a schematic diagram showing a timing chart of an inspection signal (inspection pattern II) for inspecting the liquid crystal display panel 100 of the strip substrate 20.
8 is a schematic diagram showing a timing chart of an inspection signal (inspection pattern III) for inspecting the liquid crystal display panel 100 of the strip substrate 20. FIG.
9A is a schematic plan view schematically showing a pixel area of an active matrix substrate 40 of the liquid crystal display panel 100, and FIG. 9B is a schematic plan view of a pixel area having defective portions 51 and 52. .
FIG. 10 is a schematic plan view schematically showing a conventional liquid crystal display panel on which no inspection TFT 3 is mounted.
FIG. 11 is a schematic plan view schematically showing a liquid crystal display panel on which a conventional inspection TFT 3 is mounted.
FIG. 12 is a schematic plan view schematically showing a relationship among a mother substrate 50, a strip substrate 20, and a liquid crystal display panel 100.
FIG. 13 is a schematic plan view schematically showing a strip substrate 20 of a liquid crystal display panel 100 on which a conventional inspection TFT 3 is mounted.
FIG. 14A is a schematic plan view showing a liquid crystal display panel 100 and an FPC area 22 thereof. 3B is an enlarged schematic plan view of the FPC region 22 and a cross-sectional view thereof.
FIG. 15 is a schematic plan view schematically showing a strip substrate 20 when the test input terminals 7 and 8 of the liquid crystal display panel 100 are provided in the FPC area 22 of the liquid crystal display panel 100.
FIG. 16A is a schematic plan view schematically showing a positional relationship between a gate bus line 1, an inspection gate signal input line (odd number) 1a, and an inspection gate signal input line (even number) 1b. (B) is a schematic plan view schematically showing a positional relationship between the gate bus line 1 and the integrated inspection gate signal input line 1t.
FIG. 17 schematically shows a strip substrate 20 in which an integrated inspection gate signal input line 1t is provided instead of the inspection gate signal input line (odd number) 1a and the inspection gate signal input line (even number) 1b. It is a plane schematic diagram.
[Explanation of symbols]
1 gate bus line
1 'Gate bus line of adjacent strip substrate
1a Inspection gate signal input line (odd number)
1b Inspection gate signal input line (even number)
1t Inspection gate signal input line (integrated)
2 Source bus line
2a Source signal input line for inspection (red)
2b Source signal input line for inspection (green)
2c Source signal input line for inspection (blue)
3 TFT for inspection
5 Control signal line for inspection
5a Control signal line for gate bus line inspection
5b Control signal line for source bus line inspection
6-minute break
6a Horizontal disconnection
6a 'Horizontal disconnection (counter substrate)
6b Vertical disconnection
6b 'Vertical disconnection (counter substrate)
7 Test input terminals (test input terminals GE, GO and SW)
8 Test input terminals (Test input terminals R, G, B and C)
9 Common electrode wiring for inspection
10 TFT (for display)
11a Pixel electrode
11b Common electrode
12 Auxiliary capacitance electrode
14 FPC terminal
14a End face of FPC terminal
15 FPC
16 Gate driver IC chip mounting area
17 Source driver IC chip mounting area
18 resin layer (resin)
19 Display area
20 Strip substrate (display panel forming plate)
21 Inspection input terminal
22 Flexible printed wiring board mounting part
23 short circuit wiring
24 Inspection input terminal in panel
25 Inspection wiring outside panel
26 common test input terminal
27 Wiring for common inspection
30 glass substrate
31 Gate electrode
31a Titanium nitride film
31b Aluminum film
31c titanium film
32 Interlayer insulation film
33 Semiconductor film
33a Intrinsic amorphous silicon layer
33b n + amorphous silicon layer
34 drain electrode
35 Source electrode
34a, 35a Aluminum film
34b, 35b Titanium film
36 First interlayer insulating film
37 Second interlayer insulating film
39 Contact hole
40 Active matrix substrate
50 Mother board
51 defective part
52 defective part
100 Liquid crystal display panel (display panel)

Claims (6)

A display panel forming plate in which a plurality of display panels each having a display wiring and an inspection wiring connected to the display wiring are arranged in a line and integrated,
The inspection wiring of each of the display panels crosses a portion to be divided between the display panel and an adjacent display panel adjacent thereto, and an inspection input terminal is provided at an end thereof. A display panel forming plate comprising a flexible printed wiring board mounting portion of the display panel. The display panel forming plate according to claim 1,
A display panel forming board, wherein an in-panel inspection input terminal connected to the inspection wiring of the display panel is provided in the flexible printed wiring board mounting portion of the display panel. The display panel forming plate according to claim 1,
A display panel forming plate, comprising: a common inspection wiring provided to extend along an arrangement direction of the plurality of display panels and connected to respective inspection wirings of the plurality of liquid crystal panels. The display panel forming plate according to claim 1,
A display panel forming plate, wherein the inspection input terminal is formed of aluminum and / or molybdenum. The display panel forming plate according to claim 1,
A display panel forming plate, wherein the display panel is a liquid crystal display panel. A display panel, wherein the display panel forming plate according to any one of claims 1 to 5 is divided along a portion to be divided.

Images