KR101380228B1 - Array substrate for Chip on glass type liquid crystal display device - Google Patents

Abstract

According to an exemplary embodiment of the present invention, a display area, a first non-display area having a gate pad formed therein, a second non-display area having a data pad formed therebetween, and a display area interposed therebetween are disposed at a portion symmetrical with the second non-display area. A substrate on which a third non-display area is defined; A plurality of gate wirings and data wirings formed to define a plurality of pixel regions crossing each other in the display region; A thin film transistor which is a switching element provided in each of the plurality of pixel areas; Pixel electrodes connected to one electrode of the thin film transistor in each of the plurality of pixel regions; A plurality of gate driver integrated circuits in a chip form spaced apart from each other in the first non-display area; A plurality of data driver integrated circuits in a chip form spaced apart from each other in the second non-display area; A plurality of gate connection wirings connected to one of the plurality of gate driving integrated circuits in the first display area and simultaneously connected to the gate wirings; A plurality of data connection wires connected to one of the plurality of data driving integrated circuits in the second display area and simultaneously connected to the data wires; A COG type liquid crystal display including a semiconductor wiring made of the same material on the same layer as the active layer, which is one component constituting the thin film transistor and intersects with the plurality of all data connection wirings in the second non-display area An array substrate for a COG type liquid crystal display device including an array substrate for an apparatus is provided.

Description

[0001] The present invention relates to an array substrate for a liquid crystal display (LCD)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an array substrate for a COG (chip on glass) type liquid crystal display device.

In recent years, as the information society has developed rapidly, there has been a need for a display device having excellent characteristics such as thinness, light weight, and low power consumption. Accordingly, a flat panel display has been actively developed, In particular, liquid crystal displays (LCDs) are superior in resolution, color display, and image quality, and are actively applied to monitors of notebook computers and desktop computers.

In general, in a liquid crystal display device, two substrates on which electrodes are formed are arranged so that the surfaces on which the two electrodes are formed face each other, a liquid crystal material is injected between the two substrates, and then an electric field And moving the liquid crystal molecules, thereby expressing the image by the transmittance of light depending on the liquid crystal molecules.

1, which is an exploded perspective view of a general liquid crystal display device, a liquid crystal display device includes a liquid crystal layer 30 sandwiched between an array substrate 10 and a color filter 30, The lower array substrate 10 has a plurality of gate wirings 14 arranged longitudinally and laterally crosswise on the upper surface of the transparent substrate 12 to define a plurality of pixel regions P, And a data line 16. A thin film transistor Tr is provided at an intersection of these two lines 14 and 16 and is connected in a one-to-one correspondence with the pixel electrode 18 provided in each pixel region P.

The upper portion of the color filter substrate 20 facing the array substrate 10 is electrically connected to the rear surface of the transparent substrate 22 through the gate wiring 14, the data wiring 16, the thin film transistor T, Shaped black matrix 25 for framing each pixel region P so as to cover the respective pixel regions P in the pixel region P. The red (R), green A color filter layer 26 including color filter patterns 26a, 26b and 26c of blue (G) and blue (B) colors is formed on the front surface of the color filter layer 26, A common electrode 28 is provided.

Although not shown in the drawings, the two substrates 10 and 20 are sealed with a sealant or the like along their edges in order to prevent leakage of the liquid crystal layer 30 interposed therebetween. 10 and 20 and the liquid crystal layer 30 are provided with an upper and a lower orientation film for giving reliability in the molecular alignment direction of the liquid crystal and at least one outer surface of each of the substrates 10 and 20 is provided with a polarizing plate have.

On the outer side of the array substrate 10, a back-light is provided to supply light. An on / off signal of the thin film transistor T is applied to the gate wiring 14 When image signals of the data lines 16 are transferred to the pixel electrodes 18 of the selected pixel region P sequentially by scanning, the liquid crystal molecules between them are driven by the vertical electric field between them, and the light transmittance Various images can be displayed with change

In the liquid crystal display device having such a structure, the array substrate, the color filter substrate, and the liquid crystal layer interposed between the two substrates are defined by a liquid crystal panel, and a driver for driving the liquid crystal panel is formed at the outer periphery of the liquid crystal panel. The driving unit includes a printed circuit board (PCB) on which components for generating various control signals, data signals and the like are mounted, a driving integrated circuit (IC) connected to the liquid crystal panel and the printed circuit board, A chip on glass (COG) method, a tape carrier package (TCP) method, and a liquid crystal panel according to a method of packaging a driving integrated circuit on the liquid crystal panel. And a chip on film (COF) method.

The double COG method is widely applied to liquid crystal display devices in recent years because it has a simpler structure than the TCP method and the COF method and can increase the ratio of the liquid crystal panel in the liquid crystal display device.

FIG. 2 is a schematic plan view of a conventional COG-type liquid crystal display device array substrate, and FIG. 3 is a plan view showing an enlarged view of a region A in FIG.

As shown in the figure, the conventional array substrate 51 for a COG type liquid crystal display comprises a display area AA for displaying an image, first, second and third non-display areas (NA1, NA2, NA3) are defined. In the first non-display area NA1, a plurality of gate driving integrated circuits 67 which apply gate signal voltages to a plurality of gate lines 63 formed in the display area AA are positioned. In the non-display area NA2, a plurality of data driver integrated circuits 69a and 69b are provided to apply data signal voltages to the plurality of data lines 65 formed in the display area AA.

A plurality of data pads (not shown) are formed in the second non-display area NA2 between the data driving integrated circuits 69a and 69b, and branched from one end of each of the data pads 81 to each other. A plurality of data connection wires 66 are formed to extend to AA, and the plurality of data connection wires 66 are connected to the plurality of data wires 65 formed in the display area AA. In this case, in the data connection line 66, an electrostatic compensation circuit C1 including a plurality of thin film transistors (not shown) is configured to prevent damage of the thin film transistors (not shown) in the display area AA due to static electricity. have.

In the conventional COG type liquid crystal display 51 array substrate having the above-described configuration, the display area AA includes the partial areas A1 and A2 as many as the number of the data driving integrated circuits 69a and 69b. It can be seen that it is divided into, and by changing the amount of carriers charged internally between these partial areas (A1, A2) is not equipotential, even if the same signal voltage is applied, the brightness of the image is reduced, and the display quality is reduced have.

The reason why the subregions A1 and A2 connected to the different data driving integrated circuits 69a and 69b have different luminance is that each of the subregions A1 and A2 connected to the same data driving integrated circuit 69a and 69b has a different luminance. In the pixel region P, the data line 65 defining these pixel regions P is finally connected to the data driving integrated circuits 69a and 69b to form an equipotential therein. However, since the partial regions A1 and A2 connected to the different driving integrated circuits are not electrically connected to each other, the amount of carriers trapped in the protective layer made of an organic or inorganic insulating material by a plasma process or the like is changed. Even if the threshold voltage shift of the transistor is induced or the same data signal voltage is applied, the transistor does not have the same luminance, and the display product is deteriorated due to the luminance difference between the partial regions A1 and A2.

In the case of a general array substrate in which an integrated driving circuit is not formed on a substrate, all data wires are electrically connected to each other by a shorting bar at the outermost portion of the non-display region of the substrate, so that all pixel electrodes of the display region have an equipotential. Since the shorting bar is cut at the final stage of the manufacturing process in the state, all the pixel electrodes in the display area are equipotential so that the above-described degradation of the display product does not occur. However, in the case of the COG type, the shorting bar may be formed at the outermost part of the non-display area. Therefore, it is impossible to achieve the equipotential for all the pixel areas, thereby causing a problem of deterioration of the display product due to the luminance difference.

SUMMARY OF THE INVENTION An object of the present invention is to provide an array substrate for a COG type liquid crystal display device which prevents display quality deterioration due to a luminance difference between a partial region connected to a data driving integrated circuit and a different data driving integrated circuit.

An array substrate for a COG type liquid crystal display device according to an embodiment of the present invention includes a display area, a first non-display area having a gate pad formed therebetween, and a second non-display area having a data pad formed therebetween. A substrate on which a third non-display area is defined, the third non-display area being positioned at a portion symmetrical with the second non-display area; A plurality of gate wirings and data wirings formed to define a plurality of pixel regions crossing each other in the display region; A thin film transistor which is a switching element provided in each of the plurality of pixel areas; Pixel electrodes connected to one electrode of the thin film transistor in each of the plurality of pixel regions; A plurality of gate driver integrated circuits in a chip form spaced apart from each other in the first non-display area; A plurality of data driver integrated circuits in a chip form spaced apart from each other in the second non-display area; A plurality of gate connection wirings connected to one of the plurality of gate driving integrated circuits in the first display area and simultaneously connected to the gate wirings; A plurality of data connection wires connected to one of the plurality of data driving integrated circuits in the second display area and simultaneously connected to the data wires; The second non-display area includes semiconductor wiring made of the same material on the same layer as the active layer, which is one component that intersects and contacts the plurality of data connection wirings and forms the thin film transistor.

In another embodiment, an array substrate for a COG type liquid crystal display device includes a display area, a first non-display area having a gate pad formed thereon, a second non-display area having a data pad formed therein, and the display area. A substrate on which a third non-display area defined between the second non-display area and a portion which is symmetrical to the second non-display area is defined; A plurality of gate wirings and data wirings formed to define a plurality of pixel regions crossing each other in the display region; A thin film transistor which is a switching element provided in each of the plurality of pixel areas; Pixel electrodes connected to one electrode of the thin film transistor in each of the plurality of pixel regions; A plurality of gate driver integrated circuits in a chip form spaced apart from each other in the first non-display area; A plurality of data driver integrated circuits in a chip form spaced apart from each other in the second non-display area; A plurality of gate connection wirings connected to one of the plurality of gate driving integrated circuits in the first display area and simultaneously connected to the gate wirings; A plurality of data connection wires connected to one of the plurality of data driving integrated circuits in the second display area and simultaneously connected to the data wires; The third non-display area includes a semiconductor wiring made of the same material on the same layer as the active layer, which is one component of the thin film transistor and intersects one end of the plurality of data lines.

In this case, a plurality of metal patterns spaced apart from each other in the form of branches from the plurality of data wires or the plurality of data connection wires may be formed on the semiconductor wire, and the thin film transistor may be disposed between the semiconductor wires and the plurality of metal patterns. Among the components, the impurity amorphous silicon pattern is formed of the same material forming the ohmic contact layer.

In the plurality of spaced metal patterns, the spaced area corresponds to an area between each data line or an area between each data connection line.

The thin film transistor is characterized in that the gate electrode, the gate insulating film, the active layer, the ohmic contact layer, and the source and drain electrodes are sequentially stacked.

The array substrate for a COG type liquid crystal display device according to the present invention includes a carrier movement means for enabling carrier movement in a portion where a data connection wiring of a non-display region is formed, and a portion in a display region connected to different data driving integrated circuits. By making the equipotentials between the regions suppress the occurrence of the luminance difference between these partial regions, there is an effect of preventing the display quality deterioration due to the partial luminance difference.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the drawings.

4 is a schematic plan view of an array substrate for a COG type liquid crystal display according to an exemplary embodiment of the present invention, FIG. 5 is an enlarged plan view of region B of FIG. 4, and FIG. 6 is a cut line VI-VI of FIG. 5. Sectional drawing of the part cut along the side.

As shown, the array substrate 110 for a COG type liquid crystal display device according to the present invention includes a display area AA and a first, second and third non-display areas around the display area AA. NA1, NA2, NA3) are defined.

On the other hand, in the display area AA of the array substrate 110, a plurality of gate lines 113 and data lines 126 that define a plurality of pixel regions P intersecting with each other, and within the pixel regions P, respectively. Sources connected to the gate lines 113 and the data lines 126 defining the pixel regions P and spaced apart from the sequentially stacked gate electrodes (not shown), the gate insulating layer 117, and the semiconductor layer (not shown). And a thin film transistor Tr including a drain electrode (not shown), and a pixel electrode 150 connected to the drain electrode (not shown) of the thin film transistor Tr.

In this case, each of the gate and data connection lines 114 and 134 connected to the plurality of gate lines 113 and the plurality of data lines 126 is divided into several groups, respectively, and each end thereof is divided into the first non-display area NA1. ) And a second non-display area NA2, and at each end extending to the first and second non-display areas NA1 and NA2, a gate pad and a data pad are respectively shown. It is composed.

The display area AA may include a plurality of portions depending on the number of data driving integrated circuits 165a and 165b to which the data line 126 is more precisely connected, and the data connection line 134 connected to the plurality of data lines 126. It is divided into areas A1 and A2. In the drawing, two data driving integrated circuits 165a and 165b are configured to be divided into two partial regions A1 and A2.

On the other hand, as described above, each of the gate pad (not shown) and the data pad (not shown), which are divided into a plurality of groups, are electrically connected through bumps (not shown), and the like. 2 are connected to a plurality of gate and data driving integrated circuits 163 and 165 mounted on the same line in the non-display areas NA1 and NA2.

In addition, each of the data connection line 134 and the gate connection line 114 may be formed of a plurality of thin film transistors Tr to prevent damage to the thin film transistor Tr, which is a switching element in the display area AA due to static electricity. The first and second non-display areas NA1 and NA2 are connected to an electrostatic compensation circuit C1.

In this case, as a characteristic feature of the present invention, a portion of the second non-display area NA2 in which the data connection line 134 is formed is connected to each data connection line 134 and the electrostatic compensation circuit C1 is formed. The semiconductor wiring 123 is formed to cross the data connection wiring 134 in contact with the area between the display regions AA and form an equipotential. In this case, the semiconductor wire 123 is formed of only a semiconductor material such as pure amorphous silicon, not a metal material which is connected to the data connection wires 134 in contact with the data connection wires 134 on the gate insulating layer 117 but is smoothly conductive. The lower layer of the semiconductor material and the data connection wiring 134 is the same metal material forming the upper layer in the form of spaced apart at regular intervals and has a structure in which a plurality of metal patterns (not shown) are formed. The structure of the semiconductor wiring 123 depends on whether the array substrate 110 is manufactured by a five mask process (see FIGS. 5 and 6) or by a four mask process (see FIGS. 7 and 8). 5 and 6 illustrate, as an example, a semiconductor wiring 123 having a single layer structure of only a semiconductor material made of pure amorphous silicon by being manufactured by a five-mask process. In the case of the four-mask process, the active layer (not shown) and the semiconductor layer (not shown) of the thin film transistor Tr formed in each pixel area P in the display area AA and the upper portion thereof are not shown. This is because the source and drain electrodes of (not shown) are simultaneously manufactured through one mask process. This manufacturing method will be described later.

Meanwhile, since the semiconductor wire 123 is formed of a semiconductor material in contact with all of the data connection wires 134, not all of the data wires 126 in the display area AA are electrically electrically connected. It will have a movable passage. Therefore, even when the amount of carriers that are captured and exposed to the plasma in the process of forming a protective layer or the like as an insulating material varies for each of the partial regions A1 and A2, the carriers are moved through the semiconductor wiring 123. Since the amount of carriers between the regions A1 and A2 is in equilibrium, the amount of carriers induced by each subregion A1 and A2 after the final completion is at a similar level, resulting in a luminance difference for each of the partial regions A1 and A2. You will not.

As described above, the semiconductor wiring 123 may be formed in the second non-display area NA2 on which the data driving integrated circuit 165 is mounted, or as a modification of FIG. 7 (in the modification of the present invention). As shown in an enlarged plan view of a portion in which a semiconductor wiring of the array substrate for a COG type liquid crystal display device is formed) and FIG. 8 (a cross-sectional view of a portion taken along a cutting line VII-V). The wiring 123 is positioned below the non-display area that is symmetrical with the second non-display area NA2 of FIG. 4 and the display area AA of FIG. 4 interposed therebetween. The third non-display area NA3 may be formed in contact with all of the data lines 126 in correspondence with the ends of the data lines 126 formed outside the display area AA of FIG. 4. In this case, even in the third non-display area NA3, an antistatic circuit C1 may be connected to an end of each data line 126, and in this case, the semiconductor wire 123 may be connected to each of the antistatic circuits. It is formed inside (C1) adjacent to the display area (AA in FIG. 4). In the drawing, for example, a semiconductor wiring 123 formed of a semiconductor material is formed on the gate insulating layer 117 by a four-mask process, and a metal pattern 135 spaced apart therebetween is formed. It was. In this case, the semiconductor wire 123 may have a straight shape having the same width, or, as shown in the drawing, has a first width at a portion where the metal pattern 135 is formed, and the metal pattern 135 is removed. The portion may be formed to have a second width larger than the first width. In this case, the spaced apart plurality of metal patterns 135 is characterized in that the spaced area corresponds to an area between each data line 126 or an area between each data connection line (not shown). In this case, the metal pattern 135 is branched from each data line 126, and the metal pattern 135 may be omitted.

Hereinafter, as described above, a method of manufacturing an array substrate for a COG liquid crystal display device including a semiconductor wiring connecting both data connection wiring or data wiring to a non-display area will be described.

9A to 9F are cross-sectional views illustrating manufacturing steps of a portion including a thin film transistor as a switching element in one pixel region of an array substrate for a COG type liquid crystal display according to the present invention, and FIGS. 10A to 10G illustrate the present invention. Step by step manufacturing step for the portion where the semiconductor wiring is formed in the non-display area of the array substrate for the COG type liquid crystal display device according to the step, and step by step manufacturing step for the portion shown in Figure 8 having the characteristics according to the four mask manufacturing process. . In this case, the semiconductor wiring is connected to the end of the data wiring in FIG. 8 and is formed in the third non-display area. However, the semiconductor wiring may be formed in the second non-display region in which the data connection wiring is formed. In addition, the manufacturing method of the present invention does not mention the antistatic circuit connected to each data line and the gate line. Since the components constituting the antistatic circuit are a plurality of thin film transistors, and each of the thin film transistors has the same structure as the thin film transistor which is a switching element formed in the pixel region, the thin film transistor can be replaced by a method of manufacturing a thin film transistor in the pixel region. Because there is.

9A and 10A, first, by depositing a metal material on the substrate 110 to form a metal layer (not shown), a photoresist having photosensitivity thereon is applied to the entire surface, and then the photo After exposing the resist using an exposure mask, developing the resist, the metal layer (not shown) exposed to the outside of the developed photoresist is etched, and a series of mask processes are performed to strip the photoresist. Patterning the metal layer (not shown) to form a gate wiring (not shown) extending in one direction, and simultaneously forming a gate electrode 115 branched from the gate wiring (not shown) in each pixel region (P). . At the same time, in the non-display area (not shown) on one side, a gate connection wiring (not shown) connected to the gate wiring (not shown) and a gate pad electrode (not shown) are formed at one end of the gate connection wiring (not shown). do.

Next, as shown in FIGS. 9B and 10B, an inorganic insulating material such as silicon oxide (SiO ₂ ) or nitride is formed on the entire surface of the gate wiring (not shown), the gate electrode 115, and the exposed substrate 110. Silicon (SiNx) is deposited to form a gate insulating film 117, and subsequently, pure amorphous silicon, impurity amorphous silicon, and metal materials are successively deposited on the gate insulating film 117 to form a pure amorphous silicon layer 118 and an impurity amorphous. The silicon layer 119 and the metal material layer 122 are formed.

Next, a photoresist layer 181 is formed by applying a photoresist on the metal material layer, a transmission area TA for transmitting 100% of the exposed light, a blocking area BA for blocking 100% of light, and light An exposure mask 191 including a semi-transmissive area (HTA) capable of adjusting a transmission amount of the light source between 0% and 100% is positioned above the photoresist layer 181, and then the photoresist layer 181 is disposed on the photoresist layer 181. The exposure through the exposure mask 191 is performed.

In this case, when the photoresist on which the photoresist layer 181 is formed receives a light, and is a negative type remaining during development, the data line and the data connection line on the array substrate 110 and the pixel region ( Corresponding to the portion of the source and drain electrodes to be formed in P), the transmission area TA of the exposure mask 191 overlaps the gate electrode 115 and is exposed between the source and drain electrodes. The semi-transmissive area HTA of the exposure mask 191 is located in the other area for the area between the channel connection and the data connection line in the area where the semiconductor wiring is to be formed in the third non-display area NA3. For example, the exposure mask 191 is positioned to correspond to the blocking area BA of the exposure mask 191 and then exposed. In this case, when the photoresist is a positive type tape, the positions corresponding to the array substrates of the transmissive area and the blocking area are changed to correspond to each other, and then the exposure is performed to expose the negative type photoresist. The same result as used is obtained.

Next, as described above, when the exposure mask 191 is placed on the array substrate 110, the exposure is performed, and the photoresist layer 181 is developed, as shown in FIGS. 9C and 10C. A first photoresist pattern 181a having a thick first thickness remains in a region corresponding to the transmission region (TA in FIGS. 9B and 10B) of the exposure mask 191 and FIGS. 10B, and the exposure mask (FIG. 9B). 9b and 10b, the second photoresist pattern 181b having a second thickness thinner than the first thickness remains, and the exposure mask (FIG. The photoresist layer (181 in FIGS. 9B and 10B) corresponding to the blocking region (BA in FIG. 9B) of 191 in FIGS. 9B and 10B is removed to expose the metal layer 122 during development.

Next, as shown in FIGS. 9D and 10D, the metal layer exposed to the outside of the first and second photoresist patterns 181a, 9c, and 181b of FIG. 10c (122 of FIGS. 9c and 10c) and a lower portion thereof. By sequentially etching the impurity amorphous silicon layer (119 of FIGS. 9C and 10C) and the pure amorphous silicon layer (118 of FIGS. 9C and 10C) to the gate insulating layer 117 to cross the gate wiring (not shown). Each pixel region P is defined, and a first pure amorphous silicon pattern (not shown), a first impurity amorphous silicon pattern (not shown), and a data line 126 that are patterned and stacked in the same shape are sequentially formed. In the pixel region P, a source drain pattern 127 connected to the data line 126 is formed. In this case, a second impurity amorphous silicon pattern 125a and an active layer 124 of pure amorphous silicon are formed under the source drain pattern 127. Also, in the third non-display area NA3, a plurality of data connection wires (not shown) connected to each of the data wires 126 are formed, and in contact with the plurality of data connection wires (not shown). Or a second pure amorphous silicon pattern 123, a third impurity amorphous silicon pattern 125b, and a metal wire 128 are formed in contact with one end of each of the plurality of data wires 126. In the drawing, the metal wire 128 is connected to the data wire 126. In addition, a data pad electrode (not shown) is formed at an end of the data connection wiring (not shown).

Next, the ashing process is performed on the substrate 110 on which the data line 126, the data connection line (not shown), the source drain pattern 127, and the metal line 128 in the form of a wire are formed. By removing the photoresist pattern having two thicknesses (181b in FIGS. 9C and 10C), the center portion of the source drain pattern 127 is exposed in the pixel region P, and the respective data wirings are formed in the third non-display region NA3. A portion of the metal wiring 128 positioned in the spaced area between 126 or the spaced area between each data connection wire (not shown) is exposed.

At this time, the thickness of the photoresist pattern 181a having the first thickness also becomes thin due to the ashing, but remains even after the completion of the ashing with a predetermined thickness.

Next, as shown in FIGS. 9E and 10E, the second photoresist pattern (181b of FIGS. 9C and 10C) is removed by the ashing to expose the source drain pattern (127 of FIG. 9D) and the lower portion thereof. The impurity amorphous silicon pattern (125a in FIG. 9D) is sequentially etched and removed to form source and drain electrodes 131 and 133 which are spaced apart from each other in the pixel region P, and below the active layer 124. And form an ohmic contact layer 129 of impurity amorphous silicon spaced apart from each other. In the non-display area NA, the metal wiring (128 in FIG. 10D) and the third impurity amorphous silicon pattern (125b in FIG. 10) of a part of the region spaced apart between the data wiring 126 or the data connection wiring (not shown) are provided. ) Is formed on the second pure amorphous silicon pattern 123 in the wiring form to form a metal pattern 135 in the form of a branch and spaced apart from the data wiring 126 or the data connection wiring (not shown). In this case, a third impurity amorphous silicon pattern 125b still remains between the metal pattern 135 and the second pure amorphous silicon pattern 123. Meanwhile, the second pure amorphous silicon pattern 123 having the wiring form the semiconductor wiring 123. The semiconductor wiring 123 formed as described above is made of pure amorphous silicon, and thus a small amount of carriers can be moved therethrough, and thus a short circuit between the data wirings 126 does not occur since a complete electrical conduction is not performed with the metallic material. to be. Meanwhile, the metal pattern 128 spaced apart from each other in the form of branching from the data line 126 or the data connection line (not shown) may be omitted. Thereafter, the strip is processed to remove the first photoresist pattern 181a.

Next, as shown in FIGS. 9F and 10F, the strip is processed to remove the first photoresist pattern (181a of FIGS. 9E and 10E). Thereafter, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), which is an inorganic insulating material, is formed on the entire surface of the data wire 126, the data connection wire (not shown), the source and drain electrodes 131 and 133, and the semiconductor wire 123. Depositing a protective layer 140, and then patterning the protective layer 140 and the gate insulating layer 117 under the drain contact hole 143 to partially expose the drain electrode 133. A gate pad contact hole (not shown) exposing a gate pad electrode (not shown) and a data pad contact hole (not shown) exposing the data pad electrode (not shown) are formed.

Next, indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material, is disposed on the passivation layer 140 having the drain contact hole 143 and the gate and data pad contact holes (not shown). The pixel electrode 150 which contacts the drain electrode 133 through the drain contact hole 143 through the drain contact hole 143 by depositing and patterning the entire surface, and the gate and data pad electrodes (not shown), respectively. The array substrate 110 is completed by forming gate and data auxiliary pad electrodes (not shown) in contact.

On the other hand, in the above-described manufacturing method, the manufacturing method of the array substrate including the semiconductor wiring through the four mask process is shown as an example, it is also possible to complete the array substrate having the above-described semiconductor wiring through the five mask process. The manufacturing method of the array substrate through the 5-mask process will be briefly described where the differences from the 4-mask process without the drawings.

The gate wiring and the gate electrode are formed, and a gate insulating film is formed thereon. Subsequently, a pure and impurity amorphous silicon layer is formed on the gate insulating layer, and then patterned to form an impurity amorphous silicon pattern connected to an active layer and an upper portion thereof in the pixel region, and at the same time, a pure and impurity amorphous silicon double layer structure in the non-display region. Wiring pattern is formed. Thereafter, a metal material layer is deposited and patterned to form a source and drain electrode spaced apart from each other on the impurity amorphous silicon pattern, a data line connected to the source electrode, and a data connection line connected thereto, and dry etching is performed to form the source and drain electrodes. By removing the impurity amorphous silicon pattern exposed between the drain electrode and the impurity amorphous silicon wiring pattern exposed between the data wiring or the data connection wiring, an ohmic contact layer exposing the active layer under the source and drain electrodes in the pixel region is removed. In the non-display area, a semiconductor wiring of pure amorphous silicon is formed. After that, a protective layer for exposing the drain electrode is formed on the upper portion thereof, and a pixel electrode in contact with the drain electrode is formed on the upper portion thereof, thereby completing an array substrate according to a five mask process.

The present invention is not limited to the above-described embodiments and modifications thereof, and various modifications may be made without departing from the spirit of the present invention.

1 is an exploded perspective view of a general liquid crystal display device.

2 is a schematic plan view of a conventional array substrate for a COG type liquid crystal display device.

3 is an enlarged plan view of a region A of FIG. 2;

4 is a schematic plan view of an array substrate for a COG type liquid crystal display according to an embodiment of the present invention.

5 is a plan view showing an enlarged view of a region B in Fig.

6 is a cross-sectional view of the portion cut along line VI-VI of Fig. 5;

FIG. 7 is an enlarged plan view of a portion in which semiconductor wiring of an array substrate for a COG type liquid crystal display device according to a modification of the present invention is formed; FIG.

FIG. 8 is a cross-sectional view of a portion taken along the line VII-VII of FIG. 7. FIG.

9A to 9F are cross-sectional views of manufacturing steps of a portion including a thin film transistor as a switching element in one pixel region of an array substrate for a COG type liquid crystal display according to the present invention.

10A to 10G are cross-sectional views of steps in manufacturing a portion in which a semiconductor wiring is formed in a non-display area of an array substrate for a COG type liquid crystal display according to the present invention.

Description of the Related Art

110: array substrate 123: semiconductor wiring

134: data connection wiring A1, A2: partial area

C1: antistatic circuit NA2: second non-display area

Claims (6)

A third non-display area having a display area, a first non-display area having a gate pad formed therein, a second non-display area having a data pad formed therebetween, and a third non-display area positioned at a portion symmetrical with the second non-display area A substrate on which a display area is defined; A plurality of gate wirings and data wirings formed to define a plurality of pixel regions crossing each other in the display region; A thin film transistor which is a switching element provided in each of the plurality of pixel areas; Pixel electrodes connected to one electrode of the thin film transistor in each of the plurality of pixel regions; A plurality of gate driver integrated circuits in a chip form spaced apart from each other in the first non-display area; A plurality of data driver integrated circuits in a chip form spaced apart from each other in the second non-display area; A plurality of gate connection wirings connected to one of the plurality of gate driving integrated circuits in the first display area and simultaneously connected to the gate wirings; A plurality of data connection wires connected to one of the plurality of data driving integrated circuits in the second display area and simultaneously connected to the data wires; A semiconductor wiring made of the same material on the same layer as the active layer, which is one component of the thin film transistor, which intersects with and contacts the plurality of all data connection wirings in the second non-display area. Array substrate for a COG type liquid crystal display device comprising a. A third non-display area having a display area, a first non-display area having a gate pad formed therein, a second non-display area having a data pad formed therebetween, and a third non-display area positioned at a portion symmetrical with the second non-display area A substrate on which a display area is defined; A plurality of gate wirings and data wirings formed to define a plurality of pixel regions crossing each other in the display region; A thin film transistor which is a switching element provided in each of the plurality of pixel areas; Pixel electrodes connected to one electrode of the thin film transistor in each of the plurality of pixel regions; A plurality of gate driver integrated circuits in a chip form spaced apart from each other in the first non-display area; A plurality of data driver integrated circuits in a chip form spaced apart from each other in the second non-display area; A plurality of gate connection wirings connected to one of the plurality of gate driving integrated circuits in the first display area and simultaneously connected to the gate wirings; A plurality of data connection wires connected to one of the plurality of data driving integrated circuits in the second display area and simultaneously connected to the data wires; A semiconductor wiring made of the same material on the same layer as the active layer, which is one component of the thin film transistor, which intersects one end of the plurality of data lines in the third non-display area and is in contact with them; Array substrate for a COG type liquid crystal display device comprising a. 3. The method according to claim 1 or 2, An array substrate for a COG type liquid crystal display device having a plurality of metal patterns spaced apart from each other in a plurality of data lines or a plurality of data connection lines. The method of claim 3, And an impurity amorphous silicon pattern is formed between the semiconductor wiring and the plurality of metal patterns with the same material forming the ohmic contact layer among the components constituting the thin film transistor. The method of claim 3, And wherein the plurality of spaced metal patterns correspond to a space between each data line or a space between each data connection line. 3. The method according to claim 1 or 2, The thin film transistor may include a gate electrode, a gate insulating film, an active layer, an ohmic contact layer, and a source and a drain electrode sequentially stacked in a form of a COG type liquid crystal display device.

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