KR20110068271A - Thin film transistor array substrate and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A thin film transistor array substrate and a method for manufacturing the same are provided to improve an aperture ratio and preventing light leakage by applying a shield pattern. CONSTITUTION: A thin film transistor array substrate comprises gate lines and data lines(18c) on a substrate(10) in order to define pixel regions, a TFT which is formed on an intersection area of the gate line and the data line, a pixel electrode which is arranged on the pixel region, a shielding pattern(24b) which is formed on the upper part of the data line for being overlapped, and a TFT array substrate which includes a common electrode(26b) and generates transversal electric field.

Description

Thin film transistor array substrate and method for manufacturing the same

The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a thin film transistor array substrate and a method for manufacturing the same.

Currently, an active matrix liquid crystal display device having a thin film transistor (Thin-Film-Transistor) and pixel electrodes connected to the thin film transistor in a matrix manner is attracting the most attention due to its excellent resolution and ability to implement video.

The structure of the liquid crystal display according to the related art will be described with reference to FIG. 1 as follows.

1 is a schematic cross-sectional view of a liquid crystal display according to the prior art, which is a schematic cross-sectional view showing a case where light leakage occurs in a data line area.

The liquid crystal display device of the in-plane switching (IPS) according to the prior art, as shown in Figure 1, the pixel electrode 23 formed on the pixel region and the pixel region and the pixel electrode 23 and A lower substrate 11 having array wirings and alignment layers 25 including a common electrode 21 and a thin film transistor (not shown), which are switching elements, formed on the same plane or another layer, spaced apart by a predetermined interval, and The upper substrate 41 includes a black matrix 43 and color filters (not shown) including sub color filters (R, G, and B), and the lower substrate 11 and the upper substrate 41. Between the liquid crystals 51 is filled.

Here, the lower substrate 11 is also referred to as a thin film transistor array substrate, a thin film transistor (not shown) that is a switching element is located in a matrix form, the gate line (not shown) and the data line (not shown) crossing the plurality of thin film transistors ( 13) is formed.

In addition, the thin film transistor array substrate of the liquid crystal display according to the related art has a display area, ie, a driving area, in which light is transmitted to display an image, a non-display area in which light is blocked by a black matrix, and an image is not displayed. That is, it can be divided into a non-driving area.

In this case, the non-driving area is different from the data line 13 and the pixel electrode 23 differently from the area in which the liquid crystal is driven due to the electric field generated between the driving area, that is, the pixel electrode 23 and the common electrode 21. The liquid crystal is driven by the electric field generated in. As such, when an electric field different from the driving region is generated in the non-driving region, it becomes impossible to control the liquid crystal in a desired direction so that unwanted light is transmitted and light leakage occurs. Therefore, the black matrix 43 is formed on the upper substrate 41 to block light leakage in the non-driving region.

According to the liquid crystal display device according to the prior art made of the above configuration has the following problems.

Light leakage to the driving region of the liquid crystal display according to the prior art is blocked by the black matrix provided on the upper substrate, the light leakage is generated due to misalignment that may occur when the upper substrate and the lower substrate is bonded.

In addition, in order to prevent light leakage that may be generated in this way, when the width of the black matrix is widened, there is a problem that the aperture ratio is reduced.

Therefore, when the desired electric field cannot be formed, the liquid crystal cannot be controlled to transmit unwanted light. Due to the structural characteristics of the liquid crystal display device according to the related art, the pixel cannot form such a desired electric field. do.

An object of the present invention for solving the above problems is to provide a thin film transistor array substrate and a method of manufacturing the same that can prevent light leakage by applying a shielding pattern and improve the aperture ratio.

A thin film transistor array substrate according to the present invention for achieving the above object is formed on the substrate, the gate line and data line arranged to cross each other to define a pixel region, and the portion where the gate line and the data line intersect A thin film transistor, a pixel electrode connected to the drain electrode of the thin film transistor, arranged in the pixel region, a shielding pattern formed to overlap the upper portion of the data line, and alternately arranged in the pixel region. Thereby generating a transverse electric field, and including a common electrode formed on the shielding pattern.

The shielding pattern is formed of a photo acrylic film.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor array substrate, the method comprising: forming a gate electrode and a common line on a substrate, and forming a gate insulating layer on the substrate on which the common line and the gate electrode are formed. Forming a data line, a semiconductor pattern, a source and a drain electrode on the substrate on which the gate insulating film is formed; forming a protective film on the substrate on which the source and drain electrodes are formed; Forming a contact hole exposing the drain electrode, forming a shielding pattern corresponding to the data line on the substrate on which the contact hole is formed, and forming a common electrode and a pixel electrode on the substrate on which the shielding pattern is formed. Forming a step.

The forming of the shielding pattern may include forming a pattern forming material on the substrate on which the contact hole is formed, and aligning the soft mold having the recess pattern formed on the substrate on which the pattern forming material is formed. Contacting the soft mold to a layer, and separating the soft mold and the substrate on which the pattern material layer is formed.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor array substrate, the method comprising: forming a gate electrode and a common line on a substrate, and forming a gate insulating layer on the substrate on which the common line and the gate electrode are formed. Forming a data line, a semiconductor pattern, a source and a drain electrode on the substrate on which the gate insulating film is formed, forming a protective film on the substrate on which the source and drain electrodes are formed, and forming a protective film on the substrate on which the protective film is formed. Forming a shielding pattern corresponding to the contact hole and the data line exposing the drain electrode, and forming a common electrode and a pixel electrode on the substrate on which the contact hole and the shielding pattern are formed.

The forming of the shielding pattern and the contact hole may include forming a pattern material layer on the substrate on which the protective film is formed, and aligning the soft mold having the concave portion pattern and the convex portion pattern on the substrate on which the pattern forming material is formed. And then contacting the soft mold to the pattern material layer, separating the soft mold and the substrate on which the pattern material layer is formed to form recesses and contact patterns on the pattern material layer, and the recesses and contacts. Etching the pattern material layer by using a pattern as an etch mask.

In the above-described thin film transistor array substrate and a method of manufacturing the same, a shielding pattern is formed on the data line 18c, whereby the shielding pattern shields a signal between the data line 18c and the pixel electrode so as to be adjacent to the data line 18c. It is possible to reduce the width of the liquid crystal non-driven region generated in the, and to reduce the width of the black matrix 143 formed correspondingly there is an effect that the aperture ratio is improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B are plan and cross-sectional views illustrating a thin film transistor array substrate according to an exemplary embodiment of the present invention.

2A and 2B, in the thin film transistor array substrate according to the present invention, gate lines 12a and data lines 18c are formed on the substrate 10 to define pixel regions. A thin film transistor, which is a switching element, is formed in an intersection region of the gate line 12a and the data line 18c, and a common electrode 26b and a pixel which generate a transverse electric field to drive a liquid crystal (not shown) in the pixel region. The electrode 26a is arrange | positioned.

The thin film transistor includes a gate electrode 12a integrally formed with the gate line 12a, a drain electrode 18a formed to face the source electrode 18b connected to the data line 18c, and the source electrode 18b. And an active layer 16a forming a channel region between the source electrode 18b and the drain electrode 18a by the gate voltage supplied to the gate electrode 12a.

The common electrode 26b is branched into the pixel area, and is alternately disposed with the pixel electrode 26a, and is formed on the common electrode 26b so as to overlap the data line 18c, and is disposed in parallel with the gate line 12a. 12b) and the first contact hole 22c.

The pixel electrode 26a is formed such that one side thereof is alternately disposed with the common electrode 26b, and the other side thereof is integrally formed with a connection line formed to overlap the common line 12b, and the connection line is formed as a second contact. It is connected to the drain electrode 18a through the hole 22a.

The gate line 12a and the data line 18c extend toward the driving circuit part and are connected to the corresponding gate pad line 12c and the data pad line (not shown), respectively, and the gate pad line 12c is a gate contact hole. A data pad line (not shown) is electrically connected from the driving circuit through a data contact hole (not shown), and is electrically connected to a gate pad electrode 26c receiving a scan signal from the driving circuit portion through a 22b. Is electrically connected to a data pad electrode (not shown) to which is applied.

The common electrode 26b is formed on the data line 18c, and a shielding pattern 24b is formed between the data line 18c and the common electrode 26b.

As such, by forming the common electrode 26b on the data line 18c, the common electrode 26b shields a signal between the data line 18c and the pixel electrode to generate a liquid crystal in an area adjacent to the data line 18c. The width of the non-driving area can be reduced, and the width of the black matrix 143 formed correspondingly can be reduced, thereby improving the aperture ratio.

Next, a method of manufacturing a thin film transistor array substrate including a shielding pattern and a common electrode formed on a data line will be described in detail.

3A and 3B to 6A and 6B are plan and cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

First, FIGS. 3A and 3B are plan and cross-sectional views illustrating a thin film transistor array substrate on which a first mask process is performed.

As shown in FIGS. 3A and 3B, a gate electrode 12a, a common line 12b, and a gate pad 12c are formed on the substrate 10.

The substrate 10 includes a region G-Pad in which a gate pad is formed, a region D-line in which a data line is formed, a pixel region PXL, a region Cst in which a capacitor is formed, and a thin film transistor. It is defined as a region to be formed (TFT).

The gate electrode 12a, the common line 12b, and the gate pad 12c sequentially form a first metal layer and a photoresist on the substrate 10, and perform a photo process using the first mask on the photoresist. To form a first photoresist pattern (not shown), which is then etched into the metal film using an etching mask.

Next, the gate insulating layer 14 is formed on the substrate 10 on which the gate electrode 12a, the common line 12b, and the gate pad 12c are formed.

4A and 4B are plan and cross-sectional views illustrating a thin film transistor array substrate having a second mask process.

4A and 4B, the data line 18c, the source and drain electrodes 18b and 18a, and the semiconductor pattern 16a are formed on the substrate 10 on which the gate insulating layer 14 is formed. The passivation layer 20 is formed on the substrate 10 on which the data line 18c, the source and drain electrodes 18b and 18a are formed.

The semiconductor pattern 16a is formed under each of the source and drain electrodes 18b and 18a and the data line 18c.

A method of forming the data line 18c, the source and drain electrodes 18b and 18a, and the semiconductor pattern 16a will be described in more detail below.

First, a semiconductor layer, a second metal layer, and a second photoresist pattern are sequentially formed on the substrate 10 on which the gate insulating layer 14 is formed.

In this case, the semiconductor layer is formed of an amorphous silicon layer and an n + amorphous silicon layer.

The second photoresist pattern is formed by a photo process using a second mask (not shown) after forming the photoresist on the substrate on which the second metal layer is formed. In this case, the second mask uses a mask having three different transmittances including a transmission region for transmitting light, a semi-transmission region for transmitting a portion of light and blocking a portion of the light, and a blocking region for blocking light. The photoresist remains as it is in the blocking region. The photoresist remains in a semi-transmissive region at a thickness lower than that of the blocking region, and no photoresist remains in the transmissive region. Therefore, the blocking region is disposed in the region where the data line is to be formed, the region in which the source and drain electrodes are to be formed, the transflective region is disposed in the channel region of the thin film transistor, and the transmissive region is disposed in the blocking region and the transflective region. It is placed in the remaining area except the area.

Subsequently, the second metal layer and the semiconductor layer are etched using the second photoresist pattern as an etch mask to form the data line 18c, the semiconductor pattern 16a, and the source / drain electrode pattern on the substrate 10.

The second photoresist pattern is then ashed to form a third photoresist pattern. In this case, all of the second photoresist patterns formed in the region where the channel is to be formed are removed during the ashing process to expose the second metal layer of the source / drain electrode pattern formed in the region where the channel is to be formed.

Subsequently, the second metal layer of the source / drain electrode pattern exposing the third photoresist pattern as an etch mask is etched to form source / drain electrodes 18b and 18a.

Then, the third photoresist pattern is removed through a script process.

5A and 5B are plan and cross-sectional views illustrating a thin film transistor array substrate having a third mask process.

As shown in FIGS. 5A and 5B, first and second contact holes 22a and 22b are formed on the substrate 10 on which the data lines 18c and the source and drain electrodes 18b and 18a are formed.

The first contact hole 22a and the second contact hole 22b pattern the passivation layer 22 to expose the drain electrode 18a and the gate pad 12c, respectively.

The first and second contact holes 22a and 22b form a photoresist on the passivation layer 20, and perform a photo process using a third mask on the photoresist to form a fourth photoresist pattern (not shown). Is formed, and the protective film 22 is etched using an etching mask.

6A and 6B are plan and cross-sectional views illustrating a thin film transistor array substrate on which a shielding pattern 24b, a common electrode 26b, and a pixel electrode 26a are formed through an IPP process and a four mask process. FIG. 7D is a cross-sectional view for describing a process of forming the shielding pattern 24b, the common electrode 26b, and the pixel electrode 26a in more detail.

First, as shown in FIG. 7A, a pattern material layer 24a is formed on the substrate 10 on which the first and second contact holes 22a and 22b are formed.

In this case, photoacryl is used as the pattern material layer 24a.

Then, a backplane is provided on the rear surface to correspond to the substrate 10 on which the pattern material layer 24a is formed, and the soft mold 100 having the recess pattern 100a is prepared on the surface thereof.

The backplane may be made of glass, PET film, etc., and the soot mold (100: soft mold) may be manufactured by curing an elastomer such as PDMS (polydimethylsiloxane) and PUA (polyurethane acrylate), in addition to polyurethane (polyurethane) ), Polyimides and the like can be used.

In addition, the soft mold 100 is provided with a recess 100a for forming a shielding pattern on its surface.

As shown in FIG. 7B, after aligning the substrate 10 on which the soft mold 100 and the pattern material layer 24a are formed, the surface of the soft mold 100 contacts the pattern material layer 24a. The shield pattern 24b is formed in the pattern material layer 24a by leaving corresponding portions of the recesses 100a of the soft mold 100. Here, the pattern material layer 24a may be cured using heat or light while the soft mold 100 and the pattern material layer 24a are in contact with each other.

Subsequently, as illustrated in FIG. 7C, the shielding pattern 24b is formed by separating the soft mold 100 from the pattern material layer 24a on which the shielding pattern 24b is formed.

As shown in FIG. 7D, the pixel electrode 26a, the common electrode 26b, and the gate pad electrode 26c are formed on the substrate 10 on which the shielding pattern 24b is formed, thereby completing the present process. do.

The pixel electrode 26a, the common electrode 26b, and the gate pad electrode 26c sequentially form a third metal layer and a photoresist, which are transparent conductive films, on the substrate 10 on which the shielding pattern 24b is formed. The fifth photoresist pattern (not shown) is formed by performing a photolithography process using a fourth mask on the resist, and the third metal layer is etched using the etching mask.

In this case, the common line 12b and the pixel electrode 26a overlap each other with the gate insulating layer 14 and the passivation layer 20 interposed therebetween to form a storage capacitor.

Such a thin film transistor array substrate and its manufacturing method form a common electrode 26b on the data line 18c, whereby the common electrode 26b shields a signal between the data line 18c and the pixel electrode to prevent the data line 18c. The width of the liquid crystal non-driving region generated in the region adjacent to the N-th) can be reduced, and the width of the black matrix 143 formed correspondingly can be reduced, thereby improving the aperture ratio.

Next, a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention will be described in detail.

8A and 8B to 9A and 9B are plan and cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

8A and 8B are plan views illustrating a thin film transistor array substrate on which a second mask process is performed.

8A and 8B, a gate electrode 12a, a common line 12b, a gate pad 12c, a gate insulating layer 14, a data line 18c, a source and a drain are disposed on the substrate 10. The electrodes 18b and 18a, the semiconductor pattern 16a and the protective film 20 are formed.

The gate electrode 12a, common line 12b, gate pad 12c, gate insulating film 14, data line 18c, source and drain electrodes 18b and 18a, semiconductor pattern 16a, and protective film ( 20) is formed through the same process as the first and second mask processes of the first embodiment of the present invention, so a description thereof will be omitted.

9A and 9B illustrate a thin film transistor array substrate on which shielding patterns 24b, first and second contact holes 24be and 24de, pixel electrodes 26a, common electrodes 26b, and gate pad electrodes 26c are formed. 10A through 10E show shielding patterns 24b, first and second contact holes 24be and 24de, pixel electrodes 26a, common electrodes 26b, and gate pad electrodes 26c. Are cross-sectional views for explaining the forming process in more detail.

First, as shown in FIG. 10A, a pattern material layer 24a for forming a shielding pattern is formed on the substrate 10 on which the passivation layer 20 is formed.

In this case, photoacryl is used as the pattern material layer 24a.

Then, a backplane is provided on the rear surface to correspond to the substrate 10 on which the pattern material layer 24a is formed, and a soft mold 200 having a recess pattern on the surface thereof is prepared.

The backplane may be made of glass, PET film, and the like. The soft mold (200) may be manufactured by curing an elastomer such as PDMS (polydimethylsiloxane) and PUA (polyurethane acrylate). In addition, polyurethane (polyurethane) ), Polyimides and the like can be used.

In addition, the soft mold 200 has a concave portion 200a for forming a shielding pattern and convex portions 200b and 200c for forming first and second contact holes on a surface thereof.

As shown in FIG. 10B, after aligning the substrate 10 on which the soft mold 200 and the pattern material layer 24a are formed, the surface of the soft mold 200 is placed on the pattern material layer 24a. Contacting to leave the corresponding portions of the concave portion 200a and the convex portion 200b of the soft mold 200 in the pattern material layer 24a and the concave portion 24c and the first and second contact patterns 24b and 24d. ). Here, the pattern material layer 24a may be cured by using heat or light while the soft mold 200 and the pattern material layer 24a are in contact with each other.

Next, as illustrated in FIG. 10C, the soft mold 100 is separated from the pattern material layer 24a on which the concave portion 24c and the first and second contact patterns 24b and 24d are formed.

As shown in FIG. 10D, the recess 24c and the first and second contact patterns 24b and 24b of the pattern material layer 24a are etched using an etch mask to form first and second contact holes. 24be, 24de) and blocking pattern 24c are formed.

Subsequently, as shown in FIG. 10E, the pixel electrode 26a, the common electrode 26b, and the gate are formed on the substrate 10 on which the shielding pattern 24c and the first and second contact holes 24be and 24de are formed. This step is completed by forming the pad electrode 26c.

The pixel electrode 26a, the common electrode 26b, and the gate pad electrode 26c sequentially form a third metal layer and a photoresist, which are transparent conductive films, on the substrate 10 on which the shielding pattern 24c is formed. The fifth photoresist pattern (not shown) is formed by performing a photolithography process using a fourth mask on the resist, and the third metal layer is etched using the etching mask.

In this case, the common line 12b and the pixel electrode 26a overlap each other with the gate insulating layer 14 and the passivation layer 20 interposed therebetween to form a storage capacitor.

Such a thin film transistor array substrate and its manufacturing method form a common electrode 26b on the data line 18c, whereby the common electrode 26b shields a signal between the data line 18c and the pixel electrode to prevent the data line 18c. The width of the liquid crystal non-driving region generated in the region adjacent to the N-th) can be reduced, and the width of the black matrix 143 formed correspondingly can be reduced, thereby improving the aperture ratio.

1 is a schematic cross-sectional view of a liquid crystal display according to the prior art, which is a schematic cross-sectional view showing a case where light leakage occurs in a data line region.

2A and 2B are a plan view and a cross-sectional view of a thin film transistor array substrate according to an embodiment of the present invention.

3A and 3B to 6A and 6B are plan and cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

7A to 7D are cross-sectional views illustrating in more detail a process of forming the shielding pattern, the common electrode, and the pixel electrode.

8A and 8B to 9A and 9B are plan and cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

10A through 10E are cross-sectional views illustrating in more detail a process of forming a shielding pattern, first and second contact holes, a pixel electrode, a common electrode, and a gate pad electrode.

Claims (8)

A gate line and a data line formed on the substrate and arranged to cross each other to define a pixel region; A thin film transistor formed at a portion where the gate line and the data line cross each other; A pixel electrode connected to the drain electrode of the thin film transistor and arranged in the pixel region; A shielding pattern formed to overlap the upper portion of the data line; And And a common electrode disposed on the shielding pattern in an alternating manner with the pixel electrode in the pixel region, the common electrode formed on the shielding pattern. The method of claim 1, wherein the shielding pattern A thin film transistor array substrate, characterized in that formed by a photo acrylic film. Forming a gate electrode and a common line on the substrate; Forming a gate insulating film on the substrate on which the common line and the gate electrode are formed; Forming a data line, a semiconductor pattern, a source and a drain electrode on the substrate on which the gate insulating film is formed; Forming a protective film on the substrate on which the source and drain electrodes are formed; Forming a contact hole exposing the drain electrode on the substrate on which the protective film is formed; Forming a shielding pattern on the substrate on which the contact hole is formed to correspond to the data line; And forming a common electrode and a pixel electrode on the substrate on which the shielding pattern is formed. The method of claim 3, wherein the forming of the shielding pattern is performed. Forming a pattern forming material on the substrate on which the contact hole is formed; Arranging the soft mold having the recess pattern formed on the substrate on which the pattern forming material is formed, and then contacting the soft mold to the pattern material layer; And separating the substrate on which the soft mold and the patterned material layer are formed. The method of claim 4, wherein the pattern forming material is A method of manufacturing a thin film transistor array substrate, characterized in that formed by a photoacrylic film. Forming a gate electrode and a common line on the substrate; Forming a gate insulating film on the substrate on which the common line and the gate electrode are formed; Forming a data line, a semiconductor pattern, a source and a drain electrode on the substrate on which the gate insulating film is formed; Forming a protective film on the substrate on which the source and drain electrodes are formed; Forming a shielding pattern on the substrate on which the protective layer is formed to correspond to the contact hole and the data line exposing the drain electrode; And forming a common electrode and a pixel electrode on the substrate on which the contact hole and the shielding pattern are formed. The method of claim 6, wherein the forming of the shielding pattern and the contact hole is performed. Forming a pattern material layer on the substrate on which the protective film is formed; Arranging the soft mold having the concave portion pattern and the convex portion pattern formed on the substrate on which the pattern forming material is formed, and then contacting the soft mold to the pattern material layer; Separating the soft mold and the substrate on which the pattern material layer is formed to form recesses and contact patterns in the pattern material layer; And etching the patterned material layer using the recess and the contact pattern as an etch mask to form the thin film transistor array substrate. The method of claim 7, wherein the pattern forming material A method of manufacturing a thin film transistor array substrate, characterized in that formed by a photoacrylic film.

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