KR20050097000A - Liquid crystal display device and method for fabricating of the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device in which a driving circuit is mounted in a COG method.

According to the present invention, when a driving circuit chip is mounted on a liquid crystal display device in a COG method, bumps and pads (data pads and gates) of the driving circuit chip (CHIP) may be caused by tilting of the driving circuit chip mounted on the glass substrate. The purpose is to prevent the problem of uneven contact resistance between the pads).

A characteristic constitution of the present invention for achieving the above object is to form an anti-tilt pattern in the glass region corresponding to the four corners of the drive circuit chip.

Since the anti-tilt pattern serves to support the four corners of the driving circuit chip mounted on the substrate, in the bonding process, the bumps of the driving circuit chip can be stably seated on the PAD part so that the bumps and the pads of the chip can be secured. There is an advantage that the contact resistance between them can be equalized.

Description

Liquid crystal display device and method for fabricating of the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and to a configuration of a liquid crystal display device for directly mounting a driving circuit chip on a glass substrate by a chip on glass (COG) method and a manufacturing method thereof.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, the active matrix liquid crystal display (AM-LCD) in which the above-described thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner is attracting the most attention due to its excellent resolution and ability to implement video.

Hereinafter, a configuration of a general active matrix liquid crystal display device will be described with reference to the drawings.

1 is an exploded perspective view schematically illustrating a configuration of a general liquid crystal display device.

As shown in FIG. 1, in the liquid crystal panel, a first substrate (lower substrate) 10 and a second substrate (upper substrate) 20 are bonded to each other at a predetermined interval and face the second substrate 20. A gate line 12 and a data line 14 are formed on one surface of the first substrate 10 to vertically cross each other to define the pixel region P. A thin film is formed at an intersection point of the two lines 12 and 14. The transistor T is configured.

One end of the gate line 12 includes a gate pad GP that receives a gate signal directly from the outside, and one end of the data line 14 includes a data pad DP that receives a data signal directly from the outside. Is composed.

In the pixel region P, a transparent pixel electrode 14 in contact with the thin film transistor T is formed.

On the other hand, one surface of the second substrate 20 facing the first substrate 10 has a black matrix 22 having a lattice shape, and an open portion inside the lattice, that is, a color corresponding to the pixel area P. The filter layers 28a, 28b, and 28c are formed, and a transparent common electrode 26 is formed on the front surface of the second substrate 20 including the color filter and the black matrix.

The liquid crystal layer 30 is formed in spaced spaces between the first and second substrates 10 and 20.

The liquid crystal display device constructed as described above uses a thin film transistor as a switching element.

In the above configuration, the gate driving circuit and the data driving circuit are configured to apply signals to the gate pad and the data pad.

The gate driving circuit and the data driving circuit may be configured in various ways, and examples thereof include a tape carrier package (TCP) method, a chip on film (COF) method, and a chip on glass (COG) method.

The TCP refers to a package utilizing Tape Automated Bonding (TAB) technology in which an IC chip is connected to a tape film and sealed with a resin. One side of the TCP is connected to the aforementioned pad, and the other is a signal input. It is configured by connecting with the PCB board.

The COF refers to a method of bonding a basic chip bumped onto a substrate of polyimide, and this technology is a new type of package developed to cope with LCD driving circuits with the trend of thin and short communication devices.

The COG is a method of bonding the basic driving circuit to the glass substrate,

As one of the bonding methods, it is a new mounting method to cope with the miniaturization of the connection pitch due to the ultra-thin and light weight of the developed application.

In general, LCD products require high resolution and a large number of contact points. The arrangement of the glass panel and drive circuit process requires the ability for higher resolution.

In this respect, COG is one bonding method to make LCD products that require high resolution.

Hereinafter, a configuration of a conventional liquid crystal display device in which a chip is mounted in the COG method will be described with reference to the drawings.

2 is a cross-sectional view showing the configuration of a liquid crystal display device in which a driving circuit is mounted in a COG method.

As shown, one end of the liquid crystal panel D formed by bonding the first substrate 10 and the second substrate 20 with the liquid crystal layer 30 therebetween, that is, the gate pad or the data pad DP The driving circuit chip 50 is mounted on the formed portion.

One bumper 52a of the driving circuit chip 50 is bonded to the pad PD of the liquid crystal panel D, and the other bumper 52b is connected to a PCB substrate (not shown) and inputs a signal ( 60 is connected to serve to receive a signal input from the PCB substrate (not shown).

3 is a plan view schematically illustrating a planar configuration of the driving circuit chip.

As shown, the driving circuit chip 50 having the above-described function includes a first part I in which the IC chip is packed with resin and a bump connected to a lead frame (not shown) of the IC chip (not shown). It may be divided into a second part (II) consisting of 72a, 72b.

The plurality of bumpers 72a and 72b configured in the second part II have an input function for directly receiving a signal from the outside and an output for outputting a signal from the input signal through an IC chip. It will function.

Therefore, when the above-described driving circuit chip 50 is mounted on the LCD substrate, the bump 72b for the input function is connected to an external PCB substrate (not shown) to receive a signal. The bump 72a having the output function is connected one-to-one to the pad (not shown), and is input from the PCB substrate (not shown) and continuously receives a signal flowing through the packed IC chip to the pad (not shown). It will function to print.

The above-described driving circuit chip 50 generally aligns the bumps 72a and 72b and the pad portion of the chip 50 through a mechanical device, and then performs one-to-one bonding of the bumps and the pads. do.

However, bonding failures often occur due to mechanical errors during bonding.

This will be described with reference to FIG. 4.

4 is a cross-sectional view illustrating a bad state when bonding a glass substrate and a driving circuit chip of a liquid crystal panel.

As illustrated, the pad PD may be driven in an automated manner through an adhesive means such as an anisotropic conductive film (ACF) on the driving circuit chip 50 on the substrate 10 having the plurality of pads PD. Adhering to the process.

At this time, when the driving circuit chip 50 is attached, the driving circuit chip is often inclined in the vertical direction (long axis direction) due to a mechanical error.

In this case, when the bump 72 and the pad PD of the driving circuit chip 50 are attached, the contact resistance at the contact portion may be different because the attachment area is different from that of the normal.

Since the voltage value output from the driving circuit chip 50 to the pad is changed by the changed contact resistance between the bump 72 and the pad PD, the pixel area is deteriorated due to the changed signal. Will occur.

The present invention has been proposed for the purpose of solving the above-described problem, in order to prevent the driving circuit chip from tilting, by forming a tilt prevention pattern on the substrate and the driving circuit in the process of the driving circuit in contact with the pad Characterized in that not to tilt.

SUMMARY OF THE INVENTION The present invention has been proposed for the purpose of solving the problem, and the liquid crystal display according to the present invention includes a first substrate and a second substrate defined by a display area and a peripheral area positioned around the display area and including a driving circuit area. and; Gate wiring and data wiring crossing the first substrate so as to vertically intersect one surface of the first substrate to define a pixel region; A thin film transistor configured at an intersection point of the gate line and the data line; A pixel electrode configured in the pixel region; A gate pad configured at one end of the gate line corresponding to the non-display area, and a data pad configured at one end of the data line; A plurality of anti-tilt patterns configured in the driving circuit area; The driving circuit is mounted in the driving circuit region, and the tilt prevention pattern includes a driving circuit disposed below.

The anti-tilt pattern has a function of preventing the driving circuit chip from inclining in a process of contacting a pad (a gate pad and a data pad).

The height of the anti-tilt pattern disposed under the driving circuit chip is the same height as the sum of the height of the exposed height of the pad (gate pad, data pad) and the contact portion of the driving circuit chip.

The driving circuit chip may have a quadrangular shape, and the anti-tilt pattern may be located at a lower corner of the square driving circuit chip.

The thin film transistor may include a gate electrode connected to the gate wiring, a semiconductor layer positioned on the gate electrode, a source electrode connected to the data wiring while in contact with the semiconductor layer, and a drain electrode spaced apart from the source electrode. It includes.

The pixel electrode is made of a transparent conductive material.

A method of manufacturing a liquid crystal display device according to a first aspect of the present invention includes the steps of defining a display area on a first substrate and a second substrate, and a non-display area positioned around the display area and including a driving circuit area; Forming a gate line and a data line crossing the first substrate perpendicularly to one surface of the first substrate to define a pixel area; Forming a thin film transistor at an intersection point of the gate line and the data line; Forming a pixel electrode in the pixel region; Forming a gate pad at one end of the gate line corresponding to the non-display area and a data pad at one end of the data line; Forming a plurality of tilt prevention patterns in the driving circuit region; And mounting a driving circuit in which the anti-tilt pattern is located below the driving circuit region.

The anti-tilt pattern serves to prevent the driving circuit chip from being inclined in contact with the pad (gate pad or data pad).

The height of the anti-tilt pattern disposed under the driving circuit chip is equal to the height of the pad plus the height of the contact portion of the driving circuit chip.

The driving circuit chip may have a quadrangular shape, and the anti-tilt pattern may be located at a lower corner of the square driving circuit chip.

The thin film transistor may include a gate electrode connected to the gate wiring, a semiconductor layer positioned on the gate electrode, a source electrode connected to the data wiring while in contact with the semiconductor layer, and a drain electrode spaced apart from the source electrode. It includes.

According to a second aspect of the present invention, there is provided a liquid crystal display, comprising: defining a display area on a substrate and a non-display area including a driving circuit area around the display area; Forming a gate wiring connected to the display region in one direction and a gate electrode connected thereto, a gate pad at one end of the gate wiring corresponding to the non-display region, and a first metal pattern in the driving circuit region; ; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring, the gate pad, and the first metal pattern are formed; Forming a first semiconductor pattern and a second semiconductor pattern on the gate insulating layer corresponding to the gate electrode and the first metal pattern; A data line including a source electrode and a drain electrode in contact with the first semiconductor pattern, a data pad connected to the source electrode, extending in a direction perpendicular to the gate line, and at one end corresponding to the non-display area; Forming a second metal pattern on the first semiconductor layer; Forming and patterning a protective film on an entire surface of the substrate on which the source and drain electrodes, the data wiring, and the second metal pattern are formed, exposing the drain electrode and completely exposing the gate pad and the data pad; Forming a pixel electrode in contact with the drain electrode in the pixel region, a transparent gate pad terminal in contact with the gate pad, and a transparent data pad terminal in contact with the data pad.

And mounting a driving circuit in contact with the gate pad and the data pad corresponding to the non-display area.

The structure in which the first metal pattern, the gate insulating film, the second semiconductor pattern, the second metal pattern, and the protective film are stacked on the non-display area is located below a region other than the center region of the driving circuit. It functions as an anti-tilt pattern which prevents the furnace from tilting.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example

The present invention is characterized in that a tilt prevention pattern is formed on a glass substrate on which a driving circuit chip is to be mounted, corresponding to the four corners of the driving circuit chip.

Hereinafter, a configuration of a liquid crystal panel according to the present invention in which a driving circuit chip is mounted on a glass substrate will be described with reference to the drawings.

5 is an enlarged plan view of an enlarged side of a liquid crystal panel according to the present invention, and FIG. 6 is a cross-sectional view taken along the line II-II of FIG. 5.

As shown in FIG. 5 and FIG. 6, the liquid crystal panel S is formed by bonding the first substrate S1 and the second substrate S2 with a liquid crystal layer (not shown) interposed therebetween. A part of the second substrate S2 corresponding to is in a cut state.

In this configuration, the pad part PA configured at one end of the first substrate S1 may be exposed.

As shown in the drawing, a plurality of driving circuit chips 200 corresponding to the pad part PA are bonded to each other. At this time, a characteristic of the driving circuit chip 200 may be prevented from tilting at a portion corresponding to the four corners of the driving circuit chip 200. The pattern F is formed.

At this time, since the anti-tilt pattern F is configured to be higher than the pads 134 formed in the pad part PA, the anti-tilt pattern F is bonded in the process of bonding the driving circuit chip 200. Since no inclination occurs in the bumps 202 of the driving circuit chip, the pads may be exactly aligned.

Therefore, the pad 202 and the bump 202 of the driving circuit chip can be contacted with an accurate contact area.

In this case, the height of the anti-tilt pattern F is equal to the sum of the height of the pad viewed from the side and the contact portion of the driving circuit part in contact with the pad when the driving circuit chip contacts the pad part. Should be the same.

In the above-described configuration, the anti-tilt pattern F may be manufactured in a process of forming an existing first substrate (thin film transistor array substrate) rather than adding a separate process.

7 is an enlarged plan view showing a part of an array substrate for a liquid crystal display device according to the present invention including the bumps.

As illustrated, the thin film transistor array substrate S1 may be divided into a display area G1 and a non-display area G2 around the display area G1, and the glass substrate 100 corresponding to the display area G1. A plurality of gate lines 102 extending in one direction and spaced in parallel to each other are formed thereon, and a plurality of data lines 120 spaced apart from each other in parallel to the gate lines 102 in a direction perpendicular to each other. do.

In this case, an area defined by the intersection of the gate line 102 and the data line 120 is referred to as a pixel area P, and a gate electrode is formed at one side of the pixel area P, that is, at an intersection point of the two wires 102 and 120. A thin film transistor T composed of the 104, the active layer 112, the source electrode 116, and the drain electrode 118 is formed.

The pixel region P includes a transparent pixel electrode 130 in contact with the drain electrode 118.

The gate electrode 118 is connected to the gate wiring 102, and the source electrode 116 is configured to be connected to the data wiring 120.

In the non-display area G2, a gate pad 106 configured at one end of the gate line 102 and receiving a gate signal from the outside is configured, and the gate pad 106 is not parallel to an area in which the gate pad 106 is configured. A data pad 122 configured at one end of the data line 120 and receiving a data signal from the outside is formed in the non-display area G2 on the other side.

The transparent data pad terminal 134 and the transparent gate pad terminal 132 contacting the data pad 122 and the gate pad 106 are further configured.

In the above-described configuration, a plurality (not shown) of the aforementioned anti-tilt patterns F are formed to correspond to the spaced areas of the data pads and the gate pads 122 and 106.

The anti-tilt pattern F is formed to correspond to the corners of the driving circuit chip in a region where the driving circuit chip (not shown) is mounted.

Hereinafter, a manufacturing process of an array substrate for a liquid crystal display device according to the present invention configured as described above will be described.

8A to 8E, 9A to 9E, 10A to 10E, and 11A to 11E are cut along the lines III-III, IV-IV, V-V, VI-VI of FIG. It is process sectional drawing shown according to a process sequence.

8A to 8E are process flowcharts showing pixel regions, FIGS. 9A to 9E are process flowcharts showing gate pad portions, FIGS. 10A to 10E are process flowcharts showing data pad portions, and FIGS. 11A to 11E are inclined. It is process sectional drawing which shows the prevention pattern area | region.

As shown in FIGS. 8A, 9A, 10A, and 11A, the non-display area G2 is defined on the transparent insulating substrate 100 around the display area and the display area G1.

Aluminum (Al), aluminum alloy (for example, AlNd), chromium (Cr), tungsten (W), and molybdenum (eg, Al) on the entire surface of the substrate 100 in which the display area G1 non-display area G2 is defined Select one or more metals from the group of conductive metals including Mo), titanium (Ti), copper (Cu), and the like to form a first metal layer (not shown) on the entire surface of the substrate 100, followed by a first mask process. By patterning, a plurality of gate lines 102 including gate pads 106 at one end and extending in one direction and configured to be parallel to each other, and a gate electrode 104 connected to the gate lines 102 are formed.

At the same time, each of the first metal patterns 108 may correspond to the corners of the gate driving circuit chip (not shown) corresponding to the region in which the driving circuit chip (not shown) is mounted, corresponding to the non-display area G2. ).

In this case, when the gate wiring 102 is formed, a metal having a low resistance is used to prevent a signal delay. Examples of the metal include aluminum (Al) or copper (Cu).

When aluminum (Al) or copper (Cu) is used, an aluminum or glass substrate that is easily corroded to chemical liquids is formed by forming a separate buffer metal layer having high chemical resistance to corrosion or adhesion to the glass substrate at the upper or upper and lower portions thereof. It can also be configured to compensate for the disadvantages of copper with poor adhesion.

A gate insulating layer 110 is formed on the entire surface of the substrate 100 on which the gate wirings, the gate electrodes 102 and 104, and the first metal pattern 108 are formed.

The gate insulating layer 110 is formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO _X ).

8B, 9B, 10B, and 11B, an active layer 112 and an ohmic contact layer are formed on the gate insulating layer 110 corresponding to the gate electrode 104. 114 is formed on the gate insulating film 110 corresponding to the island-shaped metal pattern 108 formed in the non-display area G2, and is the same as the active layer 112 and the ohmic contact layer 114. The semiconductor pattern 116 is formed of a material.

In this case, the active layer 112 is formed by depositing amorphous silicon (a-Si: H), and the ohmic contact layer 114 is formed by depositing amorphous silicon containing n + or p + impurity ions.

As shown in FIGS. 8C, 9C, 10C, and 11C, aluminum (Al) is formed on the entire surface of the substrate 100 on which the active layer 112, the ohmic contact layer 114, and the semiconductor layer 118 are formed. ) And one or more metals selected from a group of conductive metals including aluminum alloys (AlNd), chromium (Cr), tungsten (W), molybdenum (Mo), molybdenum tungsten (MoW), copper (Cu), etc. Patterned, one end of the source electrode 116 and the drain electrode 118 spaced apart from each other while contacting the ohmic contact layer 114, and connected to the source electrode 116 and corresponding to the non-display area G2. The data line 120 having the data pads 122 is formed in the gate.

At the same time, an island-shaped second metal pattern 124 is formed on the semiconductor layer 116 formed in the non-display area G2.

8D and 9D, as shown in FIGS. 10D and 11D, silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) are included on the entire surface of the substrate 100 on which the source and drain electrodes 116 and 118 are formed. One of the group of inorganic insulating materials is deposited and patterned to form a passivation layer 126 having a drain contact hole 128 exposing a portion of the drain electrode 118.

In this case, in the process of patterning the passivation layer 126, a process of completely exposing the gate pad 106 and the data pad 122 corresponding to the non-display area G2 is performed.

However, the passivation layer 126 is left over the first metal pattern 108, the semiconductor layer 116, and the second metal pattern 124 in the non-display area G2.

As shown in FIGS. 8E, 9E, 10E and 11E, indium tin oxide (ITO) and indium zinc oxide (IZO) are included on the entire surface of the substrate 100 on which the passivation layer 126 is formed. Depositing and patterning one selected from a group of transparent conductive metals to form a transparent pixel electrode 130 positioned in the pixel region P while in contact with the drain electrode 118 and contacting the gate pad 106. A transparent gate pad terminal 132 is formed, and a transparent data pad terminal 134 in contact with the data pad 122 is formed.

In the above-described process, the first metal pattern, the gate insulating film, the semiconductor layer, the second metal pattern, and the protective film stacked corresponding to the non-display area function as the aforementioned anti-tilt pattern F.

Through the above-described process, an array substrate for a liquid crystal display device including the driving circuit chip anti-tilt pattern according to the present invention can be manufactured.

As described above, the liquid crystal display device according to the present invention has a configuration in which the driving circuit chip is directly attached to the substrate, and inclined to a portion corresponding to the four corners of the driving circuit chip in correspondence to the region where the driving circuit chip is attached. Characterized in that the load prevention pattern, in this case, even if the driving circuit chip is inclined due to a mechanical error in the process of bonding the drive circuit chip to the panel can be caught directly by the tilt prevention pattern. have.

Therefore, the bumps of the driving circuit chip and the pads of the liquid crystal panel may be attached with a constant contact area, so that the contact resistance becomes uniform, thereby stabilizing the image quality of the liquid crystal panel.

1 is a diagram showing the configuration of a general liquid crystal display device;

2 is a cross-sectional view schematically showing the configuration of a liquid crystal display according to the related art in which a driving circuit is mounted in a COG method.

3 is a plan view schematically illustrating a configuration of a driving circuit chip;

4 is a cross-sectional view illustrating a shape in which a driving circuit chip is mounted on a substrate;

5 is a cross-sectional view schematically showing the configuration of a liquid crystal display device according to the present invention in which a driving circuit is mounted in a COG method.

6 is a cross-sectional view taken along the line II-II of FIG. 5,

7 is an enlarged plan view illustrating an enlarged portion of an array substrate for a liquid crystal display device according to the present invention;

8A to 8E, 9A to 9E, 10A to 10E, and 11A to 11E are cut along the lines III-III, IV-IV, V-V, VI-VI of FIG. It is process sectional drawing shown in process sequence.

<Brief description of symbols for the main parts of the drawings>

S: liquid crystal panel S1: first substrate (array substrate)

S2: second substrate (color filter substrate) 200: drive circuit chip

F: Tilt prevention pattern

Claims (16)

A first substrate and a second substrate defined by a display area and a peripheral area positioned around the display area and including a driving circuit area; Gate wiring and data wiring crossing the first substrate so as to vertically intersect one surface of the first substrate to define a pixel region; A thin film transistor configured at an intersection point of the gate line and the data line; A pixel electrode configured in the pixel region; A gate pad configured at one end of the gate line corresponding to the non-display area, and a data pad configured at one end of the data line; A plurality of anti-tilt patterns configured in the driving circuit area; A driving circuit mounted in the driving circuit region and having the anti-tilt pattern below Liquid crystal display comprising a. The method of claim 1, And the anti-tilt pattern has a function of preventing the driving circuit chip from being inclined in contact with pads (gate pads and data pads). The method of claim 1, And the height of the anti-tilt pattern disposed under the driving circuit chip is equal to the height of the sum of the exposed height of the pad (gate pad and data pad) and the height of the contact portion of the driving circuit chip. The method of claim 1, The driving circuit chip has a quadrangular shape, and the anti-tilt pattern is located under the four corners of the square driving circuit chip. The method of claim 1, The thin film transistor may include a gate electrode connected to the gate wiring, a semiconductor layer positioned on the gate electrode, a source electrode connected to the data wiring while in contact with the semiconductor layer, and a drain electrode spaced apart from the source electrode. Liquid crystal display comprising a. The method of claim 1, The pixel electrode is made of a transparent conductive material. Defining a display area on the first substrate and the second substrate and a non-display area positioned around the display area and including a driving circuit area; Forming a gate line and a data line crossing the first substrate perpendicularly to one surface of the first substrate to define a pixel area; Forming a thin film transistor at an intersection point of the gate line and the data line; Forming a pixel electrode in the pixel region; Forming a gate pad at one end of the gate line corresponding to the non-display area and a data pad at one end of the data line; Forming a plurality of tilt prevention patterns in the driving circuit region; Mounting a driving circuit in which the inclination prevention pattern is located in correspondence with the driving circuit region; Liquid crystal display device manufacturing method comprising a. The method of claim 7, wherein And the anti-tilt pattern prevents the driving circuit chip from being inclined in contact with the pad (gate pad or data pad). The method of claim 7, wherein And the height of the anti-tilt pattern disposed under the driving circuit chip is equal to the height of the pad plus the height of the contact portion of the driving circuit chip. The method of claim 7, wherein The driving circuit chip has a quadrangular shape, and the anti-tilt pattern is located in the lower corner of the rectangular driving circuit chip manufacturing method of a liquid crystal display device. The method of claim 7, wherein The thin film transistor may include a gate electrode connected to the gate wiring, a semiconductor layer positioned on the gate electrode, a source electrode connected to the data wiring while in contact with the semiconductor layer, and a drain electrode spaced apart from the source electrode. Liquid crystal display device manufacturing method comprising a. Defining a display area on the substrate and a non-display area including a driving circuit area around the display area; Forming a gate wiring connected to the display region in one direction and a gate electrode connected thereto, a gate pad at one end of the gate wiring corresponding to the non-display region, and a first metal pattern in the driving circuit region; ; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring, the gate pad, and the first metal pattern are formed; Forming a first semiconductor pattern and a second semiconductor pattern on the gate insulating layer corresponding to the gate electrode and the first metal pattern; A data line including a source electrode and a drain electrode in contact with the first semiconductor pattern, a data pad connected to the source electrode, extending in a direction perpendicular to the gate line, and at one end corresponding to the non-display area; Forming a second metal pattern on the first semiconductor layer; Forming and patterning a protective film on an entire surface of the substrate on which the source and drain electrodes, the data wiring, and the second metal pattern are formed, exposing the drain electrode and completely exposing the gate pad and the data pad; Forming a pixel electrode in a pixel region in contact with the drain electrode, a transparent gate pad terminal in contact with the gate pad, and a transparent data pad terminal in contact with the data pad; Array substrate manufacturing method for a liquid crystal display comprising a. The method of claim 12, And mounting a driving circuit in contact with the gate pad and the data pad corresponding to the non-display area. The method of claim 13, The structure in which the first metal pattern, the gate insulating film, the second semiconductor pattern, the second metal pattern, and the protective film are stacked on the non-display area is located below a region other than the center region of the driving circuit. A method of manufacturing an array substrate for a liquid crystal display device, which functions as an anti-tilt pattern which prevents the furnace from tilting. The method of claim 13, The pixel electrode, the gate pad terminal, and the data pad terminal are formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO). The method of claim 12, The first semiconductor pattern and the second semiconductor pattern is a method of manufacturing an array substrate for a liquid crystal display device in which a pure amorphous silicon (a-Si: H) layer and an impurity amorphous silicon (n + a-Si: H) layer is stacked.