KR20060045269A - Method for preventing electrostatic in fabricating array substrate of lcd - Google Patents

Abstract

The present invention relates to a method of preventing static electricity when manufacturing an array substrate of a liquid crystal display device which can improve productivity by reducing a defective rate caused by static electricity generated during an array process. The method includes forming a plurality of gate lines arranged in one direction on a glass substrate, a first connection line connecting the gate lines, and a first contact pattern connected to the first connection line at an outer corner of the glass substrate. step; Forming an active layer on the resulting product; A plurality of S / D lines vertically intersecting with the gate line on the active layer, a second connection line connecting S / D lines, and a second connection line corresponding to the first contact pattern and connected to the second connection line; Forming a contact pattern; And directly contacting the first contact pattern and the second contact pattern.

Description

Method for preventing electrostatic in fabricating array substrate of LCD for manufacturing an array substrate of a liquid crystal display device

1A to 1C are plan views illustrating an antistatic method when manufacturing an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

2A to 2C are plan views illustrating an antistatic method in manufacturing an array substrate of a liquid crystal display according to another exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10, 20: glass substrate 11, 21: gate line

11a and 21a: first connection line 11b and 21b: first contact pattern

12, 23: S / D line 12a, 23a: second connection line

12b and 23b: second contact pattern 22: active layer

A, B: cutting part

The present invention relates to a method of manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method of preventing static electricity when manufacturing an array substrate of a liquid crystal display device which can improve productivity by reducing a defective rate caused by static electricity generated during an array process. It is about.

The liquid crystal display has been developed in place of the CRT on the basis of its advantages of being light and simple, low voltage driving and low power consumption. In particular, the thin film transistor liquid crystal display (TFT-LCD) realizes high quality, large size and colorization comparable to the CRT. Recently, it is used in various fields as well as notebook PC and monitor market.

The TFT-LCD has a structure in which an array substrate provided with TFT and pixel electrodes, and a color filter substrate provided with a color filter and a counter electrode are bonded under the interposition of the liquid crystal layer. In a TFT-LCD, it is very important to reduce the number of manufacturing steps thereof, in particular, the number of manufacturing steps of the array substrate. This is because as the number of manufacturing processes is reduced, the manufacturing cost of the TFT-LCD can be reduced, because a larger amount of TFT-LCD can be supplied at a lower price.

The reduction in the number of manufacturing processes is usually realized by the reduction in the number of mask processes, and recent TFT-LCDs are manufactured through a 5-mask process. The mask process is a process of forming a photoresist pattern which is an etch mask through photoresist coating, exposure and development processes.

Hereinafter, a method of manufacturing an array substrate using a 5-mask process will be described.

First, after depositing a first metal film for a gate on a glass substrate, the first metal film is patterned by a first mask process to form a gate wiring including a gate.

Then, an amorphous silicon (hereinafter referred to as "a-Si") film and a doped amorphous silicon (hereinafter referred to as "n + a-Si") and a doped amorphous silicon film are formed on the entire surface of the substrate so as to cover the gate wiring. After the films are sequentially deposited, the n + a-Si film and the a-Si film are patterned by a second mask process to form an active layer.

Next, after depositing a second metal film for S / D (source / drain) on the gate insulating film including the active layer, the second metal film is patterned by a third mask process to form S / D to form a TFT, In addition, an active wiring is formed below the data wiring.

Subsequently, after the protective film is coated on the entire area of the glass substrate including the TFT, the gate wiring and the data wiring, a via hole is formed through the fourth mask process to etch the protective film to expose the S / D. To expose the pads.

Then, after depositing an ITO film on the protective film including a via hole, the ITO film is patterned by a fifth mask process to form a pixel electrode on the protective film, and as a result, fabrication of the array substrate is completed.

The conventional array substrate completed through such a manufacturing process is a method for preventing defects caused by static electricity generated in the process, and constitutes an electrostatic protection circuit in each of the gate pad portion and the data pad portion. However, in the antistatic method according to the related art, since the static electricity protection circuit is completed only by performing the ITO process, that is, the fifth mask process, to form the pixel electrode, when static electricity is generated in the previous process, for example, the gate and the S When static electricity is generated between the layers of / D, there is a problem that can not be vulnerable to static electricity because there is no circuit that can disperse such static electricity.

Accordingly, the present invention was created to solve the above problems inherent in the antistatic method in manufacturing an array substrate of a liquid crystal display device according to the prior art, and an object of the present invention is to provide an interlayer between a gate and an S / D. The present invention provides a method of preventing static electricity during fabrication of an array substrate of a liquid crystal display device which can improve productivity by reducing a defective rate caused by static electricity generated in the semiconductor device.

In order to achieve the above object, according to one aspect of the present invention, there is provided a method of preventing static electricity when manufacturing an array substrate of a liquid crystal display device: This method comprises a plurality of gate lines, gate lines arranged in one direction on a glass substrate; Forming a first connection line for connecting and a first contact pattern connected to the first connection line at an outer corner of the glass substrate; Forming an active layer on the resulting product; A plurality of S / D lines vertically intersecting with the gate line on the active layer, a second connection line connecting S / D lines, and a second connection line corresponding to the first contact pattern and connected to the second connection line; Forming a contact pattern; And directly contacting the first contact pattern and the second contact pattern.

According to another aspect of the invention, the direct contact between the first contact pattern and the second contact pattern is made by laser welding.

According to another aspect of the invention, the direct contact of the first contact pattern and the second contact pattern is performed in one or more of the four parts to which they correspond.

According to another aspect of the present invention, the method further includes, after the step of directly contacting the first contact pattern and the second contact pattern, the first and second contact patterns directly contacted portions before a subsequent array test. And cutting an adjacent second connecting line portion.

According to another aspect of the present invention, the cutting step is performed at one or more second connection lines among the second connection lines adjacent to the portions where the first and second contact patterns are directly contacted.

According to another aspect of the present invention, a plurality of gate lines arranged in one direction on a glass substrate, a first connection line connecting the gate lines and a first contact connected to the first connection line at the outer corner of the glass substrate Forming a pattern; Forming an active layer on the resultant obtained by using a shadow mask covering an outer portion of the glass substrate including the first contact pattern; And a plurality of S / D lines vertically intersecting with the gate line on the active layer, a second connection line connecting S / D lines, and directly contacting the first contact pattern to be connected to the second connection line. And forming a second contact pattern.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1C are plan views illustrating an antistatic method when manufacturing an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

An antistatic method in manufacturing an array substrate of a liquid crystal display device according to an embodiment of the present invention, as shown in Figure 1a, by depositing a gate first metal film (not shown) on the glass substrate 10 Subsequently, the first metal layer is patterned by a first mask process to form a plurality of gate lines 11 arranged in one direction and a first connection line 11a connecting the gate lines 11, and at the same time, the glass substrate 10. The first contact pattern 11b connected to the first connection line 11a is formed at the outer corner portion of the bottom line.

Next, although not shown in the drawings, a gate insulating film, an undoped amorphous silicon (a-Si) film, and a doped amorphous silicon (n + a-Si) film were sequentially deposited on the entire surface of the resultant, and then n + was subjected to the second mask process. The a-Si film and the a-Si film are patterned to form an active layer.

Subsequently, as illustrated in FIG. 1B, after depositing a second metal film (not shown) for S / D on the gate insulating film including the active layer, the second metal film is patterned by a third mask process to form a gate line 11. ) And a second connection line 12a connecting the plurality of S / D lines 12 and the S / D lines 12 that are vertically intersected with each other, and at the outer corner of the glass substrate 10. A second contact pattern 12b is formed to correspond to the first contact pattern 11b and to be connected to the second connection line 12a.

Thereafter, the first contact pattern 11b and the second contact pattern 12b are welded with a laser to directly contact the first contact pattern 11b and the second contact pattern 12b. Laser welding of the first contact pattern 11b and the second contact pattern 12b is performed at one or more of the four parts to which they correspond.

When the first and second contact patterns 11b and 12b are directly contacted by laser welding, an electrical equipotential is formed between the gate and the S / D layer, so that a short between the gate and the S / D layer due to static electricity is generated. Is prevented.

Subsequently, although not shown in the figure, fabrication of the array substrate is completed through the remaining fourth and fifth mask processes.

Subsequently, as indicated by reference numeral A of FIG. 1C, a portion of the second connection line 12a adjacent to the portions where the first contact pattern 11b and the second contact pattern 12b are directly contacted may be formed. The laser is cut before the array test. If the array test is not performed, it may be cut at the time of cell scribing. Or you may cut | disconnect at the time of the ITO etching process in a 5th mask process. In this case, the first and second contact patterns 11b and 12b cut one or more second connection lines 12a among the second connection lines 12a adjacent to the directly contacted portions.

2A to 2C are plan views illustrating an antistatic method in manufacturing an array substrate of a liquid crystal display according to another exemplary embodiment of the present invention.

In the method of preventing static electricity when manufacturing an array substrate of a liquid crystal display according to another exemplary embodiment of the present invention, as shown in FIG. 2A, a gate first metal film (not shown) is deposited on a glass substrate 20. Subsequently, the first metal layer is patterned by a first mask process to form a plurality of gate lines 21 arranged in one direction and a first connection line 21a connecting the gate lines 21, and at the same time, the glass substrate 20. The first contact pattern 21b connected to the first connection line 21a is formed at the outer corner portion of the substrate.

Next, as shown in FIG. 2B, a gate insulating film (not shown) is formed by using a shutter or a shadow mask (not shown) covering the outer portion of the glass substrate 20 including the first contact pattern 21b on the resultant. ), An a-Si film, and an n + a-Si film are sequentially deposited, and then the n + a-Si film and the a-Si film are patterned by a second mask process to form the active layer 22, thereby forming the first contact pattern 21b. The gate insulating film and the active layer 22 are not formed on the substrate.

Subsequently, as illustrated in FIG. 2C, a second metal film (not shown) for S / D is deposited on the gate insulating film including the active layer 22, and then the second metal film is patterned by a third mask process. The outer corner of the glass substrate 20 is formed while forming a plurality of S / D lines 23 vertically intersecting with the line 21 and a second connection line 23a connecting the S / D lines 23. A second contact pattern 23b connected to the second connection line 23a is formed at the portion of the second contact pattern 23b while being in direct contact with the first contact pattern 21b.

As such, when the first and second contact patterns 21b and 23b directly contact each other, an electrical equipotential is formed between the gate and the S / D layer, and a short between the gate and the S / D layer due to static electricity is prevented.

Thereafter, after fabrication of the array substrate through the fourth and fifth mask processes, as shown by reference numeral B, the four first contact patterns 21b and the second contact patterns 23b are directly contacted. The portion of the second connecting line 23a adjacent to the portions is cut using a laser before subsequent array testing. If the array test is not performed, it is enough to cut at the time of cell scribing. Or you may cut | disconnect at the time of the ITO etching process in a 5th mask process. In this case, the first and second contact patterns 21b and 23b cut at least one portion of the second connection line 23a among the second connection lines 23a adjacent to the directly contacted portions.

According to the above-described configuration of the present invention, the gate and the S / D layer is directly contacted at the outer side of the glass substrate to form an electrical equipotential between the gate and the S / D layer, thereby preventing short circuit due to the generation of static electricity between these layers can do. This is to prevent the static electricity before the fifth mask process can reduce the failure rate caused by static electricity to improve productivity.

While the invention has been shown and described with respect to certain preferred embodiments thereof, the invention is not so limited and it is intended that the invention be limited without departing from the spirit or field of the invention as set forth in the following claims It will be readily apparent to one of ordinary skill in the art that various modifications and variations can be made.

Claims (6)

In the antistatic method when manufacturing the array substrate of the liquid crystal display device, Forming a plurality of gate lines arranged in one direction on the glass substrate, a first connection line connecting the gate lines, and a first contact pattern connected to the first connection line at an outer corner of the glass substrate; Forming an active layer on the resulting product; A plurality of S / D lines vertically intersecting with the gate line on the active layer, a second connection line connecting S / D lines, and a second connection line corresponding to the first contact pattern and connected to the second connection line; Forming a contact pattern; And And directly contacting the first contact pattern and the second contact pattern. The method of claim 1, And wherein the direct contact between the first contact pattern and the second contact pattern is made by laser welding. The method of claim 1, Wherein the direct contact of the first contact pattern and the second contact pattern is performed at one or more of the four parts to which they correspond. The method of claim 1, The method may further include, after the step of directly contacting the first contact pattern and the second contact pattern, a second connection line portion adjacent to the portions where the first and second contact patterns are directly contacted before a subsequent array test. Cutting step; characterized in that it further comprises. The method of claim 4, wherein The cutting step is characterized in that the first and second contact pattern is performed in one or more second connection line of the second connection line adjacent to the parts directly contacted. In the antistatic method when manufacturing the array substrate of the liquid crystal display device, Forming a plurality of gate lines arranged in one direction on the glass substrate, a first connection line connecting the gate lines, and a first contact pattern connected to the first connection line at an outer corner of the glass substrate; Forming an active layer on the resultant obtained by using a shadow mask covering an outer portion of the glass substrate including the first contact pattern; And A plurality of S / D lines vertically intersecting with the gate line on the active layer, a second connection line connecting S / D lines, and a second contact line directly contacting the first contact pattern and connected to the second connection line; Forming a contact pattern; and a method of preventing static electricity when manufacturing an array substrate of a liquid crystal display device.

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