KR100979118B1 - Semiconductor device and layout method of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a gate electrode formed on an active region, and to a layout method thereof, wherein two or more gate electrodes having different lengths are integrally formed on the same active region to correspond to the gate electrodes. The transistor regions are formed.

Description

Semiconductor device and layout method thereof {SEMICONDUCTOR DEVICE AND LAYOUT METHOD OF THE SAME}

1 is a diagram illustrating a conventional short MOS transistor.

2 is a view showing a conventional long MOS transistor.

3 is a diagram illustrating a general driving delay circuit using a MOS transistor.

4 shows a conventional layout structure for FIG.

5A to 5E are views showing a semiconductor device of the present invention.

6 shows a layout structure of the present invention with respect to FIG.

7 is a view showing a bootstrap circuit using the semiconductor device of the present invention.

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a gate electrode formed on an active region and a layout method thereof.

In general, MOS transistors may be used in various applications in semiconductor devices, and MOS transistors having different gate lengths may be used depending on the purpose.

For example, when a MOS transistor is used for a drive, a MOS transistor having a short gate G length L1 is conventionally used to draw only the driving capability as shown in FIG. 1.

When the MOS transistor is used for a capacitor, as shown in FIG. 2, a MOS transistor having a long gate G length L2 is used to maximize the capacitor capacity.

However, in the case of a circuit which continuously performs driving and charging / discharging by using a MOS transistor, a MOS transistor having a short gate length L1 as shown in FIG. 1 and a gate length as shown in FIG. A MOS transistor with a long L2) must be used continuously.

That is, in the case of the delay driving circuit which delay-drives the input signal IN and outputs the output signal OUT as shown in FIG. Including the MOS capacitors (PM2, NM2, PM4, NM4, PM6, NM6) connected between INV1, INV3, INV5, INV7 and each inverter (INV1, INV3, INV5, INV7).

In the case of such a delay driving circuit, as shown in FIG. 4, a short gate length for pull-ups provided in the inverter chains INV1, INV3, INV5, and INV7 in the N type well region 10 is shown. Morse transistors PM1, PM3, PM5, PM7 and PMOS transistors PM2, PM4, PM6 having a long gate length having a capacitor structure are alternately formed, and an inverter chain is formed in the P type well region 20. NMOS transistors NM1, NM3, NM5, NM7 having short gate lengths for pull-down, respectively, provided at (INV1, INV3, INV5, INV7), and NMOS transistors NM2 having long gate lengths having a capacitor structure. , NM4, NM6) has a layout structure formed alternately.

That is, in the conventional circuit that uses various electrical characteristics according to the gate length of the MOS transistor, an active pattern in which a MOS transistor having a short gate length for driving a signal and a MOS transistor having a long gate length for a capacitor operation or the like are independent of each other Laid out separately to have.

Therefore, the layout area is increased, so that the number of net dies, that is, the number of chips produced in one wafer, may be reduced, thereby reducing the price competitiveness of the chips.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having all of various electrical characteristics according to gate length while occupying a small layout area.

Another object of the present invention is to reduce the layout area of a circuit that continuously performs driving and charging / discharging using a semiconductor device such as a MOS transistor.

Still another object of the present invention is to reduce the layout area of a semiconductor circuit using various electrical characteristics according to the gate length, thereby securing the price competitiveness of the semiconductor chip.

According to an embodiment of the present invention, two or more gate electrodes having different lengths are integrally formed on the same active region, thereby forming transistor regions corresponding to the respective gate electrodes. It features.

In addition, in the semiconductor device according to another aspect of the present invention for achieving the above object, the first and second transistor regions are formed integrally with the first and second gate electrodes of different lengths on the same active region. And a first source and a drain corresponding to the first transistor region are commonly connected to each other, thereby driving the second transistor by charging and discharging the first transistor region.

In accordance with an aspect of the present invention, there is provided a method of laying out a semiconductor device, by forming two or more gate electrodes having different lengths integrally on the same active region, thereby corresponding to the respective gate electrodes. Are formed.

In addition, the layout method of a semiconductor device according to another aspect of the present invention for achieving the above object comprises the steps of forming an active region; Forming first and second gate electrodes of different lengths integrally on the active region; And forming a first source and a drain region and a second source and a drain region on both sides of the first and second gate electrodes, respectively, thereby forming a first transistor region comprising the first gate, source, and drain. And a second transistor region including the second gate, the source, and the drain.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention provides a semiconductor device in which two or more gate electrodes having different lengths are integrated on one active region, so that various transistor operations may be performed in correspondence with the respective gate electrodes.

Specifically, the semiconductor device of the present invention may have a layout structure as shown in FIGS. 5A to 5E.

First, referring to FIG. 5A, according to the first embodiment of the present invention, a gate pattern GP in which two gate electrodes G3 and G4 having different lengths are integrally formed, and the source and drain regions S, D) may be formed of an active pattern AP.

In the gate pattern GP, a short gate electrode G3 and a long gate electrode G4 are integrally formed, and one side of each gate electrode G3 and G4 is aligned on the same line in the width direction. Do. Here, the gate electrode G4 has a length 'L5' longer by 'L4' than the length 'L3' of the gate electrode G3, and each gate electrode G3 and G4 has a bar shape.

The active pattern AP includes a channel region overlapping the gate pattern, and a source region S and a drain region D formed at both sides of the channel region. Here, the active pattern AP includes a channel region overlapping the gate electrode G3 and has an active region having a length corresponding to the gate electrode G3, and a channel region overlapping the gate electrode G4. It consists of an active region having a length corresponding to the gate electrode G4.

Next, as shown in FIG. 5B, two gate electrodes G3 and G4 having different lengths, a predetermined portion of one side of the gate electrode G3, and one side of the gate electrode G4 are illustrated as shown in FIG. 5B. A semiconductor device having a gate pattern GP having a triangular auxiliary gate electrode G5 having both sides of a predetermined portion integrally formed thereon may be disclosed.

That is, the gate pattern GP may include a gate electrode G3 having a short length such as 'L3', a gate electrode G4 having a long length such as 'L5', and two gate electrodes G3 having two different lengths. G4) A triangular auxiliary gate electrode G5 located at a portion perpendicular to each other while being in contact with each other is formed integrally.

The active pattern AP has the same layout structure as the active pattern AP of FIG. 5A.

In the semiconductor device having the layout structure according to the second exemplary embodiment of the present invention, the gate pattern GP process is further performed by removing the bending portion generated by the contact between the two gate electrodes G3 and G4 as the auxiliary gate electrode G5. There is an effect that can be made easily.

Next, as a third embodiment of the present invention, as shown in FIG. 5C, a semiconductor device including a gate pattern GP having the same structure as that of FIG. 5A and a rectangular active pattern AP may be disclosed. . Here, the active pattern AP has a rectangular layout structure regardless of the shape of the gate pattern AP.

Next, as shown in FIG. 5D, as shown in FIG. 5D, a gate pattern GP having two gate electrodes G3a and G3b and a gate electrode G4 integrally formed thereon, and a rectangular active pattern AP Disclosed is a semiconductor device consisting of a).

Here, the gate electrode G4 is positioned between the two gate electrodes G3, and the two gate electrodes G3 have a short length, such as 'L3', and the gate electrode G4 has a long length, such as 'L4'. Have

Next, as a fifth embodiment of the present invention, as shown in FIG. 5E, a gate pattern in which two gate electrodes G3a and G3b, a gate electrode G4, and two auxiliary gate electrodes G5a and G5b are integrally formed. A semiconductor device including a GP and a rectangular active pattern AP may be disclosed.

Here, the gate electrode G4 is positioned between the two gate electrodes G3 as shown in FIG. 5D, and the two gate electrodes G3 have a short length, such as 'L3', and the gate electrode G4 has a length of 'L4' and the like. As long as

Further, the auxiliary gate electrode G5a has a triangular structure in which one side predetermined portion of the gate electrode G3a and one side predetermined portion of the gate electrode G4 are both sides, and one side predetermined portion and the gate electrode of the auxiliary gate electrode G5b are formed. It has a triangular structure which makes the other side predetermined part of (G4) both sides.

As described above, the semiconductor device of the present invention may be composed of an active pattern AP and a gate pattern GP having two or more gate electrodes having different lengths formed on the active pattern AP. The pattern AP and the gate pattern GP may have various structures as shown in FIGS. 5A to 5E.

When the gate pattern GP including two or more gate electrodes having different lengths is integrally formed on one active pattern AP, one MOS transistor may have all electrical characteristics according to the gate length. This has the effect of being reduced.

For example, when the semiconductor device of the present invention having a gate pattern in which a long gate electrode and a short gate electrode are integrally formed is applied to the circuit of FIG. 3, the circuit of FIG. 3 has a layout structure as shown in FIG. 6. Can be.

Referring to FIG. 6, the delay driving circuit of the present invention includes an N type well region 10 and a P type well region 20 disposed adjacent to each other, and an inverter INV1 is disposed in the N type well region 10. PMOS transistors PM1, PMOS capacitors PM2, PM4, and PM6 and PMOS transistors provided in the inverters INV3, INV5, and INV7 are arranged in pairs to form PMOS transistors PM1, PM4, and PMV, respectively. Transistors PM8 to PM10 are formed. In the P type well region 20, the NMOS transistor NM1 provided in the inverter INV1, the NMOS capacitors NM2, NM4, NM6, and the NMOS provided in the inverters INV3, INV5, INV7. The transistors are paired to form NMOS transistors NM8 to NM10 laid out in one active pattern. Here, each of the PMOS transistors PM8 to PM10 and the NMOS transistors NM8 to NM10 may correspond to the semiconductor device of the present invention, and may include a gate having a short length corresponding to the inverters INV3, INV5, and INV7. The long gate corresponding to the capacitors PM2, NM2, PM4, NM4, PM6 and NM6 has an integrated gate pattern structure.

In addition, the gate of the PMOS transistor PM1 and the gate of the NMOS transistor NM1 are electrically connected to each other through a wiring, and the source of the PMOS transistor PM1 is electrically connected to the power supply voltage line VDDL. The source of the NMOS transistor NM1 is electrically connected to the ground voltage line VSSL.

In addition, the drain and the gate of the PMOS and NMOS transistors PM8 and NM8 formed on one side of the shorter gate electrode in the PMOS and NMOS transistors PM1 and NM1 are electrically connected to each other through a wiring. In the MOS and NMOS transistors PM8 and NM8, the drain and the gates of the PMOS and NMOS transistors PM9 and NM9 formed on one side of the shorter gate electrode are electrically connected to each other through wiring. In the MOS transistors PM9 and NM9, the drain formed on one side of the shorter gate electrode and the gates of the PMOS and NMOS transistors PM10 and NM10 are electrically connected to each other through a wiring.

In addition, the source formed at the other side of the short gate electrode in each of the PMOS transistors PM8 to PM10, and the source and the drain formed at both sides of the long gate electrode are electrically connected to the power supply voltage line VDDL. In each of the NMOS transistors NM8 to NM10, the source formed on the other side of the short gate electrode and the source and drain formed on both sides of the long gate electrode are electrically connected to the ground voltage line VSSL.

In the delay drive circuit of the present invention having such a layout structure, the inverters INV3, INV5, and INV7 of FIG. 3 and the MOS capacitors PM2, NM2, PM4, NM4, PM6, and NM6 are paired with each other on one active pattern. Since it is formed of a semiconductor device having two gate electrodes integrated, there is an effect of reducing the layout area as shown by the dotted line portion 30 of FIG.

As another example of a circuit to which the semiconductor device of the present invention is applied, the bootstrap circuit of FIG. 7 may be provided. Here, the bootstrap circuit is mainly used to transfer a signal having a boosted voltage VPP level for driving a word line without a threshold voltage loss in a semiconductor memory device such as a DRAM.

That is, referring to FIG. 7, the bootstrap circuit of the present invention transmits the signal SIG1 to the boot node BN in response to the signal SIG2 and charges / discharges the NMOS transistor NM11 and the boot node BN. An NMOS transistor NM12 for pulling up the output SIG5 to the signal SIG3 level in response to a potential of the NMOS transistor NM13 for pulling down the output SIG5 to the signal SIG4 level in response to the signal / SIG1 inverting the signal SIG1. It includes.

Here, when the bootstrap circuit is used in the word line driving circuit of the DRAM, the signals SIG1 may correspond to the word line control signal, two signals SIG2 and SIG3 may correspond to the boosted voltage VPP, and the signal SIG4 may be the ground voltage. It may correspond to VSS, and the signal SIG5 may correspond to a word line driving signal.

The bootstrap circuit of the present invention having such a configuration pumps the boot node BN to a level higher than the signal SIG3 level in order to deliver the signal SIG3 to the output SIG5 without losing the NMOS transistor threshold voltage.

To this end, the NMOS transistor NM11 drives the signal SIG1 in response to the signal SIG2 and simultaneously charges / discharges the signal SIG2. That is, the NMOS transistor NM11 must have both a driving capability and a capacitor component, and the NMOS transistor NM11 can be implemented as the semiconductor device of the first to fifth embodiments of the present invention. In this case, since the layout area of the NMOS transistor NM11 may be reduced, the layout area occupied by the bootstrap circuit in a semiconductor device such as a DRAM may be reduced.

The present invention provides a semiconductor device in which two or more gate electrodes having different lengths are integrally formed on the same active region, thereby reducing the layout area while including all the electrical characteristics according to the gate length.

In addition, in the circuit for continuously driving and charging / discharging a predetermined signal, the short gate electrode for driving and the long gate electrode for charging / discharging are integrally formed on the same active region. As formed, the layout area of the circuit can be reduced.

In addition, the present invention, in the semiconductor circuit using a variety of electrical characteristics according to the gate length, by implementing the MOS transistors having different gate lengths provided in the semiconductor circuit as a semiconductor device having a single active pattern and the gate pattern, As the layout area of the circuit is reduced, the net die can be improved, and thus, the semiconductor chip can have a price competitiveness.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (34)

By forming two or more gate electrodes of different lengths integrally on one active region, transistor regions are formed corresponding to the respective gate electrodes, The gate electrode may include a first gate electrode, a second gate electrode having a longer length than the first gate electrode, and a predetermined portion of one side of the first gate electrode and the second gate electrode while being integral with the first and second gate electrodes. Triangular auxiliary gate electrode having one side of the gate electrode as a predetermined side Semiconductor device comprising a. The method of claim 1, One side of each gate electrode is aligned with the same line in the width direction. delete The method of claim 1, The active region is divided into a first region in which the first gate electrode is formed and a second region in which the second gate electrode is formed, and the second region has a length longer than that of the first region. Semiconductor device. The method of claim 1, And the first and second gate electrodes have a bar shape. delete By forming two or more gate electrodes of different lengths integrally on one active region, transistor regions are formed corresponding to the respective gate electrodes, The gate electrode may be integrally formed with first and second gate electrodes having a channel region having the same length and a third gate electrode having a length longer than that of the first and second gate electrodes. A triangular first auxiliary gate electrode which is integral with the first and third gate electrodes and has one side predetermined portion of the first gate electrode and one side predetermined portion of the third gate electrode, and the second and third A triangular second auxiliary gate electrode which is integral with the gate electrode and has one side predetermined portion of the second gate electrode and one side predetermined portion of the third gate electrode as both sides. Semiconductor device comprising a. The method of claim 7, wherein And the first to third gate electrodes have a bar shape. delete First and second transistor regions having different lengths are integrally formed on one active region to form first and second transistor regions, A triangular auxiliary gate electrode is formed on the active region integrally with the first and second gate electrodes and has one side predetermined portion of the first gate electrode and one side predetermined portion of the second gate electrode as both sides. The first device and the drain corresponding to the first transistor region is connected in common, the semiconductor device, characterized in that the driving of the second transistor by the charge and discharge of the first transistor region. The method of claim 10, The first source is connected to a boot node, and is applied to a bootstrap circuit in which charging and discharging is performed as a first signal is input to the first gate electrode, thereby driving a second signal input to the first drain. Semiconductor device. The method of claim 10, And any one of a second source and a drain corresponding to the second transistor region is commonly connected to the first source and the drain. The method of claim 10, And the first gate electrode has a length longer than that of the second gate electrode. The method of claim 13, The active region is divided into a first region in which the first gate electrode is formed and a second region in which the second gate electrode is formed, and the second region has a length longer than that of the first region. Semiconductor device. The method of claim 13, One side of the first and second gate electrode is aligned with the same line in the width direction. The method of claim 15, And the first and second gate electrodes have a bar shape. delete Transistor regions are formed corresponding to each of the gate electrodes by integrally forming two or more gate electrodes having different lengths on one active region, The gate electrodes are integrally formed with a first gate electrode having a predetermined length and a second gate electrode longer than the first gate electrode, Forming triangular auxiliary gate electrodes on the gate electrodes which are integral with the first and second gate electrodes and have one side predetermined portion of the first gate electrode and one side predetermined portion of the second gate electrode as both sides; A semiconductor device layout method. The method of claim 18, One side of each gate electrode is a layout method of a semiconductor device, characterized in that formed on the same line in the width direction. delete The method of claim 18, The active region is divided into a first region in which the first gate electrode is formed and a second region in which the second gate electrode is formed, and the second region has a length longer than that of the first region. Layout method of semiconductor device. The method of claim 18, And the first and second gate electrodes have a bar shape. delete Transistor regions are formed corresponding to each of the gate electrodes by integrally forming two or more gate electrodes having different lengths on one active region, The gate electrodes may include first and second gate electrodes having a predetermined length, and a third gate electrode longer than the first and second gate electrodes positioned between the first and second gate electrodes. The gate electrodes may include a triangular first auxiliary gate electrode which is integral with the first and third gate electrodes and has one side predetermined portion of the first gate electrode and one side predetermined portion of the third gate electrode as both sides; Forming a second auxiliary gate electrode having a triangular second auxiliary gate electrode which is integral with the second and third gate electrodes and has one side predetermined part of the second gate electrode and one side predetermined part of the third gate electrode; Layout method. The method of claim 24, And the first to third gate electrodes have a bar shape. delete Forming an active region; First and second gate electrodes having different lengths and integrally formed on the active region, and a predetermined portion of one side of the first gate electrode and one side of the second gate electrode integrally with the first and second gate electrodes Forming a triangular auxiliary gate electrode having both sides of a predetermined portion; And Forming first source and drain regions and second source and drain regions on both sides of the first and second gate electrodes, respectively. And a first transistor region comprising said first gate, source, and drain, and a second transistor region comprising said second gate, source, and drain. 28. The method of claim 27, And the first gate electrode is formed to have a length longer than that of the second gate electrode. 29. The method of claim 28, The active region is divided into a first region in which the first gate electrode is formed and a second region in which the second gate electrode is formed, and the second region is formed to have a longer length than the first region. A layout method of a semiconductor device. 29. The method of claim 28, One side of the first and second gate electrodes are formed to be aligned on the same line in the width direction. 31. The method of claim 30, And the first and second gate electrodes are formed to have a bar shape. delete 28. The method of claim 27, And forming a first wiring connected to the first drain and the source and the second source in common, and a second wiring connected to the second drain. The method of claim 33, wherein And a predetermined voltage is applied to the first wiring to charge and discharge the first transistor region and to drive the second transistor region.

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