JP4869631B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device that achieves high-speed circuit operation and low power consumption in a logic circuit or a memory circuit using a semiconductor device.

  In a conventional bootstrap type pass transistor circuit, one electrode of a normal MOSFET isolation transistor is connected to the gate electrode of a normal MOSFET (pass transistor), and a control signal applied to the other electrode of the isolation transistor is passed through the isolation transistor. The circuit configuration applied to the gate electrode of the pass transistor is exhibited. Therefore, the gate electrode of the pass transistor becomes a floating gate (FG). Such a bootstrap type pass transistor is disclosed in Non-Patent Document 1, for example.

  The characteristics of this bootstrap type pass transistor circuit are as follows. The source, drain and gate potentials of the pass transistor are initially at ground potential (ground level). The gate of the isolation transistor is set to the power supply voltage. First, the source potential of the isolation transistor is raised to “H” level. At this time, the potential of the pass transistor floating gate (FG potential) rises to an intermediate level by charge redistribution due to capacitive coupling.

  Next, when an “H” level input signal is applied to the source of the pass transistor, the FG potential of the pass transistor further increases and reaches a potential exceeding the “H” level. As a result, current flows through the pass transistor, and the “H” level propagates from the source to the drain.

  In a pass transistor composed of only one normal transistor, the gate potential only reaches the “H” level, so the drain potential is only from “H” level to a voltage lower by the threshold voltage Vth of the pass transistor. Does not rise (Vth drop phenomenon). Therefore, the bootstrap circuit can avoid the problem that a simple pass transistor circuit cannot be used in a multi-stage circuit, and can reach the drain voltage to the “H” level without a Vth drop phenomenon.

K. Fujii, T. Douseki, “A Sub-1V Bootstrap Pass-Transistor Logic,” IEICE Trans. Electron., Vol. E86-C, no. 4, pp.604-611, Apr. 2003.

  However, even in this conventional bootstrap circuit, when the power supply voltage is as low as about 0.5 V, the on-operation current of the transistor is greatly reduced and the circuit operation is slowed down, so that further contrivance is necessary. That is, when the gate-source voltage of the transistor is about 0.5V, the difference from the threshold voltage Vth (for example, 0.2V) (gate overdrive voltage (Vdd−Vth)) is about 0.3V from the conventional about 1V. Since the current is greatly reduced, the on-current is reduced to a fraction or less, the load capacity charge / discharge time is lengthened, and the circuit operation is delayed.

  The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor device having a bootstrap circuit capable of high speed and low power consumption operation.

According to a first aspect of the present invention, there is provided a semiconductor device formed on an SOI substrate comprising a semiconductor substrate, a buried insulating film, and an SOI layer, comprising one electrode, the other electrode, and a control electrode having an insulating structure. A first MIS transistor of the first conductivity type, and a second MIS transistor of the first conductivity type having one electrode, the other electrode, and a control electrode having an insulating structure, the other of the second MIS transistors An electrode is connected to a control electrode of the first MIS transistor, and the first MIS transistor and the second MIS transistor are each of a second conductivity type isolated from other elements in the SOI layer. The first MIS transistor has a body region, and the control electrode and the body region are electrically connected.

  In the first MIS transistor of the semiconductor device according to the first aspect of the present invention, the control electrode and the body region are electrically connected, and the capacitance generated between the control electrode and one electrode of the first MIS transistor. As the component, the PN junction capacitance between the body region and the one electrode region is increased, so that the potential fluctuation of the control electrode accompanying the potential fluctuation of the one electrode is increased by capacitive coupling between the one electrode and the control electrode. can do. As a result, compared with a structure in which the control electrode of the first MIS transistor and the body region are not electrically connected, there is an effect of increasing the signal propagation capability of the first MIS transistor.

<Embodiment 1 to Embodiment 3>
(Circuit configuration of Embodiment 1)
1 is a circuit diagram showing a configuration of an active body bias control (ABC) type bootstrap circuit (ABC bootstrap circuit) according to a first embodiment of the present invention. As shown in the figure, the gate electrode (floating gate electrode) and the body region (electrode) of the NMOS pass transistor Q1 are electrically connected. By functioning the source electrode of the pass transistor Q1 as the source terminal S1 (one signal end) and the drain electrode as the drain terminal D1 (the other signal end) (including being connected to one signal end and the other signal end), A signal is propagated between the source terminal S1 and the drain terminal D1 via the pass transistor Q1.

  Then, the drain of the separation transistor Q2 having the NMOS structure is connected to the floating gate of the pass transistor Q1. The source electrode of the isolation transistor Q2 functions as the source terminal S2 (control signal terminal) (including being connected to the control signal terminal), receives the control signal from the source terminal S2, and applies the power source Vdd to the gate electrode.

  As described above, the ABC bootstrap circuit of the first embodiment is characterized in that the gate electrode and the body region are connected in the NMOS pass transistor Q1.

  In addition, the pass transistor Q1 and the isolation transistor Q2 constituting the ABC bootstrap circuit are formed on the SOI substrate separately from other elements. In other words, each element formed on the SOI substrate including the pass transistor Q1 and the isolation transistor Q2 is insulated and isolated from other elements, so that the body region is separated for each transistor. Even if the region is electrically connected, there is no short circuit with the gate electrode of another transistor formed adjacently. This is because in a transistor formed on an SOI substrate, a thin film Si layer (SOI layer) can be insulated and separated for each transistor, so that a body region can be separated for each transistor.

(Circuit configuration of the second embodiment)
2 is a circuit diagram showing a configuration of an ABC bootstrap circuit according to a second embodiment of the present invention. As shown in the figure, an isolation transistor Q3 having an NMOS configuration is provided in place of the isolation transistor Q2 (see FIG. 1) of the first embodiment.

  The source electrode of the isolation transistor Q3 functions as the source terminal S3 (control signal terminal), is electrically connected to the body region, the power supply Vdd is applied to the gate electrode, and the drain electrode is connected to the gate electrode of the pass transistor Q1. The Other configurations are the same as those of the first embodiment shown in FIG.

  In the ABC bootstrap circuit of the second embodiment, when an “H” (level) signal is input to the source terminal S3, the potential of the body region (body potential) also starts to change to “H” at the same time, and the isolation transistor Q3 Since the threshold voltage Vth is lower than the threshold voltage Vth of the isolation transistor Q2 of the first embodiment, the effect of enabling higher speed operation and lower voltage operation than that of the first embodiment is achieved.

(Circuit configuration of Embodiment 3)
3 is a circuit diagram showing a configuration of an ABC bootstrap circuit according to a third embodiment of the present invention. As shown in the figure, an NMOS separation transistor Q4 is provided in place of the separation transistor Q2 (see FIG. 1) of the first embodiment.

  The source electrode of the isolation transistor Q4 functions as a source terminal S4 (control signal terminal), the gate electrode and the body region are electrically connected, the power supply Vdd is applied to the gate electrode, and the drain electrode is the pass transistor Q1. Connected to the gate electrode. Other configurations are the same as those of the first embodiment shown in FIG.

  In the ABC bootstrap circuit of the third embodiment, since the “H” level of the power supply voltage (Vdd) is previously applied to the gate electrode of the isolation transistor Q4, the body region electrically connected to the gate electrode is also “ H ”level. Therefore, the threshold voltage Vth of the isolation transistor Q4 further decreases, and the floating gate (FG) potential of the pass transistor Q1 is set to the first embodiment before the “H” level is applied to the source terminal S1. It becomes possible to get closer to “H” level to 2 or more.

(Body potential fixed structure)
The pass transistor Q1 of the first to third embodiments, the isolation transistor Q3 of the second embodiment, and the isolation transistor Q4 of the third embodiment require a body potential fixing structure in which the body potential can be set from the outside.

  By forming these pass transistors Q1 and isolation transistors Q3 and Q4 on the SOI substrate, it is possible to fix the body potential in a state of being isolated from other elements (transistors). Specific examples will be described below.

  4 is a plan view showing a body potential fixing structure with a T-type gate, and FIG. 5 is a cross-sectional view taken along the line CC in FIG. As shown in these drawings, the body-fixed structure transistor QB1 is formed on an SOI substrate including the silicon substrate 1, the buried insulating film 2, and the SOI layer 3. A complete isolation film 4a is formed in the SOI layer 3 so as to penetrate from the surface of the SOI layer 3 to the buried insulating film 2, and the complete isolation film 4a is formed in the periphery, so that other elements (transistors) formed adjacently are formed. The body-fixed structure transistor QB1 can be formed in the SOI layer 3 that is insulated from the SOI layer 3.

A P ⁻ body region 5 and a body contact region 6 are formed adjacent to each other in the SOI layer 3, and a gate insulating film (described in the description) is formed on the P ⁻ body region 5 (channel region) between the drain region 9 and the source region 10. For convenience, a T-type gate electrode 7A is formed via a not-shown), and the horizontal bar portion (“-”) of the T-type gate electrode 7A is on the boundary region between the P ⁻ body region 5 and the body contact region 6. It is formed.

  The body contact region 6 in the body-fixed structure transistor QB1 having such a structure can be electrically connected to the T-type gate electrode 7A or the source region 10 through an external wiring such as an aluminum wiring.

  6 is a plan view showing a body potential fixing structure by partial trench isolation, and FIG. 7 is a sectional view taken along the line DD of FIG. As shown in these drawings, the body fixed structure transistor QB2 is formed in the SOI layer 3 that is insulated and isolated from other elements formed around by the complete isolation film 4a, like the body fixed structure transistor QB1.

In the SOI layer 3, a P ⁻ body region 5 and a body contact region 6 are formed with a partial isolation film 4b sandwiched therebetween, and the partial isolation film 4b has a part (5a) of the P ⁻ body region 5 formed in a lower layer portion. Therefore, P ⁻ body region 5 and body contact region 6 are electrically connected by part 5a of P ⁻ body region 5 below partial isolation film 4b.

Then, gate electrode 7B is formed on P ⁻ body region 5 (channel region) between drain region 9 and source region 10 via a gate insulating film (not shown for convenience).

  The body contact region 6 in the body-fixed structure transistor QB2 having such a structure can be electrically connected to the gate electrode 7B or the source region 10 through an external wiring such as an aluminum wiring.

(Direct body contact (BC) structure)
The body-fixed structure transistor QB (QB1, QB2) shown in FIGS. 4 to 7 has an electrical connection between the body contact region 6 and the gate electrode 7 (7A, 7B) from the external wiring. Connection by is also conceivable.

  FIG. 8 is a perspective view showing an example of a direct BC structure. FIG. 8 shows a direct BC structure in a partial trench isolation structure. As shown in the figure, the body contact 20 is directly erected on the body contact region 6 and the gate electrode 7B is formed extending in the gate width direction to directly connect the gate electrode 7B and the body contact 20 directly. Thus, the gate electrode 7B and the body contact region 6 are electrically connected.

(Structure of pass transistor and isolation transistor)
(Structure of Embodiment 3)
9 is a plan view showing a layout configuration of the pass transistor and the isolation transistor according to the third embodiment, and FIG. 10 is a cross-sectional view taken along the line AA of FIG. 9 and 10 show the pass transistor Q1 and the isolation transistor Q4 in the third embodiment, and both the pass transistor Q1 and the isolation transistor Q4 adopt a body potential fixing structure with a partial trench structure.

  As shown in these drawings, the pass transistor Q1 is formed in the SOI layer 3 that is insulated and isolated from other elements (including the isolation transistor Q4) formed around by the complete isolation film 4a.

The SOI layer 3, P ^- by some 5a of the body region 5, P ^{- -} P under the body regions 5 and the body contact region 6 is formed across the partial isolation film 4b partial isolation film 4b and the body region 5 The body contact region 6 is electrically connected.

Then, the gate electrode 7 is formed on the P ⁻ body region 5 (channel region) between the drain region 9 and the source region 10 via the gate insulating film 8. Furthermore, the gate electrode 7 and the body contact region 6 are electrically connected via the contact 21, the aluminum wiring 31 and the contact 22.

On the other hand, in the isolation transistor Q4, the P ⁻ body region 13 and the body contact region 16 are formed in the SOI layer 3 with the partial isolation film 4b (not shown in FIG. 10) interposed therebetween, and the P ⁻ under the partial isolation film 4b. P ⁻ body region 13 and body contact region 16 are electrically connected by part of body region 13.

A gate electrode 14 is formed on the P ⁻ body region 13 (channel region) between the drain region 11 and the source region 12 with a gate insulating film 15 interposed therebetween. Further, the gate electrode 14 and the body contact region 16 are electrically connected through the contact 25, the aluminum wiring 33 and the contact 26.

  Further, the gate electrode 7 of the pass transistor Q1 and the drain region 11 of the isolation transistor Q4 are electrically connected through the contact 23, the aluminum wiring 32, and the contact 24, so that the embodiment shown in FIG. 3 ABC bootstrap circuits are configured.

(Structure of Embodiment 2)
FIG. 11 is a plan view showing the layout configuration of the isolation transistor according to the second embodiment, and FIG. 12 is a cross-sectional view taken along the line BB of FIG. 11 and 12 show the isolation transistor Q3 in the second embodiment, and both the pass transistor Q1 and the isolation transistor Q3 adopt a body potential fixing structure with a partial trench structure.

Isolation transistor Q3 is configured in the same manner as isolation transistor Q4. However, as shown in FIG. 12, body contact region 17 is formed in a region near source region 12, and body region 13 and body contact region 17 are partially separated. P ⁻ body region 13 and body contact region 16 are electrically connected by part 13a of P ⁻ body region 13 formed under film 4b and under partial isolation film 4b.

  The source region 12 of the isolation transistor Q3 and the body contact region 17 are electrically connected through the contact 27, the aluminum wiring 34, and the contact 28. Other configurations are the same as those of the third embodiment shown in FIGS.

(Structure of Embodiment 1)
The structure is basically the same as that of the third embodiment shown in FIGS. However, since the isolation transistor Q2 does not require electrical connection between the body contact region 16 and the gate electrode 14 unlike the isolation transistor Q4, the isolation transistor Q2 does not need to adopt a body potential fixing structure.

(Effects of Embodiments 1 to 3)
FIG. 13 is a graph showing the FG (floating gate) potential of the pass transistor in the ABC bootstrap circuit of the first to third embodiments. In FIG. 13, FG1 to FG3 indicate the FG potential of the pass transistor Q1 in the first to third embodiments, and FG10 indicates the FG potential of the conventional bootstrap circuit.

  FIG. 14 is a circuit diagram showing a configuration of a conventional bootstrap circuit. As shown in the figure, the source electrode and the drain electrode of the pass transistor Q7 function as the source terminal S7 and the drain terminal D7, and the drain electrode of the isolation transistor Q8 is connected to the floating gate. The source electrode of the isolation transistor Q8 functions as the source terminal S8, and the power supply Vdd is applied to the gate electrode. The FG potential of this pass transistor Q7 becomes FG7.

FIG. 15 is a circuit diagram schematically showing the capacitance associated with the pass transistor Q7 of the conventional bootstrap circuit. As shown in the figure, in the conventional pass transistor Q7, a gate-source capacitance _CGS is formed between the FG and the source electrode.

FIG. 16 is a circuit diagram schematically showing a capacitance associated with the pass transistor Q1 of the ABC bootstrap circuit of the first embodiment. As shown in the figure, the pass transistor Q1 has a gate-source capacitance _CGS formed in the same manner as the conventional pass transistor Q7, and the body region and FG are electrically connected to each other. A body-source capacitance C _SB due to a PN junction between the body region and the source region is added.

  Returning to FIG. 13, VS1 is a source voltage applied to the source terminal S1 (S7) of the pass transistor Q1 (Q7), and VS2 is a source terminal S2 (S3, S4, S8) of the separation transistor Q2 (Q3, Q4, Q8). Means the source voltage applied to

  As shown in FIG. 13, the FG potentials FG1 to FG3 and FG7 rise following the source voltage VS2 and the source voltage VS1, respectively, but the FG potentials FG1 to FG3 rise to a potential higher than the conventional FG potential FG7. .

Because, as described above, the floating gate (FG) of the pass transistor Q1 and the body region of the first to third embodiments are electrically connected, the FG of the pass transistor Q1 is connected to the source electrode. The coupling capacitance is a gate-source capacitance C _GS and a body-source capacitance C _SB , the capacitance component is larger than that of the pass transistor Q 7 having only the gate-source capacitance C _GS , and the fluctuation of the source voltage VS 1 It is because it becomes easy to be transmitted to FG.

  As a result, in the ABC bootstrap circuit according to the first to third embodiments, the on-current of the pass transistor Q1 becomes larger than the conventional current and lower due to the rise of the FG potentials FG1 to FG3 exceeding the conventional level. Even at the power supply voltage, there is an effect that high-speed operation is possible.

  Note that the FG potential FG2 exceeds the FG potential FG1 because the source terminal S3 and the body region of the isolation transistor Q3 of the second embodiment are electrically connected, and therefore the high voltage Vh is applied to the drain of the isolation transistor Q3. When input, the threshold voltage Vth decreases (the voltage is set to the threshold voltage Vth2), and the rise of the FG potential FG2 is a level closer to the high voltage Vh from (Vh-Vth2) to (Vh-Vth2) in the first embodiment. This is because the signal propagation capability of the pass transistor Q1 is promoted.

  Further, the reason why the FG potential FG3 exceeds the FG potential FG2 is that the gate electrode and the body region of the isolation transistor Q4 are connected, and the high voltage Vh is applied in advance to the gate electrode. This is because the threshold voltage Vth of the isolation transistor Q4 is further lowered by the amount of "H" level without causing an RC delay (associated with Q4).

<Embodiment 4>
FIG. 17 is a circuit diagram showing a configuration of a Manchester adder (semiconductor integrated circuit) as a semiconductor device according to the fourth embodiment of the present invention. The fourth embodiment uses the ABC bootstrap circuits 61 to 64 of the second embodiment as pass transistors of the Manchester adder.

Since the ABC bootstrap circuit of the first to third embodiments exhibits a speed-up effect when the gate signal of the pass transistor Q1 reaches before the source signal, it is effective to be applied to a Manchester type adder. It is. The Manchester type adder is an adder for the purpose of high-speed carry propagation. From the inputs a _i and b _{i of} each bit i, a carry generation signal g _i , a carry disappearance signal k _i , and a carry propagation signal p _i i is obtained as shown in equations (1) to (3), and a carry signal c _{i + 1} from bit i is expressed by the following equation (4).

  As shown in FIG. 17, the ABC bootstrap circuit 61 includes a pass transistor Q11 and an isolation transistor Q31, the ABC bootstrap circuit 62 includes a pass transistor Q12 and an isolation transistor Q32, and the ABC bootstrap circuit 63 includes a pass transistor Q13. The ABC bootstrap circuit 64 includes a pass transistor Q14 and an isolation transistor Q34. The configurations and connection relationships of the pass transistors Q11 to Q14 and the isolation transistors Q31 to Q34 are the same as those shown in FIG. This is the same as the pass transistor Q1 and the separation transistor Q3 in the ABC bootstrap circuit of the second embodiment.

In an ordinary Manchester type adder, a carry signal (carry signal) is propagated by a transfer gate in which a PMOS transistor and an NMOS transistor are combined, but the ABC bootstrap circuits 61 to 64 used in the fourth embodiment include As shown in FIG. 17, the signal is propagated only by the NMOS transistor, and the body region of the pass transistors Q11 to Q14 is controlled using the carry propagation signal p _i .

Hereinafter, a specific circuit configuration will be described with reference to FIG. In ABC bootstrap circuit 61 to 64, respectively the source electrode of the isolation transistor Q31~Q34 function as carry propagate signal terminal, receiving the carry propagate signal p ₀ ~p _3.

An output portion of the buffer G11 receiving a carry signal c ₀ the node N0 is the carry signal terminal for carry signal c _0.

The source electrode of the pass transistor Q11 of ABC bootstrap circuit 61 is connected to the node N0, and a drain electrode connected to the node N1 is the carry signal terminal for carry signal c _1. The node N1 is the carry signal terminal for carry signal c _1.

Inserted PMOS transistor Q51 is mediated between the node N1 and the power supply Vdd, to the gate of the PMOS transistor Q51 inverted carry generate signal bar g ₀ is given. An NMOS transistor Q55 is interposed between the node N1 and the ground level, and a carry disappearance signal k ₀ is applied to the gate of the NMOS transistor Q55. A carry signal c ₁ is obtained from the node N1.

The source electrode of pass transistor Q12 of ABC bootstrap circuit 62 is connected to node N1, and the drain electrode is connected to node N2. The node N2 is the carry signal terminal for carry signal c _2.

PMOS transistor Q52 is inserted between the node N2 and the power supply Vdd, to the gate of the PMOS transistor Q52 inverted carry generate signal bar g ₁ is assigned. Between the node N2 and the ground level NMOS transistor Q56 is interposed, the carry loss signal k ₁ to the gate of the NMOS transistor Q56 is is applied.

The source electrode of pass transistor Q13 of ABC bootstrap circuit 63 is connected to node N2, and the drain electrode is connected to node N3. The node N3 is the carry signal terminal for carry signal c _2.

PMOS transistor Q53 is inserted between the node N3 and the power supply Vdd, to the gate of the PMOS transistor Q53 inverted carry generate signal bar g ₂ is assigned. Between the node N3 and the ground level NMOS transistor Q57 is interposed, the carry loss signal k ₂ to the gate of the NMOS transistor Q57 is applied.

The source electrode of pass transistor Q14 of ABC bootstrap circuit 64 is connected to node N3, and the drain is connected to node N4. The node N4 is the carry signal terminal for carry signal c _2.

PMOS transistor Q54 is inserted between the node N4 and the power source Vdd, to the gate electrode of the PMOS transistor Q54 is inverted carry generate signal bar g ₃ is assigned. Between the node N4 and the ground level NMOS transistor Q58 is interposed, to the gate electrode of the NMOS transistor Q58 is carry loss signal k ₃ is applied. Further, the carry signal c ₄ obtained from the node N4 is outputted through the buffer G12.

PMOS transistor Q51~Q54 described above, transmits under the control of the inversion carry generation signal bar g ₀ to g ₃ which receives the gate electrode, the "H" level signal indicating a carry generated node N1~N4 digit function as carry generation signal transmitting means, NMOS transistor Q55~Q58 under the control of the carry loss signal k ₀ to k ₃ for receiving the gate electrode, and instructs the carry loss "L" level of the signal node N1~ It functions as a carry disappearance signal transmission means for transmission to N4.

FIG. 18 is a circuit diagram showing a conventional Manchester adder. Hereinafter, a specific circuit configuration will be described with reference to FIG. Buffer G11 receives carry signals c _0, the output (node N0) is connected to one electrode of the PMOS transistor Q61 and NMOS transistors Q71, the other electrode of the PMOS transistor Q61 and NMOS transistor Q71 is connected to the node N1. Further, to the gate of the PMOS transistor Q61 is applied the inverted carry propagate signal bar p _0, carry propagate signal p ₀ to the gate electrode of the NMOS transistor Q71 is applied.

Node N1 is connected to one electrode of PMOS transistor Q62 and NMOS transistor Q72, and the other electrode of PMOS transistor Q62 and NMOS transistor Q72 is connected to node N2. Further, to the gate of the PMOS transistor Q62 inverted carry propagate signal bar p ₁ is applied, the carry propagate signal p ₁ to the gate electrode of the NMOS transistor Q72 is applied.

Node N2 is connected to one electrode of PMOS transistor Q63 and NMOS transistor Q73, and the other electrode of PMOS transistor Q63 and NMOS transistor Q73 is connected to node N3. Further, to the gate of the PMOS transistor Q63 is applied the inverted carry propagate signal bar p _2, carry propagate signal p ₂ to the gate electrode of the NMOS transistor Q73 is applied.

Node N3 is input to one electrode of PMOS transistor Q64 and NMOS transistor Q74, and the other electrode of PMOS transistor Q64 and NMOS transistor Q74 is connected to node N4. Further, to the gate of the PMOS transistor Q64 is applied the inverted carry propagate signal bar p _3, the gate electrode of the NMOS transistor Q74 is carry propagation signal p ₃ is applied.

As described above, the carry signals c _{0 to} g ₄ are propagated by using the CMOS transfer gate constituted by the PMOS transistor Q6j (any of j = 1 to 4) and the NMOS transistor Q7j. It is a vessel. Other configurations are the same as the Manchester adder of the fourth embodiment shown in FIG.

Compared with the conventional Manchester adder, the Manchester adder of the fourth embodiment uses the ABC bootstrap circuits 61 to 64 instead of the CMOS transfer gates (Q61 to Q64, Q71 to Q74), so that the PMOS transistor Q61 of the transfer gate is used. ~ 64 can be deleted. Along with this, it was produced a control signal of the PMOS transistor Q61～Q64, than the inverted order carry propagate signal bar p _i for XNOR gate is unnecessary, conventional Manchester using CMOS transfer gates (type) adder However, there is an advantage of applying the ABC bootstrap circuits 61 to 64 in that the number of transistors can be reduced.

Even when the ABC bootstrap circuits 61 to 64 are realized by using a conventional general bootstrap circuit, the number of transistors described above can be reduced as compared with a conventional Manchester adder using a CMOS transfer gate, This is effective in that the signal propagation capability is excellent by propagating the carry signals c _{0 to} g ₃ through the pass transistors of the bootstrap circuit.

(Effect of Embodiment 4)
In order to evaluate the Manchester adder of the fourth embodiment, an SOI transistor model based on BSIM3 (simulation version 3 by the University of California, Berkeley) is used in a 0.18 μm SOI process with a power supply voltage of 0.5 V. Circuit simulation was performed by HSPICE.

  The threshold voltages of the NMOS transistor and the PMOS transistor are Vth-n = 0.24 V and Vth-p = −0.34 V, respectively. Here, the threshold voltage Vth is defined as a gate voltage Vgs that satisfies a drain current Ids of Ids = 1 μA / μm when the drain voltage Vds is Vds = 1.8 V, and was calculated by HSPICE simulation.

  One is a 4-bit Manchester adder having a configuration equivalent to that of the fourth embodiment shown in FIG. 17, and the other is a general bootstrap circuit used as the ABC bootstrap circuits 61 to 64 of the fourth embodiment. The case was designed as a comparative Manchester adder and each Manchester adder was evaluated. Regarding the application of the proposed method, circuit cell layout is created and wiring resistance and capacitance are extracted. The channel width of the pass transistor was Wn = 2.0 μm, and the channel width of the bootstrap isolation transistor was Wn = 0.5 μm. The delay time, operating power, and standby power are evaluated items. Regarding the evaluation of the delay time, the input voltage passes (Vdd / 2) after the input voltage passes (Vdd / 2) with the buffer connected to the previous stage of each input terminal and the subsequent stage of each output terminal. The delay time is defined as the delay time.

  Table 1 shows the evaluation results regarding the delay time, power consumption, and leakage current of the 4-bit Manchester adder. The delay time is the time required for the carry signal from the least significant bit to the most significant bit. The operating power is the power consumed for 100 ns when a random input signal of 100 patterns is given. The standby power is the power consumed for 100 ns 5 ms after the input signal is applied (after the time when the operation has been finished reliably).

  As shown in Table 1, with the application of the ABC bootstrap circuit of the second embodiment, the delay time of the Manchester adder of the fourth embodiment is shortened by 89% compared with the Manchester adder for comparison. In the Manchester type adder to be evaluated, four stages of pass transistors are connected in series. Therefore, in the conventional bootstrap structure, the transition time required for rising of the output potential is increased due to the capacitance added to each drain electrode. . When a drain signal having a long transition time is input to the source electrode of the next-stage pass transistor, a delay occurs in the rise of the gate signal of the next-stage pass transistor. For this reason, the carry signal does not propagate at high speed in the Manchester adder for comparison.

On the other hand, in the ABC bootstrap circuit of the second embodiment, the Vth reduction effect by applying a forward bias higher than the power supply Vdd to the body region of the pass transistor, and the gate potential of the pass transistor by coupling of the body-source capacitance C _SB y (This effect is common to the first to third embodiments), and as a result, greatly contributes to the reduction of the delay time of the Manchester adder of the fourth embodiment. It has been shown.

  As for power consumption, the ABC bootstrap circuit is effective for low power consumption due to the effect of reducing the power consumed by the through current consumed by the gate electrode for inputting the drain signal of the pass transistor. Although there is no significant difference in power consumption in Table 1, this is because the delay time is greatly shortened, and when the amount of shortening of the delay time is reduced (for example, the delay time is compared with Manchester for comparison). In the same way as an adder), power consumption can be greatly reduced.

  19 and 20 are graphs for explaining the effect of the Manchester adder according to the fourth embodiment. FIG. 19 shows the floating gate voltages (FG11, FG21) of the first-stage pass transistor (corresponding to the pass transistor Q11 of FIG. 17, but in the case of the comparison Manchester adder, equivalent to the pass transistor of the conventional bootstrap circuit) and The drain voltages (C11, C21) are compared.

As shown in FIG. 19, but FG potential FG11 and FG potential FG21 are both raised to the power supply voltage Vdd (500mA) above, the FG potential FG11 coupling effect of the capacitor C _SB between the body-source and rate of increase high. Accordingly, the rise of the drain voltage C11 is the carry signal c ₁ becomes faster, also have risen to around Vdd.

  FIG. 20 shows the FG potential (FG14, FG24) and drain of the fourth-stage pass transistor (corresponding to the pass transistor Q14 of FIG. 17; however, in the case of the comparison Manchester adder, it corresponds to the pass transistor of the conventional bootstrap circuit). The voltages (C14, C24) are compared.

As shown in FIG. 20, when attention is paid to the fourth-stage pass transistor, the rise of the FG potential FG24 in the conventional bootstrap is delayed, and even the power supply potential Vdd is not reached. This is because the driving force becomes weaker as the number of stages of the pass transistor becomes deeper. However, in the ABC bootstrap circuit of the present embodiment, the driving force is increased by the dynamic body control, and the fourth-stage gate potential FG14 also rises to the power supply potential Vdd or higher. Thus, increase of the drain signal C14 is carry signal c ₄ is also rising fast, has risen to around Vdd.

  Thus, it can be seen that the Manchester adder according to the fourth embodiment is significantly improved in operation speed and power consumption as compared with the comparison Manchester adder.

(Layout configuration)
FIG. 21 is an explanatory diagram showing a part of the layout configuration of the Manchester adder according to the fourth embodiment shown in FIG. FIG. 21 shows a layout configuration of the separation transistor Q31, the pass transistor Q11, the PMOS transistor Q51, and the PMOS transistor Q61 shown in FIG. However, as the isolation transistor Q31, unlike the circuit of FIG. 17, an example is shown in which the isolation transistor Q2 of the first embodiment (without body fixing) is used.

As shown in the figure, the isolation transistor Q31 is composed of a source / drain region 41 and a gate electrode 51, and the source region of the source / drain region 41 is electrically connected to the aluminum wiring 35 by a contact 29. A carry propagation signal p ₀ (not shown) is provided.

  The pass transistor Q11 includes a source / drain region 42, a gate electrode 52, and a body contact region 48. The gate electrode 52 is electrically connected to the body contact region 48 through a contact 30, an aluminum wiring 37, and a contact 29. The drain region of the source / drain region 41 of the isolation transistor Q31 is electrically connected to the gate electrode 52 of the pass transistor Q11 through the contact 29, the aluminum wiring 36, the contact 29, the aluminum wiring 37, and the contact 30.

  The source region of the source / drain region 42 of the pass transistor Q11 is electrically connected to the aluminum wiring 39 through a plurality of contacts 29, and the output (not shown) of the buffer G11 is applied to the aluminum wiring 39.

  The source / drain region 43 and the gate electrode 53 constitute an NMOS transistor Q55. The drain region of the source / drain region 43 is electrically shared with the drain region of the source / drain region 42 of the pass transistor Q11. Has a connection relationship. The source region of the source / drain region 43 is electrically connected to the aluminum wiring 40 via the contact 29. Aluminum wiring 40 is set to a ground level (not shown).

  Further, the gate electrode 54 and the source / drain region 44 constitute a PMOS transistor Q51. The drain region of the source / drain region 44 of the PMOS transistor Q51 is electrically connected to the aluminum wiring 45 through the contact 29.

  On the other hand, the drain region of the source / drain region 42 of the pass transistor Q11 and the drain region of the NMOS transistor Q55 are both electrically connected to the aluminum wiring 45 through the contact 29. Therefore, the aluminum wiring 45 functions as a node N1 electrically connected to the drain of the pass transistor Q11, the drain of the NMOS transistor Q55, and the drain of the isolation transistor Q32.

  The source region of the PMOS transistor Q51 is electrically connected to the aluminum wiring 47 through the contact 29, and the gate electrode 51 of the isolation transistor Q31 is electrically connected to the aluminum wiring 46 through the contact 30. Aluminum wiring 47 is electrically connected by contact 30, and power supply Vdd (not shown) is commonly applied to these aluminum wirings 46 and 47.

  In the fourth embodiment, the ABC bootstrap circuit of the second embodiment is shown as the ABC bootstrap circuits 61 to 64. Instead, the ABC bootstrap circuit of the first or third embodiment is used instead. It can also be used. The use of the ABC bootstrap circuit of the first embodiment is effective in that the area of the body wiring of the isolation transistor can be reduced.

<Embodiment 5>
FIG. 22 is a circuit diagram showing a configuration of an XOR circuit (semiconductor integrated circuit) as a semiconductor device according to the fifth embodiment of the present invention. As shown in the figure, PMOS transistors Q61 and Q62 are connected in series between a power supply Vdd and a node N5, and gate electrodes (first and second signal inputs) of PMOS transistors Q61 and Q62 (second logic value determining unit). Input signals A and B are applied to (function as an end). Then, the ABC bootstrap circuits 65 and 66 (first logic value determination unit) according to the second embodiment are connected to the node N5 that is the common signal end.

  The ABC bootstrap circuit 65 is composed of an NMOS separation transistor Q35 and a pass transistor Q15. An input signal B is applied to the source electrode (functioning as a second signal input terminal) of the pass transistor Q15, and the drain electrode of the pass transistor Q15 is Connected to the node N5, the input signal A is applied to the source electrode (functioning as the first signal input terminal) of the isolation transistor Q35, the power supply Vdd is connected to the gate, and the drain is connected to the gate of the pass transistor Q15.

  The ABC bootstrap circuit 66 is composed of an NMOS separation transistor Q36 and a pass transistor Q16. An input signal A is applied to the source electrode (functioning as the first signal input terminal) of the pass transistor Q16, and the drain electrode of the pass transistor Q16 is Connected to the node N5, the input signal B is applied to the source electrode (functioning as the second signal input terminal) of the isolation transistor Q36, the power supply Vdd is connected to the gate, and the drain electrode is connected to the gate of the pass transistor Q16.

  The output of the inverter G13 (output unit) having the node N5 as an input unit becomes the output signal Y, and the output signal Y becomes the exclusive OR (XOR) of the input signal A and the input signal B.

  FIG. 23 is a circuit diagram showing a configuration of a general XOR circuit using a bootstrap circuit for comparison with the fifth embodiment. A general XOR circuit uses bootstrap circuits 71 and 72 having a conventional configuration as ABC bootstrap circuits 65 and 66. Other points are the same as those of the XOR circuit of the fifth embodiment.

  In a general XOR circuit, as shown in FIG. 23, bootstrap circuits 71 and 72 are configured in which conventional isolation transistors Q65 and Q67 are connected to the gates of two conventional pass transistors Q66 and Q68 on the parallel transistor side. .

  When the input signal A and the input signal B are input in the XOR circuit of the fifth embodiment and the general XOR circuit having the above-described configuration, the general XOR circuit is connected to the pass transistors Q66 of the bootstrap circuits 71 and 72, respectively. And the gate potential of Q68 rises above the power supply voltage (Vdd), and a high potential is transmitted to the node N5. However, when the power supply Vdd is as low as about 0.5 V, it is difficult to transmit it to the node N5 satisfactorily.

  On the other hand, in the XOR circuit of the fifth embodiment, the ABC bootstrap circuits 65 and 66 are configured by the ABC bootstrap circuit of the second embodiment, so that the FG potentials of the pass transistors Q15 and Q16 are higher than the bootstrap circuits 71 and 72 or more. Therefore, even when the power supply voltage is as low as about 0.5 V, it is possible to transmit the signal to the node N5 satisfactorily, so that it is possible to always output a normal value as the output signal Y. .

  In the fifth embodiment, the ABC bootstrap circuit of the second embodiment is shown as the ABC bootstrap circuits 65 and 66. Instead, the ABC bootstrap circuit of the first or third embodiment is used instead. It can also be used. The use of the ABC bootstrap circuit of the first embodiment is effective in that the area of the body wiring of the isolation transistor can be reduced.

  Furthermore, if any of the ABC bootstrap circuits of the first to third embodiments is used instead of the series transistor side (PMOS transistors Q61 and Q62), the power supply Vdd is supplied to the node N5 via the series transistor. The effect which can be performed more favorably is produced.

<Embodiment 6>
FIG. 24 is a circuit diagram showing an SRAM cell circuit (semiconductor integrated circuit) as a semiconductor device according to the sixth embodiment of the present invention. FIG. 25 is a circuit diagram showing a general SRAM cell circuit for comparison with the fifth embodiment.

  As shown in these drawings, in the sixth embodiment and a general SRAM cell circuit, the SRAM cell unit 18 is formed by cross-connecting an inverter I1 and an inverter I2 having a CMOS structure.

  The inverter I1 is composed of a PMOS transistor Q71 (load transistor) and an NMOS transistor Q73 (driver transistor), and the inverter I2 is composed of a PMOS transistor Q72 (load transistor) and an NMOS transistor Q74 (driver transistor). A node N11 (first storage node) between the drains of Q73 serves as an output part of the inverter I1, and gates of the PMOS transistor Q71 and the NMOS transistor Q73 serve as an input part of the inverter I1, between the drains of the PMOS transistor Q72 and the NMOS transistor Q74. Node N12 (second storage node) serves as the output of inverter I2, and includes PMOS transistor Q72 and NMOS transistor. The gate of the register Q74 becomes the input of inverter I2.

  In the general SRAM cell circuit shown in FIG. 25, the node N11 is connected to the bit line BL via an NMOS transistor Q77 which is a pass transistor, and the node N12 is an inverted bit line via an NMOS transistor Q78 which is a pass transistor. The word line WL is commonly connected to the gates of the NMOS transistors Q77 and 78, which are connected to the bar BL.

  On the other hand, in the SRAM cell circuit of the sixth embodiment, the ABC bootstrap circuit 67 of the second embodiment is interposed between the node N11 (the other signal end) and the bit line BL (one signal end), and the node N12 (the other signal) End) and the inverted bit line bar BL (one signal end), the ABC bootstrap circuit 68 of the second embodiment is inserted. Further, the first word line WL1 and the second word line WL2 are used, the first word line WL1 corresponds to a word line WL of a general SRAM cell circuit, and the second word line WL2 is used as a power supply Vdd fixed line.

  The ABC bootstrap circuit 67 includes an NMOS pass transistor Q17 and an isolation transistor Q37. The pass transistor Q17 is interposed between the bit line BL and the node N11, and the source of the isolation transistor Q37 is the first word line WL1 (control signal). The gate electrode is connected to the second word line WL2, and the drain electrode is connected to the gate of the pass transistor Q17.

  The ABC bootstrap circuit 68 includes an NMOS configuration pass transistor Q18 and an isolation transistor Q38. The pass transistor Q18 is interposed between the inverted bit line BL and the node N11, and the source electrode of the isolation transistor Q38 is the first word line WL1. , The gate is connected to the second word line WL2, and the drain electrode is connected to the gate of the pass transistor Q18.

  In such a configuration, in the general SRAM cell circuit shown in FIG. 25, for example, data writing to the SRAM cell unit 18 is performed by applying “H” data to the bit line BL and applying “H” data to the inverted bit line bar BL. After the “L” data is applied, the word line WL is set to the “H” state, and the potentials of the nodes N11 and N12 are rewritten.

  However, at this time, due to the nature of the pass transistor on the “H” write side, the potential of the node N11 as the storage node rises only to a value lower than the “H” level by the threshold voltage Vth (Vth drop phenomenon).

  Therefore, for complete writing, the node N12, which is the storage node on the opposite side, is written to “L”, and is not completed until the PMOS transistor Q71, which is the load transistor on the node N11 side, is turned on. That is, the writing is completed only when the PMOS transistor Q71 is turned on and the potential of the node N11, which has been lowered by the threshold voltage Vth from the “H” level, is raised to the “H” level potential.

  On the other hand, in the SRAM cell circuit of the sixth embodiment shown in FIG. 24, with respect to data writing to the SRAM cell unit 18, "H" data is applied to the bit line BL as in the comparative SRAM cell circuit, and the inverted bit It is assumed that after applying “L” data to the line bar BL, the first word line WL1 is set to the “H” state and the potentials of the nodes N11 and N12 are rewritten.

  At this time, on the “H” write side, the gate potential of the pass transistor Q17 can be raised to “H” level + threshold voltage Vth or more by the effect of increasing the gate potential of the ABC bootstrap circuit 67. The node N11 is set to the “H” level without causing a phenomenon.

  That is, complete writing is completed when the bit line BL and the node N11 are electrically connected via the pass transistor Q17. Therefore, thereafter, writing of the “H” level to the node N11 is completed without waiting for the time when the node N12 is written to “L” and the PMOS transistor Q71 is turned on.

  Specifically, “H” level writing is performed as follows. When the power supply voltage is 0.5 V and the threshold voltage Vth of the pass transistor is 0.2 V, in the case of the above-described example, in the comparative SRAM cell circuit, the node N11 is connected to the word line WL with respect to “H” level writing to the node N11. Immediately after setting to “H”, it rises only to 0.3V.

  On the other hand, in the SRAM cell circuit of the sixth embodiment, the node N11 can be reliably set to 0.5V. Specifically, first, the first word line WL1 and the second word line WL2 become “H” (Vdd), and the floating gate (FG) potential (Vfg) of the pass transistor Q17 rises to 0.5V. Next, the bit line BL is raised from “L” level to “H” level of 0.5 V. At this time, since the source electrode and the gate electrode of the pass transistor Q17 are capacitively coupled on the bit line BL side, The FG potential rises to, for example, 0.7V. As a result, the drain potential of the pass transistor Q17 on the node N11 side is increased from the initial “L” level to 0.5V by raising the FG potential of the pass transistor Q17 to (Vfg−Vth) (≧ 0.5V). Thus, the “H” level can be written to the node N11 without causing the Vth drop phenomenon.

  As described above, the SRAM cell circuit of the sixth embodiment using the ABC type bootstrap circuit surely eliminates the Vth drop phenomenon of the storage node potential at the time of “H” level writing which cannot be solved by a general SRAM cell circuit. Therefore, there is an effect that a high-speed write operation is performed.

  In the sixth embodiment, the ABC bootstrap circuit of the second embodiment is shown as the ABC bootstrap circuits 67 and 68. Instead, the ABC bootstrap circuit of the first or third embodiment is used instead. It can also be used. The use of the ABC bootstrap circuit of the first embodiment is effective in that the area of the body wiring of the isolation transistor can be reduced.

<Embodiment 7>
FIG. 26 is a circuit diagram showing an SRAM cell circuit according to the seventh embodiment of the present invention. As shown in the figure, in the SRAM cell circuit of the seventh embodiment, the SRAM cell unit 19 is constituted by a cross connection of a high resistance load type inverter I3 and an inverter I4.

  The inverter I3 includes a load resistor R1 and an NMOS transistor Q75 (driver transistor) connected in series, and the inverter I4 includes a load resistor R2 and an NMOS transistor Q76 (driver transistor) connected in series. A node N13 (first storage node) between the drains of the NMOS transistor Q75 serves as an output unit of the inverter I3, and a gate of the load resistor R1 and the NMOS transistor Q75 serves as an input unit of the inverter I3, and the drain of the load resistor R2 and the NMOS transistor Q76. A node N14 (second storage node) in between is the output part of the inverter I4, and the load resistor R2 and the gate of the NMOS transistor Q76 are the input part of the inverter I4. The load resistors R1 and R2 are formed using, for example, a polysilicon film.

  Then, the ABC bootstrap circuit 69 of the second embodiment is inserted between the node N13 and the bit line BL, and the ABC bootstrap circuit 70 of the second embodiment is inserted between the node N14 and the inverted bit line bar BL. Yes.

  The ABC bootstrap circuit 69 includes an NMOS configuration pass transistor Q19 and an isolation transistor Q39. The pass transistor Q17 is interposed between the bit line BL and the node N13, and the source electrode of the isolation transistor Q39 is connected to the first word line WL1. The gate electrode is connected to the second word line WL2, and the drain electrode is connected to the gate of the pass transistor Q17.

  The ABC bootstrap circuit 70 includes an NMOS-structured pass transistor Q20 and an isolation transistor Q40. The pass transistor Q20 is interposed between the inverted bit line bar BL and the node N13, and the source electrode of the isolation transistor Q40 is the first word line WL1. The gate electrode is connected to the second word line WL2, and the drain electrode is connected to the gate of the pass transistor Q20.

  In such a configuration, in the SRAM cell circuit of the seventh embodiment shown in FIG. 26, data writing to the SRAM cell unit 19 is performed, for example, by applying “H” data to the bit line BL and the inverted bit line bar BL After the “L” data is applied to the first word line WL1, the first word line WL1 is set to the “H” state, and the potentials of the nodes N13 and N14 are rewritten.

  At this time, the FG potential of the pass transistor Q17 can be raised to (“H” level + threshold voltage Vth) or more by the effect of increasing the gate potential of the ABC bootstrap circuit 69 on the “H” write side. By setting the node N13 to the “H” level without causing the Vth drop phenomenon, complete writing becomes possible.

  As described above, the SRAM cell circuit according to the seventh embodiment has a configuration in which the ABC bootstrap circuits 69 and 70 are used in the high resistance load type SRAM cell unit 19. Unlike the SRAM cell unit 18, resistors (load resistors R1, R2) having high resistance values are used instead of the load transistors.

  In the SRAM cell portion 19, the operating current is smaller than that of the load (PMOS) transistor in the SRAM cell portion 18 due to the high resistance components due to the load resistors R1 and R2, and therefore, the influence of the Vth drop phenomenon at the time of writing “H” level. It was larger than the SRAM cell unit 18 or more. That is, in the case of the SRAM cell portion 18, even if the Vth drop phenomenon occurs, the potential of the node N11 (node N12) is set to the “H” level by the subsequent ON operation of the PMOS transistors (Q71, Q72) as the load transistors. Although it can be raised relatively early, when a high resistance is used as in the SRAM cell portion 19, the operating current of the resistor is smaller than that of the PMOS transistor that is a load transistor, so that the rise to the “H” level is considerable. There was a problem that it took a long time.

  However, the SRAM cell circuit of the seventh embodiment solves the problem of the Vth drop phenomenon and uses load resistors R1 and R2 instead of the PMOS transistor, so that it is stacked on top of the NMOS transistor unlike the PMOS transistor. Since it can be formed, the cell area can be reduced compared to the SRAM cell circuit of the sixth embodiment.

  Therefore, in the SRAM cell circuit of the seventh embodiment, by using ABC bootstrap circuits 69 and 70 as pass transistors, the Vth drop phenomenon does not occur in the “H” level writing to the storage nodes (nodes N13 and N14). Therefore, the problems caused by using the high resistance load type SRAM cell section 19 can be overcome, and an SRAM cell circuit capable of reducing the cell area and operating at high speed can be obtained.

<Others>
In order to avoid the Vth drop phenomenon of “H” writing, in a general SRAM cell circuit, it is conceivable to increase the ON potential (for transistor) of the word line WL to a power supply voltage or higher. For example, when the power supply voltage Vdd is 0.5 V and the threshold voltage Vth of the pass transistor is 0.2 V, if the level when the word line WL is turned on is boosted to 0.7 V, the Vth drop of “H” level writing The phenomenon can be prevented. However, a separate circuit for applying a power supply voltage of 0.7 V to the word line WL is necessary, and the circuit area increases.

  Therefore, the SRAM cell circuits of the fifth and sixth embodiments do not require a special power supply circuit for boosting the potential of the word line WL to a normal “H” level or higher. Further, in the SRAM cell circuits of the fifth and sixth embodiments, by setting the ON potential of the word line WL to a value exceeding the power supply Vdd, it is expected that the write operation is further speeded up.

  In the first to seventh embodiments, the ABC bootstrap circuit using the NMOS-type pass transistor and the isolation transistor among the MIS transistors is shown. However, the polarity is reversed, and all the PMOS-type pass transistors and Of course, an ABC bootstrap circuit using an isolation transistor can also be realized. Further, the present invention is not limited to a MOS transistor, and it is needless to say that the gate insulating film may be formed of a MIS transistor formed of a film other than an oxide film such as a nitride film.

  Furthermore, in the first to seventh embodiments, the example in which the isolation transistor and the pass transistor are formed on the SOI substrate is shown. However, if the body region can be separated for each transistor, the isolation region and the pass transistor are formed on a normal bulk substrate. May be. For example, when two NMOS transistors serving as an isolation transistor and a pass transistor are formed on a P substrate, an N well region is formed in the upper layer portion of the P substrate, and the two P well regions are independent of each other in the upper layer portion of the N well region. Thus, two NMOS transistors having body regions separated from each other on a bulk substrate can be obtained by forming a triple well structure in which an N source / drain region is formed in each of two P well regions. it can.

It is a circuit diagram which shows the structure of the ABC bootstrap circuit which is Embodiment 1 of this invention. It is a circuit diagram which shows the structure of the ABC bootstrap circuit which is Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the ABC bootstrap circuit which is Embodiment 3 of this invention. It is a top view which shows the body electric potential fixed structure by a T-type gate. It is sectional drawing which shows CC sectional structure of FIG. It is a top view which shows the body electric potential fixed structure by partial trench isolation | separation. 7 is a cross-sectional view showing the DD cross-sectional structure of FIG. It is a perspective view which shows a direct body contact (BC). FIG. 10 is a plan view showing a layout configuration of pass transistors and isolation transistors according to the third embodiment. It is sectional drawing which shows the AA cross-section of FIG. FIG. 10 is a plan view showing a layout configuration of an isolation transistor according to a second embodiment. It is sectional drawing which shows the BB sectional structure of FIG. 6 is a graph showing the potential of a pass transistor in the ABC bootstrap circuit of the first to third embodiments. It is a circuit diagram which shows the structure of the conventional bootstrap circuit for a comparison. FIG. 6 is a circuit diagram schematically showing a capacitance associated with a pass transistor of a conventional bootstrap circuit for comparison. FIG. 3 is a circuit diagram schematically showing a capacitor associated with a pass transistor of the ABC bootstrap circuit of the first embodiment. It is a circuit diagram which shows the structure of the Manchester adder which is Embodiment 4 of this invention. It is a circuit diagram which shows the conventional Manchester adder. It is a graph (the 1) for the effect explanation of the Manchester adder of Embodiment 4. It is a graph (the 2) for the effect explanation of the Manchester adder of Embodiment 4. FIG. 18 is an explanatory diagram showing an outline of a part of the layout configuration of the Manchester adder according to the fourth embodiment shown in FIG. 17; It is a circuit diagram which shows the structure of the XOR circuit which is Embodiment 5 of this invention. It is a circuit diagram which shows the structure of the general XOR circuit for a comparison. It is a circuit diagram which shows the structure of the SRAM cell circuit which is Embodiment 6 of this invention. It is a circuit diagram which shows the structure of the common SRAM cell circuit for a comparison. It is a circuit diagram which shows the structure of the SRAM cell circuit which is Embodiment 7 of this invention.

Explanation of symbols

61-70 ABC bootstrap circuit, Q1 pass transistor, Q2-Q4 isolation transistor.

Claims (9)

A semiconductor device formed on an SOI substrate comprising a semiconductor substrate, a buried insulating film and an SOI layer,
A first MIS transistor of a first conductivity type having one electrode, the other electrode, and a control electrode having an insulating structure;
And a second MIS transistor of the first conductivity type having a control electrode having an insulating structure and an insulating electrode, and the other electrode of the second MIS transistor is connected to the control electrode of the first MIS transistor And
Each of the first MIS transistor and the second MIS transistor has a body region of a second conductivity type that is insulated from other elements in the SOI layer.
In the first MIS transistor, a control electrode and a body region are electrically connected.
Semiconductor device. The semiconductor device according to claim 1,
In the second MIS transistor, one electrode and a body region are electrically connected.
Semiconductor device. The semiconductor device according to claim 1,
The second MIS transistor is characterized in that a control electrode and a body region are electrically connected.
Semiconductor device. One signal end and the other signal end;
Control signal end,
A semiconductor device portion, wherein the semiconductor device portion includes the semiconductor device according to any one of claims 1 to 3;
One electrode of the first MIS transistor is connected to the one signal end, and the other electrode is connected to the other signal end;
One electrode of the second MIS transistor is connected to the control signal terminal, and a fixed signal for giving an ON state to the control electrode is given.
Semiconductor device. The semiconductor device according to claim 4,
The semiconductor device is obtained by a logical product, a logical product of inverted values, and an exclusive logical sum of the first to Nth (N ≧ 1) one bit input and the first to Nth other bit inputs. Using the 1st to Nth carry generation signals, the 1st to Nth carry disappearance signals, and the 1st to Nth carry propagation signals, the first to Nth one bit inputs and the 1st to 1st bit inputs An adder for obtaining first to (N + 1) th carry signals, which is a result of addition with the other bit input of N;
The semiconductor device portion includes first to Nth semiconductor device portions,
The semiconductor device includes:
First to (N + 1) th carry signal ends from which first to (N + 1) th carry signals are obtained;
First to Nth carry propagation signal ends receiving the first to Nth carry propagation signals;
Under the control of the first to Nth carry generation signals, the first to Nth carry generation signal transmissions for transmitting a signal for instructing carry generation to the second to (N + 1) th carry signal ends. Means,
Under the control of the first to Nth carry disappearance signals, the first to Nth carry disappearance signals for transmitting signals indicating the carry disappearance to the second to (N + 1) th carry signal ends. A transmission means,
The one signal end includes the first to Nth carry signal ends, the other signal end includes the second to (N + 1) th carry signal ends, and the control signal end includes the first to Nth carry signal ends. Including the carry propagation signal edge,
In an i-th (i = 1 to N) semiconductor device portion, one electrode of the first MIS transistor is connected to an i-th carry signal end, and the other electrode is an (i + 1) -th carry signal. And one electrode of the second MIS transistor is connected to the i-th carry propagation signal end.
Semiconductor device. The semiconductor device according to claim 4,
The semiconductor device includes an XOR circuit that obtains an exclusive OR result of one bit input and the other bit input,
The semiconductor device portion includes first and second semiconductor device portions;
The semiconductor device includes:
A first signal input terminal;
A second signal input end;
A common signal end;
A first logic value determining unit having the first and second semiconductor device parts;
A second logical value determination unit;
An output unit that outputs the exclusive OR result based on a signal obtained from the common signal end;
The one signal end includes the first signal input end and the second signal input end,
The other signal end includes the common signal end;
The control signal end includes the first signal input end and the second signal input end,
In the first semiconductor device portion, one electrode of the first MIS transistor is connected to the second input signal end, the other electrode is connected to the common signal end, and one input of the second MIS transistor is connected to the second input signal end. Connected to the first signal input,
In the first semiconductor device portion, one electrode of the first MIS transistor is connected to the first input signal end, the other electrode is connected to the common signal end, and one input of the second MIS transistor is connected to the first input signal end. Connected to the second signal input,
The second logic value determining unit is connected to the first and second input terminals, and the common signal terminal is connected when both the first MIS transistors of the first and second semiconductor device portions are in an off state. Set to a predetermined logical value,
Semiconductor device. The semiconductor device according to claim 4,
The semiconductor device portion includes first and second semiconductor device portions;
The semiconductor device includes:
An SRAM cell portion having first and second storage nodes for storing mutually inverted values;
First and second bit lines;
A word line,
The first semiconductor device portion interposed between the first bit line and the first storage node of the SRAM cell portion;
The second semiconductor device portion interposed between the second bit line and the second storage node of the SRAM cell portion;
The one signal end includes the first and second bit lines,
The other signal end includes the first and second storage nodes of the SRAM cell unit,
The control signal end includes the word line,
In the first semiconductor device portion, one electrode of the first MIS transistor is connected to the first bit line, the other electrode is connected to the first storage node, and the second MIS transistor is controlled. The electrode is connected to the word line,
In the second semiconductor device portion, one electrode of the first MIS transistor is connected to the second bit line, the other electrode is connected to the second storage node, and control of the second MIS transistor is performed. The electrode is connected to the word line,
Semiconductor device. The semiconductor device according to claim 7,
The SRAM cell portion is configured by cross-connecting first and second inverters having a CMOS configuration.
Semiconductor device. The semiconductor device according to claim 7,
The SRAM cell portion is configured by cross-connecting high resistance load type first and second inverters,
Semiconductor device.

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