JPH06168597A - Flash memory and level conversion circuit - Google Patents

Abstract

PURPOSE:To miniaturize and facilitate manufacturing the constitution of a row decoder supplying negative voltage applied to a control gate at an erasure time. CONSTITUTION:A flash memory is provided with a decoder part 4 decoding an address signal and accessing a memory cell array 1. The flash memory is provided with a drive part 5 selectively outputting a voltage applied to a first power source terminal 6 and the voltage applied to a second power source terminal 7 according to a signal from the decoder part 4, and is constituted so that the high or low relation of the voltage applied to the first power source terminal 6 and the second power source terminal 7 is inverted at a writing/ reading time and at an erasure time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, a so-called flash memory, in which stored information can be electrically erased collectively or in blocks.
In particular, the present invention relates to a nonvolatile semiconductor memory device that applies a negative voltage to a control electrode (control gate) of a memory cell at the time of erasing. In the following description, the above-mentioned flash memory will be used.

[0002]

2. Description of the Related Art FIG. 60 shows a general schematic configuration of a conventional flash memory. The row decoder 503 and the column decoder 502 decode the row decode signal RDC and the column decode signal CDC to access the memory cell array 501, respectively.

In a flash memory, information is stored depending on the presence / absence of charges stored in a memory cell, and FIG. 61 shows a structural example of the memory cell. As shown in the figure, the gate has a two-layer structure of a control gate CG and a floating gate FG, the control gate CG is connected to the word line WLi, and the drain D is connected to the bit line BLi.

Flash memory is roughly divided into NO.
There are two types called R type and NAND type, and the methods of writing, reading and erasing information to and from the memory cell are slightly different. Writing, reading, and erasing of information in a memory cell will be described below by taking a NOR flash memory as an example. To write information into the memory cell having such a structure, as shown in (1) of FIG.
Li = V _PP (about 12 [V]), BLi = about 6 [V], S
= 0 [V], a high voltage is applied to the control gate CG and the drain D to flow a current through the memory cell. At this time,
A part of the electrons flowing in the memory cell is accelerated by the high electric field in the vicinity of the drain D to acquire energy, and is injected into the floating gate FG over the energy barrier of the gate insulating film. Since the floating gate FG is not electrically connected to other circuit parts, it can store charges semipermanently.

Further, in order to read the information of the memory cell,
As shown in (2) of FIG. 62, WLi = V _CC (about 5
[V]), BLi = about 1 [V], S = 0 [V],
A memory cell is selected by the word line WLi and the bit line BLi. The charge stored in the floating gate FG changes the threshold value of the cell transistor, and the current flowing through the selected memory cell changes according to the stored information. Information is read out by detecting and amplifying this current.

To erase the information in the memory cell,
As shown in (3) of FIG. 62, WLi = about 0 [V], B
With Li = open, S = V _PP (about 12 [V]), the drain D is opened and the control gate CG is set to about 0 [V].
And the high potential was applied to the source S, respectively.
However, since a high potential is applied to the source S, it is necessary to increase the breakdown voltage of the source side diffusion layer, which requires deep diffusion, which hinders reduction of the cell area.

Further, in order to divide and erase, it is necessary to partially set the source side wiring (V _SS line) to another potential, and because of the wiring separation and the increase of the driving circuit, the chip size is reduced. It was getting bigger. to solve this problem,
There is a method of applying a negative voltage to the word line WLi. That is, as shown in (4) of FIG. 62, a negative voltage (about -10 [V]) is applied to the control gate CG, V _CC (about 5 [V]) is applied to the source S, and the drain D is opened. To erase.

In this case, since the potential applied to the source S is low, it is not necessary to increase the withstand voltage on the source side, which contributes to cell shrinkage, and the potential of the control gate CG is selectively made negative to partially Can be erased. As will be described later, as an erasing method, there is also a channel erasing method in which charges in the floating gate are drawn to a channel, that is, a substrate, but in that case, a negative voltage is applied to the control gate. The channel erasing method is used in the erasing method of the NAND type flash memory described above.

In an actual flash memory, a large number of memory cells are arranged in an array as shown in FIG. 60, and the voltage is applied to the control gate CG and the drain D at the time of writing and reading, by word line and bit. This is performed by the row decoder 503 and the column decoder 502 via the line. That is, at the time of writing, the high voltage V is applied to the word line (selected word line) connected to the memory cell to be written.
_PP is applied and other word lines (non-selected word lines)
Is applied with a zero (ground) voltage V _SS . Then, about 6 V is applied to the selected bit line and the non-selected bit line is opened. Similarly, at the time of reading, the positive voltage V _CC is applied to the selected word line, the zero voltage V _SS is applied to the unselected word line, about 1 V is applied to the selected bit line, and the unselected bit line is opened. . In either case, the zero voltage V _SS is applied to the source S. In this way, each memory cell can be individually accessed to write and read information.

Therefore, the row decoder 503 of FIG.
The voltage applied to the word line WLi is selected between the power supplies V _P and V _B according to the row decode signal RDC.
_It is necessary to change the voltage of _P between writing and reading. That is, it is necessary to switch so that the high voltage V _PP is applied to the terminal of the power supply V _P during writing and the positive voltage V _CC is applied to V _P during reading. The row decode signal RDC input to the row decoder 503 is constant regardless of the write and read modes, and the row decoder 503 has a level conversion function of switching to a signal of a different voltage level according to the selection signal.

When erasing by applying a negative voltage, it is necessary to open the drain D, apply the positive voltage V _CC to the source S, and apply the negative voltage V _BB to the control gate CG, as shown in (4) of FIG. is there. The negative voltage V _BB is applied to the control gate CG for each block to be erased,
A positive voltage V _CC is applied to the word line of the block that is not erased.

In order to apply a negative voltage to the word line, as shown in FIG. 63, a negative voltage generating circuit 504 is provided on the opposite side of the row decoder across the memory cell array 1 to connect the word line, It is conceivable that a separation switch circuit is provided between them, and the negative voltage generation circuit is disconnected in the write and read modes and the row decoder is disconnected in the erase mode by this switch circuit. In FIG. 63, p-channel transistors 505 and 506 are provided between the row decoder 503 and the memory cell array 501 to serve as separation switches.

[0013] However, in the circuit of Figure 63, during normal operation of reading and writing, there is a possibility that the potential of the word line WLi rises threshold voltage V _th component of p-channel transistor than the threshold voltage V _th of the cell in the erased state and Since it is via the p-channel transistor, there is a problem that the falling speed of the word line WLi is easily delayed. Further, in order to selectively apply the negative voltage to the word line, it is necessary to make the negative voltage generating circuit similar to the row decoder circuit, and there is a problem that the circuit becomes large accordingly.

Therefore, it is possible to apply a negative voltage to the word line by using the row decoder. However, in the flash memory, at the time of reading and writing, the selected word line WLi has a high voltage, and the unselected word line WLi
Lj (j ≠ i) must be set to the ground potential, but at the time of erasing, it is necessary to set the selected word line WLi to the negative potential and the non-selected word line WLj to the positive potential.

That is, at the time of reading and writing, (potential of the selected word line WLi)> (non-selected word line WL
j)), while at the time of erasing, (potential of selected word line WLi) <(non-selected word line WL)
j potential), and the relationship of the potential difference needs to be reversed. Therefore, when the row decoder supplies a negative voltage to be applied to the word line, the row decoder has a level conversion function to the negative voltage V _BB and the positive voltage V _CC in addition to the conventional level conversion function, and at the same time selects the word line. It is necessary to be able to reverse the level relation of the voltage applied to the word line with respect to the unselected logical value.

FIG. 64 is a functional block diagram of a row decoder when a negative voltage is applied to the word lines by the row decoder. As illustrated, the row decoder 503 includes a decoding unit 507, a logic conversion unit 508, a level conversion unit 509, and a driving unit 510. The decoding unit 507 is a unit that decodes the row decode signal RDC and determines whether the word line connected to this row decoder 503 is selected or unselected. The driving unit 510 has a large driving capability to drive the word line. Here, the decoding unit 50 other than the driving unit
7, the order of the logic conversion unit 508 and the level conversion unit 509 can be freely changed. For example, the level conversion unit 5
This is the case when 09 is arranged first. However, when the level conversion unit 509 is disposed on the front side, all the subsequent parts need to operate at the level-converted voltage level. In addition, the function of the logic conversion unit 508 is changed to the row decoder 103.
It is also possible to change the address signal itself without providing it, but in that case a part for converting the address signal is required.

In any case, the row decoder for applying a negative voltage to the word line needs the above-mentioned function, and there is a problem that the circuit configuration becomes complicated. As described above, erasing the flash memory is performed by drawing electrons from the floating gate to the channel or the source by utilizing the quantum tunnel effect. However, the current (tunnel current) caused by the extracted electrons is an exponential function of the electric field between the floating gate and the channel or the source, and when the electric field changes, the tunnel current changes exponentially. Since the electric field between the floating gate and the channel or the source is determined by the voltage between the control gate and the channel or the source, the tunnel current changes exponentially if the voltage changes. Since the magnitude of the tunnel current determines the erase time of the flash memory, if the voltage between the control gate and the channel or the source changes, the erase time also changes greatly.

When the voltage between the control gate and the channel or the source changes by 1 V, the erase time changes by about one digit. There is a standard for the erase time, and a flash memory that cannot be erased within the standard time is considered defective. Considering mounting a flash memory on a portable device, if the battery driving the portable device becomes weak, the voltage between the control gate and the channel or the source may become small at the time of erasing. At this time, for the reasons described above,
The erasing time will be significantly longer, and it will not be possible to erase within the standard time.
There is a problem that the frequency of being judged as defective increases.

The present invention has been made in view of the above problems, and provides a flash memory in which a row decoder capable of applying a negative voltage is realized by a simple circuit, and even when an external state such as a power supply voltage changes. An object of the present invention is to provide a flash memory having stable erase characteristics.

[0020]

In order to solve the above problems, a semiconductor memory device according to a first aspect of the present invention includes a memory cell array and a decoding unit for decoding a plurality of signals to access the memory cell array. A semiconductor memory device comprising: a first power supply terminal and a second power supply terminal, wherein an output of the decoding unit is input, and a voltage applied to the first power supply terminal or close to the voltage. A driving unit that selectively outputs a voltage and a voltage applied to the second power supply terminal or a voltage close to the voltage,
The driving unit supplies a first voltage to the first power supply terminal and a second voltage to the second power supply terminal, the second voltage being lower than the first voltage; A third voltage to the second power supply terminal and a third voltage to the second power supply terminal.
And a second operation mode for applying a fourth voltage higher than the above voltage, and the output voltage is switched according to the first or second operation mode.

According to a second aspect of the present invention, the first terminal is connected to an input terminal to which an input signal is input, and the second terminal is connected to a first output terminal to which a first output signal is output. A first connection switch element connected, and a second connection in which a first terminal is connected to the input terminal and a second terminal is connected to a second output terminal for outputting a second output signal. A switch element and an input terminal are connected to the second terminal of the first connection switch element, an output terminal is connected to the second output terminal, and a desired voltage higher than the power supply voltage is supplied in terms of power supply. A first inverter connected between the first voltage line connected to the first voltage line and a second voltage line supplied with a desired voltage equal to or lower than the ground voltage, and an input terminal connected to the second inverter of the second connection switch element. , The output terminal is connected to the first output terminal, and in terms of power supply, A level conversion circuit comprising a second inverter connected between the first voltage line and the second voltage line, and a level conversion circuit such as this. It is a flash memory included in the decoder.

The flash memory according to the third aspect of the present invention includes a negative voltage source for generating a voltage negative with respect to the potential of the substrate or well, and applies the generated negative voltage to the control gate. A flash memory for erasing charges in a floating gate, characterized by comprising voltage regulating means for regulating a negative voltage generated by a negative voltage source to a predetermined value with respect to a potential of a substrate or a well. .

[0023]

In the flash memory of the present invention, the logic converter can be omitted by implementing the logic conversion in the drive unit of the row decoder, thereby simplifying the circuit configuration. Therefore, the driving unit is configured to selectively output the voltage applied to the first power supply terminal and the second power supply terminal, and the voltage applied to the first power supply terminal and the second power supply terminal may be high or low depending on the mode. Reverse the relationship. Further, the level conversion circuit of the second aspect has a logic inversion function as well as a level conversion function, so that the circuit configuration becomes simple.

Here, a negative voltage is applied from the drive unit to the word line.
The conditions required to do so will be briefly described. Figure 1
FIG. 6 is a diagram showing an example of a row decoder according to the first aspect of the present invention.
Yes, (1) of FIG. 1 shows a circuit example, and (2) of FIG.
It is a figure which shows the constructional example of the moving part 5. Smell (1) in Figure 1
4 is a decoding unit, and 5 is a driving unit. level
The conversion circuit is provided in front of the decoding unit 4, but here
Is not shown. Power supply terminal V₁And V₂Write to and read from
And a high voltage V depending on each erasing mode_PPAnd zero voltage V _SS,
Positive voltage V_CCAnd zero voltage V_SSAnd negative voltage V_BBAnd positive voltage V_CCBut
The signal OD is applied and selected according to the input signal IDC.
C is V_INBecoming a p-channel transistor T_p3 is o
Power supply terminal V₁Is output. Unselected
N channel transistor T when selected_n3 is on
And power supply terminal V₂Is output.

Here, the driving section 5 has a double well structure as shown in FIG. This is to prevent the problem that when a negative voltage is applied to the terminal of the driving unit 5, the substrate and the diffusion layer are forward biased, a current flows, and a predetermined voltage cannot be output. FIG. 2 is a structural example of a drive unit of a conventional flash memory in which a negative voltage is not applied via a row decoder. (1) shows the case of the P-type substrate, and (2) shows the case of forming the P-well on the N-type substrate.

As shown in (1) of FIG.
In the case of "ell", if the substrate itself is lowered, the characteristics of the portion operating at the normal voltage change, and it cannot be partially made negative, which causes a problem that the load of the negative voltage generation circuit becomes heavy. Further, in the case of Pwell on the N-type substrate, the above problem can be solved by setting the potential of Pwell to a negative potential only at a necessary portion, but the substrate bias of the p-channel transistor can be partially set to V _PP during writing. The problem arises that you can't.

In order to prevent such a problem from occurring, the structure of the driving unit 5 driven by a negative voltage is (a) (1) in FIG.
As shown in, the Pw in the Nwell area on the P-type substrate
or a n-channel MOS transistor is formed in the well region, or (b) as shown in (2) of FIG. 3, the Nwell region is formed in the Pwell region on the N-type substrate, and P-channel type MOS transistor is formed on the substrate, or (c) SOI (Silicon On)
Insulator structure, that is, if a p-channel transistor or an n-channel transistor is formed on an insulating substrate and the Pwell region is negatively biased, a negative voltage is not applied to the control gate CG of the memory cell. It will be possible. Since the drive section of the present invention has any of the above structures, it is possible to apply a negative voltage in the row decoder.

Further, in the flash memory having another basic structure of the present invention, the negative voltage source generates a voltage negative with respect to the substrate or the well, and the negative voltage is applied to the control gate to erase the data. However, at this time, the voltage regulating means makes the voltage value of the negative voltage with respect to the substrate or the well constant. As a result, a constant voltage is applied between the control gate and the substrate or well regardless of the voltage fluctuation of the voltage source, so that stable erasing can be performed.

[0029]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 4 is a basic configuration diagram of the flash memory according to the first embodiment of the present invention. As shown in FIG. 4, the flash memory of the first embodiment includes a memory cell array 1, a row decoder 3, an address buffer predecoder 17, a level conversion circuit 9, a drive unit power supply switching circuit 11, a high voltage supply unit 13, and a low voltage. It is composed of a supply unit 14 and a power supply control circuit 15. In the present embodiment, the level conversion is not performed for each word line, but the level decoding circuit 9 uses the row decode signal R.
After converting the DC level, it is input to each decoding unit. As a result, the level conversion circuit 9 can be shared.

The memory cells constituting the memory cell array 1 have the structure shown in FIG. 61, as in the conventional example. The row decoder 3 includes a decoding unit 4 and a driving unit 5 for each word line WLi. Circuit diagrams of the decoding unit 4 and the driving unit 5 are shown in (1) and (2) of FIG. 5, respectively.

Decoding section 4 decodes a plurality of signals IDC from level conversion circuit 9 to access memory cell array 1. Further, the drive unit 5 includes a first power supply terminal 6 and a second power supply terminal 7, inputs the output of the decoding unit 4, and outputs the first power supply terminal 6 according to the voltage level of the input.
The voltage (V ₁ ) applied to the second power supply terminal 7 or a voltage close to the voltage and the voltage (V ₂ ) applied to the second power supply terminal 7 or a voltage close to the voltage are selectively output.

As for the structure of the driving unit 5, as shown in FIG. 3A, a Pwell region is formed in an Nwell region on a P-type substrate, and an n-channel MO is formed therein.
An S-transistor is formed, or as shown in FIG. 3B, an N-well region is formed in a P-well region on an N-type substrate and a p-channel MOS transistor is formed therein, or an SOI structure is formed. In other words, whether a p-channel transistor or an n-channel transistor is formed on an insulating substrate and the Pwell region is negatively biased.
It has one of two structures.

Further, as shown in (1) of FIG. 6, the decoding unit 4 outputs two-phase outputs ODC ₀ and ODC ₁ which are logically inverted, and the same driving unit 5 is used as shown in (2) of FIG. Type (n
(Type) transistors T _n 13 and T _n 14 can have the same function. That is, ODC
_{When the 0} signal is at "L" level, the ODC ₁ signal is at "H" level, the transistor T _n 13 is ON and the transistor T _n 14 is OFF. When the ODC ₀ signal is at “H” level, the ODC ₁ signal is at “L” level, the transistor T _n 13 is OFF, and the transistor T _n 1 is
4 is turned on.

The high voltage supply section 13 selectively supplies a positive potential (V _CC ) and a high potential (V _PP ) under the control of the control signal Con1 from the power supply control circuit 15. Further, the negative voltage supply unit 14 selectively supplies the zero potential (V _SS ) and the negative potential (V _BB ) under the control of the control signal Con1 from the power supply control circuit 15. In addition, the positive potential (V _CC ), the high potential (V _PP ), the zero potential (V _SS ), and the negative potential (V _BB ) are: negative potential (V _BB ) <zero potential (V _SS ) <positive potential (V _CC ) <high potential (V _PP ).

The level conversion circuit 9 converts the voltage level of the signal to the decoding section 4, and as shown in FIG.
An n-channel type having a first terminal 21 to which the output (V _IH ) of the high voltage supply unit 13 is supplied and a second terminal 22 to which the output (V _IN ) of the negative voltage supply unit 14 is supplied. It comprises MOS transistors T _n 5, T _n 6, and T _n 7, and p-channel type MOS transistors T _p 5, T _p 6, and T _p 7.

In the level conversion circuit 9, the output RDC of the address buffer predecoder 17 is at "H" level (V _CC ≤V
_IH ), the voltage applied to the first terminal 21 ( _VIH )
Alternatively, a voltage close to the voltage (V _IH ) is set to the voltage (V _IN ) applied to the second terminal 22 or the voltage (V _IN ) when the input RDC is at the “L” level (V _SS ≧ V _IN ). Selectively output a close voltage.

The drive section power supply switching circuit 11 switches the power supply potentials V ₁ and V ₂ supplied to the drive section 5, and as shown in FIG. 8, two level conversion circuits 25 as shown in FIG. And 26. The level conversion circuits 25 and 2 are used to switch the outputs V ₁ and V _2, respectively.
6, the control signal Con supplied from the power supply control circuit 15
2-1 and Con2-2. That is, the output V _{1 is set} to a positive potential (V _CC ) and the output V _{2 is set} to a zero potential (V _SS ) when reading data from the memory cell array 1, and the output V _{1 is set} to a high potential (V _PP ) when writing data to the memory cell array 1. ), The output V _{2 is set} to a zero potential (V _SS ) and the output V _{1 is set} to a negative potential (V _SS ) when erasing data in the memory cell array 1.
_BB ), and the output V ₂ is a positive potential (V _CC ).

In the semiconductor memory device of this embodiment, the memory cell
The read and write operations for the file are the same as the conventional example.
Will be done. That is, at the time of writing, the drive unit power supply
Output voltage V of switching circuit 11₁= High potential (V _PP), And
Output voltage V₂= Zero potential (V_SS), WLi = V
_PP(About 12 [V]), BLi = about 6 [V], S = 0
[V].

At the time of reading, the drive unit power source switching circuit 11
Output voltage V ₁ = positive potential (V _CC ), and output voltage V ₂
=, As zero potential (V _SS ), WLi = V _CC (about 5
[V]), BLi = about 1 [V], and S = 0 [V].
Further, in order to erase the information in the memory cell, the output voltage V ₁ of the driver power supply switching circuit 11 is a negative potential (V _BB ) and the output voltage V _{2 is a} positive potential (V _CC ), and WLi = V _BB and BLi. =
Open, S = V _CC .

At this time, in the driving section 5 of the row decoder 3, the on / off operation of the transistors T _p 3 and T _n 3 is the same as that at the time of reading and writing. That is, in the selected word line WLi, the p-channel type MOS transistor T _p 3 is turned on and the n-channel type MOS transistor T 3 is turned on.
_n 3 is off and unselected word line WLj (j ≠ i)
, The p-channel MOS transistor T _p 3 is off and the n-channel MOS transistor T _n 3 is on.

The difference between the erasing operation and the reading and writing operations is the potential applied to the diffusion layer (source side) on the opposite side (the other end) to the word line WLi. That is, the negative potential (V _BB ) is applied to the source side of the p-channel MOS transistor T _p 3 and the positive potential (V _CC ) is applied to the source side of the n-channel MOS transistor T _n 3.

At this time, the selected word line WLi
Is a p-channel MOS transistor T_p3 turns on
However, the potential of the word line WLi is negative (V_BB) To
On the other hand, a p-channel MOS transistor T_pThree threshold
Hold voltage V_thIt becomes a low value, and
In the selected word line WLj, an n-channel type MOS
Transistor T_n3 is on, but word line WLj
Is the positive potential (V _CC) To n-channel MOS
Transistor T_n3 threshold voltage V_thLower value
It has become.

The negative potential during erasing is V_BBWith a value equal to
It doesn't have to be. Potential V_BBIs an internally generated potential,
The voltage applied to the word line WLi becomes a value suitable for erasing.
Sea urchin, threshold voltage V_thGenerates a voltage with minutes added
You can make it live. In addition, due to the substrate bias effect, p channel
Type MOS transistor T_p3 threshold voltage V _th
And n-channel MOS transistor T_nThreshold 3
Field voltage V_thIs a relatively large value.

The above is the description of the first embodiment, but the level conversion circuit 9 shown in FIG. 7 will be described in more detail.
In the following explanation, each potential is zero potential (ground potential).
Since it is realized by applying a voltage with reference to V _SS , the potentials V _PP , V _CC , V _SS and V _BB are respectively set to the high voltage V.
_It may be called _PP , positive voltage V _CC , zero voltage V _SS , and negative voltage V _BB .

In this level conversion circuit 9, a positive potential V_CCOr
Zero potential V_SSThe input signal RDC having the amplitude of
V_IHAnd V_INAn output having a potential corresponding to the voltage applied to
It can be converted into a force signal IDC. Therefore, the power supply terminal V_IHAnd V
_INHigh voltage V_PPAnd zero (ground) voltage V_SSIf you enter
Potential V_PPTo zero potential V_SSConverted to a signal of varying amplitude
Yes, power supply terminal V_IHAnd V_INPositive voltage V_CCAnd negative voltage V_BBTo
If input, positive potential V _CCTo negative potential V_BBShakes up to
Can be converted to a width signal.

As shown in FIG. 7, this level conversion circuit
Is a p-channel transistor T for pull-up_p6
And an n-channel transistor T for blocking high voltage_n5
And a p-channel transistor T for blocking negative voltage_p5
And pull-down n-channel transistor T_n6 and
Is the power supply terminal V_IHAnd V_INAre connected in series between. So
And output p-channel transistor T_p7 and n for output
Channel transistor T_n7 is the power supply terminal V_IHAnd V_INof
It is connected in series between the
Dista T_pThe gate of 7 is a pull-up transistor T_p
6 and high voltage blocking transistor T_nConnected to 5 connection points
Output n-channel transistor T_nGate 7
Negative voltage blocking transistor T_p5 and pull-down tran
Dista T_nIt is connected to 6 connection points. Output p-cha
Tunnel transistor T_p7 and output n-channel tran
Dista T_nThe connection point of 7 is a pull-up transistor T
_p6 and pull-down transistor T_nConnected to the gate of
Has been. High voltage blocking transistor T_nTo the gate of 5
Is the positive voltage V_CCIs applied to the channel and zero (ground)
Pressure V_SSIs being applied. Negative voltage blocking transistor T
_pZero voltage V is applied to the gate of 5 _SSIs applied to the channel
Is the positive voltage V_CCIs being applied. Input signal RDC is high voltage
Pressure blocking transistor T_n5 and negative voltage blocking transistor
T_p5 is input to the connection point and the output signal is the output p-channel.
Tunnel transistor T_p7 and output n-channel tran
Dista T_nObtained from 7 connection points.

Next, regarding the operation of the level conversion circuit of FIG.
explain. Now input terminal in positive potential V_CC(H) signal
Is input, and the zero potential V is input as the input signal RDC._SSSignal of
Is output. At this time, the output signal IDC is the power supply terminal
V _IHPotential V applied to_PPbecome. Input terminal from this state
The potential of the signal applied to the child in is V_CCTo V_SSChanged to
Suppose In response to this, the input signal to the level conversion circuit 9
RDC is positive potential V_CCChange to low voltage blocking transistor
T_p5 turns on and raises the potential at point n3
It At this time, the pull-down transistor T_n6 is on
Therefore, the point n2 is the power supply terminal V_INConnected to
However, the pull-down transistor T_n6 ability small
By setting it in advance, it is possible to limit the through current in this portion.
The potential at the point n3 is also the output n-channel transistor T_n7
Since it only needs to be turned on to as high as possible, there is no problem.
Yes. N-channel transistor T for output_n7 is on
Therefore, the potential at the point n4 drops and the pull-up
Langista T_p6 is turned on, and the potential at point n1 becomes
Source terminal V_IHPotential V corresponding to the voltage applied to_PPbecome
To rise. Therefore, p-channel transistor for output
T_p7 changes to the off state, and the potential at point n4 drops further
Then power supply terminal V_INPotential V_BBApproach. And at point n4
Since the potential drops, pull-down transistor T_n6 is
Turns on and the transition ends. This state is stable
And the positive potential V is applied to the input terminal in_CCSignal is applied
As long as this state is maintained.

The potential applied to the input terminal in is the positive potential V
The operation at the time of changing from _CC to the zero potential V _SS starts from the decrease of the potential at the point n1 contrary to the above, but the same description as the above operation can be made and is omitted here. Although the level conversion circuit of FIG. 7 has been described above, as is apparent from the description, when one of the output transistors is turned on, the other output transistor is still on. For a moment, both the output transistors T _p 7 and T _n 7 may be turned on. At this time, a through current flows through both transistors, and the potential at the point n4 becomes the intermediate potential. This point n
Since the potential of No. 4 is applied to the pull-up transistor T _p 6 and the pull-down transistor T _n 6 as the gate potential, it is necessary to set the capability of each transistor so that it can change beyond the threshold value of these transistors.

As described above, the level conversion circuit 9 of FIG. 7 has a problem that a large through-current flows when a signal changes, and at the same time, it is necessary to set the capability of the transistor so that the normal operation can be performed. There was a problem that setting was difficult. The second embodiment is a level conversion circuit that solves these problems. FIG. 9 is a diagram showing the configuration of the level conversion circuit of the second embodiment. The difference from the circuit of FIG. 7 is that a resistance element is provided between the output p-channel transistor T _p 7 and the output n-channel transistor T _n 7. a point having a depletion type n-channel transistor T8 as component, the output and the 2p channel transistor T _p 9 for being further connected in series with the output unit outputs 2
The point is that an n-channel transistor T _n 9 is provided. Gate of pull-up transistor T _p 6 and n for second output
The gate of the channel transistor T _n 9 is connected to the drain of the output n-channel transistor T _n 7, and the gate of the pull-down transistor T _n 6 and the gate of the output second p-channel transistor T _p 9 are the output p-channel transistor T _p. 7 is connected to the drain.
The output signal at the output terminal 24 of the circuit of FIG. 9 is opposite to the output signal IDC of the circuit of FIG.

The operation of the circuit of FIG. 9 is almost the same as that of the circuit of FIG. 7, except that the p-channel transistor T _p for output is used.
7 and the output n-channel transistor T _n 7 are both turned on, the depletion type transistor T8
Limits the shoot-through current. Since the transistor T8 is a depletion type and performs a constant current operation regardless of the potential difference, a through current can be prevented. Further, the gates of the pull-up transistor T _p 6 and the pull-down transistor T _n 6 are connected to points n4 and n5 at both ends of the depletion type transistor T8, respectively, and the potential difference generated between the drain and the source of the depletion type transistor T8 causes Since it is surely turned on, the balance setting of the transistor becomes easy.

Further, in the circuit of FIG. 9, since there is a time difference in the change in the potential difference between the points n4 and n5, the output second p-channel transistor T _p 9 and the output second n-channel transistor T _n 9 are simultaneously turned on. To prevent the occurrence of through current. As is clear from the above description, the depletion type transistor T8 has points n4 and n5.
It operates so as to limit the current flowing between the two and generate a potential difference between both ends. Such operation can also be realized by a resistance element.

As described above, the level conversion circuit is a circuit used when signals are transmitted between circuits having different power supply voltages. In the circuit of the first embodiment shown in FIG. 4, the address buffer decoder 17 and the row buffer are used. Used for level conversion with the decoder 3. However, as described above, it is possible to provide the level conversion circuit immediately before the drive unit 5 of the row decoder 3, in which case the normal positive voltage V _CC and the zero voltage V _SS are supplied to the decode unit 4. It

In the flash memory, in order to apply a negative voltage from the row decoder to the word line, it is necessary to reverse the logic inside the row decoder only when the negative voltage is applied. Therefore, in the first embodiment, the logic conversion circuit is omitted by inverting the voltage applied to the power supply terminal of the drive unit 5. However, a logic inversion circuit may be separately provided to invert the logic of selection and non-selection of word lines. In the third embodiment, the logic switching is possible in the circuit of FIG. 9 and it can be used as the drive unit 5 of FIG.

FIG. 10 is a circuit in which an n-channel transistor T _n 10 and a p-channel transistor T _p 10 are added to the circuit of FIG. 9, and the complementary signals S _P and S _N applied to the logic inverting terminals 25 and 26 are inverted. This inverts the output. As shown in the figure, the level conversion circuit of FIG. 10 has an n-channel transistor T _n whose drains are connected to the high voltage blocking transistor T _n 5 of the circuit of FIG. 9 and whose one gate and the other source are respectively connected. 10 and the drains of the negative voltage blocking transistor T _p 5 are connected to each other,
A p-channel transistor T _p 10 to which one gate and the other source are connected is provided.
The gates of the high voltage blocking transistor T _n 5 and the negative voltage blocking transistor T _p 5 are connected to the logic inverting terminals 25 and 26, respectively.

The logical value table of the circuit of FIG. 10 is as follows.

[0056]

[Table 1]

The operation of the circuit of FIG. 10 will be described. Logic inversion
Switching signal S to the terminal 25 for_PPositive voltage V_CCIs applied
Signal S at terminal 26_NAs zero voltage V_SSIs applied
N-channel transistor T _n10 and pcha
Tunnel transistor T_p10 is turned off, and as shown in FIG.
It becomes the same circuit as the circuit. Therefore, at this time, it is the same as the circuit of FIG.
The same operation.

Signal applied to logic inversion terminals 25 and 26
S_PAnd S_NReverse and S_PZero potential V_SSAnd S_NPositive
Potential V_CCIn case of, the high voltage blocking transistor T_n5
And a negative voltage blocking transistor T_p5 is turned off,
n-channel transistor T _n10 is for high voltage blocking
Operating as a p-channel transistor T_p10 is negative voltage
It will work as a blocker. The operation of this circuit is
It is a high voltage that is turned on with respect to the level of the signal RDC
Either a blocking transistor or a negative voltage blocking transistor
The only difference is the operation of the circuit of FIG.
Is similar to the circuit of FIG.

The portion where the transistors T _n 10 and T _p 10 are added for logical inversion can be applied to the circuit of FIG. When the circuit of FIG. 10 is used as the driving unit 5 of the row decoder 3, the driving capability of the output second p-channel transistor T _p 9 and the output second n-channel transistor T _n 9 is set so that the word line can be driven. Be sufficiently large. Then, the potential levels of the signals _SP and _SN supplied to the logic inversion input terminals 25 and 26 are inverted at the time of writing and reading and at the time of erasing. In that case, the positive voltage V _CC and the zero voltage V _SS are supplied to the decoding unit 4, and the high voltage supply unit 13 and the negative voltage are supplied to the power supply terminals V _IH and V _IN of the level conversion circuit of FIG. The voltage is directly supplied from the supply unit 14, and the drive unit power supply switching circuit 11 is not necessary.

Next, a simpler level conversion circuit having a logical inversion function will be shown as a fourth embodiment. FIG. 11 is a diagram for explaining the principle of the level conversion circuit of the fourth embodiment, in which 44 is an input terminal to which the input signal in is input, and 45 is an output signal S.
₁ is an output terminal, 46 is an output terminal from which an output signal S ₂ is output, 47 and 48 are connection switch elements, 49 and
50 is an inverter.

Here, the connection switch element 47 has its one terminal 47A connected to the input terminal 44 and the other terminal 47B connected to the output terminal 45, and the connection switch element 48 has its one terminal. 48A input terminal 44
, And the other terminal 48B is connected to the output terminal 46. Further, the inverter 49 has its input terminal connected to the terminal 47B of the connection switch element 47 and its output terminal connected to the output terminal 46, and in terms of power supply, it has a desired voltage equal to or higher than the power supply voltage V _CC. It is connected between a voltage line 51 supplied with V _IH and a voltage line 52 supplied with a desired voltage V _IN equal to or lower than a zero (ground) voltage V _SS .

The inverter 50 has its input terminal connected to the terminal 48B of the connection switch element 48 and its output terminal connected to the output terminal 45. Further, in terms of power supply, the voltage line 51 and the voltage line 51 are connected. And 52. When the H level of the input signal in is the power supply voltage V _CC and the L level is the zero (ground) voltage V _SS , V _IH ≧ V _CC , V _IN ≦
Since it is V _SS , the level conversion circuit of the present invention is, for example,
It operates as shown in the truth table in Table 2.

[0063]

[Table 2]

Therefore, the voltage values of the voltages V _IH and V _IN are set to V
By setting the desired value within the range of _IH ≥ V _CC and V _IN ≤ V _SS and controlling the ON (ON) and OFF (OFF) of the connection switch elements 47 and 48, V _IH ≥ V _CC and V _IN ≤ V It is possible to convert to a signal of a desired voltage within the _SS range, and it is also possible to use a mode in which no level conversion is performed. Further, in particular, the current state can be latched by turning off both the switch elements 47 and 48. It is also possible to turn off both the connection switch elements 47 and 48, latch the current state, and then change the voltages V _IH and V _IN to control to output a desired voltage.

Here, the level conversion circuit of the present invention has two connection switch elements 47 and 48 and two inverters 4.
9 and 50, the chip area can be reduced when this is used in a flash memory that requires a level conversion circuit, for example. The specific configuration and operation of the level conversion circuit of the fourth embodiment will be described below in order with reference to FIGS.

FIG. 12 is a diagram showing the configuration of the level conversion circuit of the fourth embodiment. 61 is an input terminal to which an input signal in is input, T _p 15 is a pMOS transistor forming a connection switch element, and 62 is a pMOS transistor. O of T _p 15
A control signal input terminal to which a control signal LP for controlling N and OFF is input. Further, T _n 15 is an nMOS transistor forming a connection switch element, and 63 is a control signal input terminal to which a control signal LN for controlling ON / OFF of the nMOS transistor T _n 15 is input.

Reference numerals 58 and 59 are inverters, and
_p 16, T _p 17 are pMOS transistors, T _n 16,
T _n 17 is an nMOS transistor. The input end of the inverter 58 and the output end of the inverter 59 are connected, and the output end of the inverter 58 and the input end of the inverter 59 are also connected. Further, 64 is a V ₁ voltage line to which the positive potential V _CC or the high potential V _PP is supplied as the voltage V _IH , and 65
Is a V ₂ voltage line to which the zero potential V _SS or the negative voltage V _BB is supplied as the voltage V _IN , 66 is an output terminal for outputting the output signal S ₁ , and 67 is an output terminal for outputting the output signal S _2. .

Although not shown, the pMOS transistors T _p 15, T _p 16, and T _p 17 are applied with the voltage V _IH on their substrates (wells) and the nMOS transistor T
_A voltage V _IN is applied to the substrate (well) of _n 15, T _n 16, and T _n 17. Next, the operation of the circuit shown in FIG. 12 will be described. Table 3 is a truth table showing the operation of this level conversion circuit, and FIGS. 13 to 20 are circuit diagrams showing the operation of this level conversion circuit.

[0069]

[Table 3]

That is, this level conversion circuit has, as modes, a non-conversion mode, an inversion mode, a high voltage conversion mode, a negative voltage conversion mode and a latch mode. First,
In the non-conversion mode, as shown in FIG. 13, the potential V _IH =
V _CC , potential V _IN = V _SS , control signal LP = V _CC , control signal LN = V _CC , pMOS transistor T _p 15 = OF
F, nMOS transistor T _n 15 = ON.

Here, when the input signal in = “L”, p
MOS transistor T _p 17 = ON, nMOS transistor T _n 17 = OFF, pMOS transistor T _p 16
= OFF, the nMOS transistor T _n 16 = ON, the output signal S ₁ = V _CC and the output signal S ₂ = V _SS . On the other hand, when the input signal in = “H”, as shown in FIG. 14, the pMOS transistor T _p 17 = OFF, nMO
S transistor T _n 17 = ON, pMOS transistor T _p 16 = ON, nMOS transistor T _n 16 = OF
At F, the output signal S ₁ = V _SS and the output signal S ₂ = V _CC .

Further, in the case of the inversion mode, it is shown in FIG.
So that the potential V_IH= V_CC, Potential V _IN= V_SS,Control signal
LP = V_SS, Control signal LN = V_SSThen, pMOS transistor
Star T_p15 = ON, nMOS transistor T_n15 =
It is turned off. Here, if the input signal in = “L”
PMOS transistor T_p16 = ON, nMOS transistor
Langista T_n16 = OFF, pMOS transistor T
_p17 = OFF, nMOS transistor T_n17 = ON
And the output signal S₁= V_SS, Output signal S₂= V_CCBecomes

On the other hand, when the input signal in = “H”, as shown in FIG. 16, the pMOS transistor T _p 1
6 = OFF, nMOS transistor T _n 16 = ON, p
With the MOS transistor T _p 17 = ON and the nMOS transistor T _n 17 = OFF, the output signal S ₁ = V _CC and the output signal S ₂ = V _SS . Further, in the high voltage conversion mode, as shown in FIG. 17, the potential V _IH = V _PP and the potential V _IN =
V _SS , control signal LP = V _PP , control signal LN = V _CC , p
The MOS transistor T _p 15 = OFF and the nMOS transistor T _n 15 = ON.

If the input signal in = “L”, then p
MOS transistor T _p 17 = ON, nMOS transistor T _n 17 = OFF, pMOS transistor T _p 16
= OFF and the nMOS transistor T _n 16 = ON, the output signal S ₁ = V _PP and the output signal S ₂ = V _SS . In this case, since the control signal LP = V _PP , the pMOS transistor T _p 15 is not turned on, and the inverter 59
It is possible to prevent the current from flowing backward from the output end side of the input terminal to the input terminal 53 side.

On the other hand, when the input signal in = “H”, as shown in FIG. 18, the pMOS transistor T _p 1
7 = OFF, nMOS transistor T _n 17 = ON, p
When the MOS transistor T _p 16 = ON and the nMOS transistor T _n 16 = OFF, the output signal S ₁ = V _SS and the output signal S ₂ = V _PP . In this case, the control signal LN =
Since it is set to V _CC , the potential V _PP of the output signal S ₂ is not applied to the input terminal 53.

Further, in the case of the negative voltage conversion mode, FIG.
As shown in FIG. 9, potential V _IH = V _CC , potential V _IN = V _BB , control signal LP = V _SS , control signal LN = V _BB , pMOS transistor T _p 15 = ON, nMOS transistor T _n
15 = OFF. Here, the input signal in = “L”
, PMOS transistor T _p 16 = ON, nMO
S transistor T _n 16 = OFF, pMOS transistor T _p 17 = OFF, nMOS transistor T _n 17 =
When turned on, the output signal S ₁ = V _BB and the output signal S ₂ = V _CC .

On the other hand, when the input signal in = “H”, as shown in FIG. 20, the pMOS transistor T _p 1
6 = OFF, nMOS transistor T _n 16 = ON, p
With the MOS transistor T _p 17 = ON and the nMOS transistor T _n 17 = OFF, the output signal S ₁ = V _CC and the output signal S ₂ = V _BB . In this case, since the control signal LN = V _BB is set, the nMOS transistor 56 is not turned on, and it is possible to prevent the current from flowing backward from the input terminal 53 side to the output terminal 67 side, and at the same time, to control the control signal. L
Since P = V _SS , the input terminal 53 and the output terminal 6
It is possible to prevent the current from flowing backward due to the potential difference between 7.

The potential V_IH= V_CCOr V_PP, Potential V_IN
= V_SSOr V_BB, Control signal LP = V _IH, Control signal LN =
V_INIn case of, the pMOS transistor T_p15 =
OFF, nMOS transistor T_n15 = OFF
The current state can be latched. Note that p
MOS transistor T_p15 = OFF, nMOS transistor
Dista T_n15 = OFF, latch current state
After the voltage V₁Or voltage V₂To change the output signal S
₁Or output signal S₂The voltage of can also be changed.

As described above, the level conversion circuit shown in FIG. 12 has three pMOS transistors T _p 15, T _p 16,
T _p 17 and three nMOS transistors T _n 15 and T _n
16 and T _n 17 and requires a small number of transistors. Therefore, when this is used, for example, in a flash memory that requires a level conversion circuit, the chip area can be reduced. Can be achieved.

The level conversion circuit of the fourth embodiment also has a logic inversion function and can be used as it is as a drive unit of a row decoder of a flash memory. When the level conversion circuit of FIG. 12 is used as the driving unit 5 of FIG. 4, the high voltage supply unit 13 and the negative voltage supply unit 1 are connected to the power input terminals V _IH and V _IN.
The power supply voltage is directly supplied from the drive unit 4, and the drive unit power supply switching circuit 1
1 is no longer needed.

FIG. 21 shows the configuration when the level conversion circuit of the fourth embodiment is applied to a row decoder of flash memory. The parts corresponding to those in FIG. 12 are designated by the same reference numerals. In the figure, 68 is a NAND circuit for decoding an internal row address signal supplied from a row address buffer (not shown), 69 is a level conversion circuit for converting the level of the output of the NAND circuit 68, and 70 is a flash memory cell. Transistors, WL is a word line, and BL is a bit line. In this example, the word line WL is connected to the output terminal 66 of the level conversion circuit 69.

Table 4 is a truth table showing the operation of the row decoder, and FIGS. 22 to 27 are circuit diagrams showing the operation of the row decoder.

[0083]

[Table 4]

That is, in this row decoder, reading
At this time, as shown in FIG. 22, the voltage V _IH= V_CC, Voltage V_IN
= V_SS, Control signal LP = V_CC, Control signal LN = V_CCTosa
PMOS transistor T_p15 = OFF, nMOS
Transistor T_n15 = ON. Here this
When the decoder is selected, the output of the NAND circuit 68 =
"L", pMOS transistor T_p17 = ON, nM
OS transistor T_n17 = OFF, pMOS transistor
Star T_p16 = OFF, nMOS transistor T_n16
= ON, the potential of the output terminal 66 = V_CCAnd this
Are supplied to the word line WL.

On the other hand, this row decoder is not selected
23, the NAND circuit, as shown in FIG.
Output of 68 = “H”, pMOS transistor T_p17
= OFF, nMOS transistor T_n17 = ON, pM
OS transistor T_p16 = ON, nMOS transistor
T_n16 = OFF, the potential of the output terminal 66 = V _SS
And is supplied to the word line WL.

At the time of writing, as shown in FIG. 24, the potential V _IH = V _PP , the potential V _IN = V _SS , the control signal LP =
V _PP , control signal LN = V _CC , pMOS transistor T _p 15 = OFF, nMOS transistor T _n 15 =
Turned on. When this row decoder is selected, the output of the NAND circuit 68 = “L”, the pMOS transistor T _p 17 = ON, and the nMOS transistor T _n 1
7 = OFF, pMOS transistor T _p 16 = OFF,
The nMOS transistor T _n 16 = ON, the potential of the output terminal 66 = V _PP, and this is supplied to the word line WL.

In this case, since the control signal LP = V _PP , the pMOS transistor T _p 15 is not turned on, and the current is prevented from flowing backward from the output end side of the inverter 59 to the NAND circuit 68 side. be able to. On the other hand, when this row decoder is deselected,
As shown in FIG. 25, the output of the NAND circuit 68 = “H”
, PMOS transistor T _p 17 = OFF, nMOS
Transistor T _n 17 = ON, pMOS transistor T
_p 16 = ON, nMOS transistor T _n 16 = OFF
Then, the potential of the output terminal 66 is set to V _SS , which is supplied to the word line WL.

When erasing, as shown in FIG.
Voltage V _IH = V _CC , voltage V _IN = V _BB , control signal LP =
V _SS , control signal LN = V _BB , pMOS transistor T _p 15 = ON, nMOS transistor T _n 15 = O
FF. When this row decoder is selected, the output of the NAND circuit 68 = “L”, the pMOS transistor T _p 16 = ON, and the nMOS transistor T _n 1
6 = OFF, pMOS transistor T _p 17 = OFF,
The nMOS transistor T _n 17 = ON, the potential of the output terminal 66 = V _BB, and this is supplied to the word line WL.

On the other hand, this row decoder is not selected
27, the NAND circuit, as shown in FIG.
Output of 68 = “H”, pMOS transistor T_p16
= OFF, nMOS transistor T_n16 = ON, pM
OS transistor T_p17 = ON, nMOS transistor
T_n17 = OFF, voltage of output terminal 66 = V _CC
And is supplied to the word line WL.

Thus, according to this row decoder,
If necessary, a positive voltage V may be applied to the word line WL._CC,zero
(Ground) voltage V_SS, High voltage V_PPOr negative voltage V_BBSupply
You can The potential V_IH= V_CCOr V_PP,potential
V_IN= V_SSOr V_BB, Control signal LP = V _IH, Control signal L
N = V_INIn case of, the pMOS transistor T_p1
5 = OFF, nMOS transistor T_n15 = OFF
Then, the current state can be latched.

Further, the pMOS transistor T_p15 = O
FF, nMOS transistor T_n15 = OFF,
After latching the current state, the potential V_IHOr potential V_INTo
By changing the voltage supplied to the word line WL
It can be changed. As described above, the level of FIG.
Use the conversion circuit for the row decoder of flash memory.
Then, the level conversion circuit 69 of the row decoder has three p
MOS transistor T_p15, T_p16, T_p17,
Three nMOS transistors T_n15, T _n16, T_n
The area occupied by the row decoder is 17
Can be reduced, and the chip area can be reduced.

As described above, the level conversion circuit of the fourth embodiment shown in FIG. 12 can be used as it is in the drive section of the row decoder, and the output of the second inverter circuit drives the word line. However, since the word line has a large load, the word line is not directly driven by the output of the inverter circuit, but a driver circuit for driving the word line is further provided.
This is an example.

FIG. 28 is a circuit diagram showing an essential part of the flash memory of the fifth embodiment, showing one row decoder. The parts corresponding to those in FIGS. 12 and 21 are designated by the same reference numerals. In the figure, reference numeral 71 is a level conversion circuit for converting the level of the output of the NAND circuit 68, and the level conversion circuit 71 is constructed by using an embodiment of the level conversion circuit shown in FIG.

Further, T _p 18 is a pMOS transistor,
T _n 18 is an nMOS transistor, and these pMO
S transistor T _p 18 and nMOS transistor T _n 1
An inverter 72 forming a word line driver is constituted by 8 and. Here, the source of the pMOS transistor T _p 18 is connected to the V _IH voltage line 64, the source of the nMOS transistor T _n 18 is connected to the V _IN voltage line 65, and p
The connection point 73 between the gate of the MOS transistor T _p 18 and the gate of the nMOS transistor T _n 18 is connected to the output terminal 67 of the level conversion circuit 71, and the drain of the pMOS transistor T _p 18 and the nMOS transistor T _n 18 are connected.
A connection point 74 with the drain of is connected to the word line WL. Inverter 7 forming a word line driver in this way
The output of the first inverter circuit is input to 2.

The truth table showing the operation of this row decoder is the same as that shown in Table 4, and in this row decoder, the positive voltage V is applied to the word line WL as required.
It is possible to supply _CC , zero voltage V _SS , high voltage V _PP or negative voltage V _BB, and also to perform a latch operation. According to the flash memory of the fifth embodiment, the level conversion circuit 71 has three pMOS transistors T _p 15,
T _p 16, T _p 17, and three nMOS transistors T
Since it is composed of _n 15, T _n 16, and T _n 17, the area occupied by the row decoder can be reduced and the chip area can be reduced in the flash memory provided with the word line driver.

FIG. 29 is a circuit diagram showing the main part of the flash memory of the sixth embodiment, showing one row decoder. The parts corresponding to those in FIGS. 12 and 21 are designated by the same reference numerals. In the figure, reference numeral 75 is a level conversion circuit for converting the level of the output of the NAND circuit 68. This level conversion circuit 75 is also constructed by using an embodiment of the level conversion circuit according to the present invention shown in FIG.

Further, T _n 19 and T _n 20 are nMOS transistors, and these nMOS transistors T _n 1
A push-pull circuit 76, which forms a word line drive circuit, is constituted by 9, T _n 20. In this example, the drain of the nMOS transistor T _n 19 is connected to the V _IH voltage line 64, the source of the nMOS transistor T _n 20 is connected to the V _IN voltage line 65, and the gate of the nMOS transistor T _n 19 is the level conversion circuit. 75, the gate of the nMOS transistor T _n 20 is connected to the output terminal 67 of the level conversion circuit 75, the source of the nMOS transistor T _n 19 and the nMOS transistor T _n 2 are connected.
The connection point 77 with the drain of 0 is connected to the word line WL.

A truth table showing the operation of this row decoder is similar to that of Table 3, and also in this row decoder, the power supply voltage V _CC and the zero (ground) voltage V are applied to the word lines WL as required. _SS , a high voltage V _PP or a negative voltage V _BB can be supplied, and a latch operation can be performed.
According to the flash memory of the sixth embodiment, the level conversion circuit 75 has three pMOS transistors T _p 15, T.
_p 16, T _p 17, and three nMOS transistors T _n
Since it is composed of 15, T _n 16 and T _n 17, the area occupied by the row decoder can be reduced and the chip area can be reduced in the flash memory provided with the word line driver.

Next, another example in which the level conversion circuit of FIG. 12 is used for a row decoder of a flash memory is shown in a seventh embodiment. FIG. 30 is a circuit diagram showing the main part of the flash memory of the seventh embodiment, showing one row decoder. The parts corresponding to those in FIGS. 12 and 21 are designated by the same reference numerals.

In the seventh embodiment, the row decoder comprises a main row decoder 78 and a sub row decoder 79. Note that WL _{0 to} WL ₃ are word lines. In the main row decoder 78, reference numeral 80 is a level conversion circuit for converting the level of the output of the NAND circuit 68. The level conversion circuit 80 is constructed by utilizing an embodiment of the level conversion circuit according to the present invention shown in FIG. ing.

In the sub row decoder 79, 8
Reference numerals _{10 to} 81 ₃ denote word line drive circuits, and 82 ₀ to
Reference numeral 82 ₃ denotes a positive voltage V _CC , high voltage V _PP or a V ₃ voltage line for supplying a zero voltage V _SS , and 83 _{0 to} 83 ₃ denotes a zero voltage V _SS , a negative voltage V _BB or a power supply voltage V _CC V ₄ Voltage line, T _p 20
_{0 ~T p 20 3, T p} 21 0 ~T p 21 3 are pMOS _{transistors, T n 20 0 ~T n 20} 3, T n 21 0 ~T
_n 21 ₃ is an nMOS transistor.

Here, the output terminal 6 of the level conversion circuit 80
6, the output terminal 6 of the pMOS transistor T _p 21 ₀ ~T _p 21 ₃ and the nMOS transistor T _n 21 ₀ ~T _n 21 ₃ of which is connected to the gate, the level conversion circuit 80
7 is connected to the gates of the pMOS transistors T _p 20 _{0 to} T _p 20 ₃ and the nMOS transistors T _n 20 _{0 to} T _n 20 ₃ .

In this example, at the time of reading, V₃Voltage line
82₀~ 82₃One of V₃Voltage line = V_CC,
Other V₃Voltage line = V_SS, V_FourVoltage line 83₀~ 83₃
= V _SSIt is said that When writing, V₃Voltage line 82
₀~ 82₃One of V₃Voltage line = V_PP,That
Other V₃Voltage line = V_SS, V_FourVoltage line 83₀~ 83₃= V
_SSIt is said that

At the time of erasing, V ₃ voltage lines 82 ₀ to 8 8
2 ₃ = V _CC , one of the V ₄ voltage lines 83 _{0 to} 83 ₃ is V ₄ voltage line = V _BB , and the other V ₄ voltage line = V _CC . Table 5 is a truth table showing the operation of the level conversion circuit 80, and FIGS. 31 to 36 are circuit diagrams showing the operation of the row decoder.

[0105]

[Table 5]

That is, in this row decoder, at the time of reading, as shown in FIG. 31, the potential V _IH = V _CC , the potential V _IN = V _SS , the control signal LP = V _CC , and the control signal LN = V _CC.
Then, pMOS transistor T _p 15 = OFF, nMOS
The transistor T _n 15 = ON. If this row decoder is selected here, the output of the NAND circuit 68 =
“L”, pMOS transistor T _p 17 = ON, nM
OS transistor T _n 17 = OFF, pMOS transistor T _p 16 = OFF, nMOS transistor T _n 16
= ON, the potential of the output terminal 66 = V _CC , the output terminal 6
7 potential = V _SS .

As a result, the nMOS transistor T_n21
₀~ T_n21₃= ON, pMOS transistor T_p21
₀~ T_p21₃= OFF, pMOS transistor T_pTwo
0₀~ T_p20₃= ON, nMOS transistor T_nTwo
0₀~ T_n20₃= OFF. Here, for example,
Line WL₀If is selected, V₃Voltage line 82₀=
V _CC, V₃Voltage line 82₁~ 82₃= V_SS, V_FourVoltage line 8
Three₀~ 83₃= V_SSIt is said that As a result, the word line WL
₀= V_CC, Word line WL₁~ WL₃= V_SSIt is said that

On the other hand, when this row decoder is not selected, as shown in FIG. 32, the output of NAND circuit 68 is "H" and pMOS transistor T _p 17
= OFF, nMOS transistor T _n 17 = ON, pM
The OS transistor T _p 16 = ON, the nMOS transistor T _n 16 = OFF, the output terminal 66 = V _SS , and the output terminal 67 = V _CC .

As a result, the nMOS transistor T _n 21
_{0 to} T _n 21 ₃ = OFF, pMOS transistor T _p 2
_{1 0 ~T p 21 3 = ON} , pMOS transistor T _p 2
0 _{0 to} T _p 20 ₃ = OFF, nMOS transistor T _n
20 _{0 to} T _n 20 ₃ = ON. So, for example, V
₃ voltage lines 82 ₀ = V _CC , V ₃ voltage lines 82 _{1 to} 82 ₃ = V
_{Even if the SS} and V ₄ voltage lines 83 _{0 to} 83 ₃ = V _SS are set, the word lines WL _{0 to} WL ₃ = V _SS are set.

At the time of writing, as shown in FIG. 33, the potential V _IH = V _PP , the potential V _IN = V _SS , the control signal LP =
With V _PP and control signal LN = V _CC , pMOS transistor T
_p 15 = OFF, nMOS transistor T _n 15 = ON
It is said that If this row decoder is selected here,
When the output of the NAND circuit 68 is “L”, the pMOS transistor T _p 17 = ON and the nMOS transistor T _n 17 =
OFF, pMOS transistor T _p 16 = OFF, nM
The OS transistor T _n 16 = ON and the output terminal 66
Voltage = V _PP and the voltage of the output terminal 67 = V _SS .

As a result, the nMOS transistor T_n21
₀~ T_n21₃= ON, pMOS transistor T_p21
₀~ T_p21₃= OFF, pMOS transistor T_pTwo
0₀~ T_p20₃= ON, nMOS transistor T_nTwo
0₀~ T_n20₃= OFF. Here, for example,
Line WL₀If is selected, V₃Voltage line 82₀=
V _PP, V₃Voltage line 82₁~ 82₃= V_SS, V_FourVoltage line 8
Three₀~ 83₃= V_SSIt is said that As a result, the word line WL
₀= V_PP, Word line WL₁~ WL₃= V_SSIt is said that

On the other hand, when this row decoder is not selected, as shown in FIG. 34, the output of the NAND circuit 68 is "H" and the pMOS transistor T _p 17
= OFF, nMOS transistor T _n 17 = ON, pM
The OS transistor T _p 16 = ON, the nMOS transistor T _n 16 = OFF, the output terminal 66 = V _SS , and the output terminal 67 = V _PP .

As a result, the nMOS transistor T _n 21
_{0 to} T _n 21 ₃ = OFF, pMOS transistor T _p 2
_{1 0 ~T p 21 3 = ON} , pMOS transistor T _p 2
0 _{0 to} T _p 20 ₃ = OFF, nMOS transistor T _n
20 _{0 to} T _n 20 ₃ = ON. So, for example, V
₃ voltage line 82 ₀ = V _PP , V ₃ voltage line 82 _{1 to} 82 ₃ = V
_{Even if the SS} and V ₄ voltage lines 83 _{0 to} 83 ₃ = V _SS are set, the word lines WL _{0 to} WL ₃ = V _SS are set.

At the time of erasing, as shown in FIG.
Potential V _IH = V _CC , potential V _IN = V _BB , control signal LP =
With V _SS and control signal LN = V _BB , pMOS transistor T
_p 15 = ON, nMOS transistor T _n 15 = OFF
It is said that If this row decoder is selected here,
When the output of the NAND circuit 68 = “L”, the pMOS transistor T _p 16 = ON and the nMOS transistor T _n 16 =
OFF, pMOS transistor T _p 17 = OFF, nM
The OS transistor T _n 17 = ON and the output terminal 66
Potential = V _BB , and the potential of the output terminal 67 = V _CC .

As a result, the nMOS transistor T _n 21
_{0 to} T _n 21 ₃ = OFF, pMOS transistor T _p 2
_{1 0 ~T p 21 3 = ON} , pMOS transistor T _p 2
0 _{0 to} T _p 20 ₃ = OFF, nMOS transistor T _n
20 _{0 to} T _n 20 ₃ = ON. Here, for example, when the word line WL ₀ is selected, the V ₃ voltage line 82 ₀ is selected.
˜82 ₃ = V _CC , V ₄ voltage line 83 ₀ = V _BB , V ₄ voltage line 83 _{1 to} 83 ₃ = V _CC , word line WL ₀ = V _BB ,
Word lines WL _{1 to} WL ₃ = V _CC .

On the other hand, when this row decoder is not selected, as shown in FIG. 36, the output of NAND circuit 68 is "H", and pMOS transistor T _p 17
= ON, nMOS transistor T _n 17 = OFF, pM
The OS transistor T _p 16 = OFF, the nMOS transistor T _n 16 = ON, the output terminal 66 = V _CC , and the output terminal 67 = V _BB .

As a result, the nMOS transistor T _n 21
_{0 to} T _n 21 ₃ = ON, pMOS transistor T _p 21
_{0 to} T _p 21 ₃ = OFF, pMOS transistor T _p 2
0 _{0 to} T _p 20 ₃ = ON, nMOS transistor T _n 2
0 _{0 to} T _n 20 ₃ = OFF. So, for example,
V ₃ voltage line 82 _{0 to} 82 ₃ = V _CC , V ₄ voltage line 83 ₀ =
Even when V _BB and V ₄ voltage lines 83 _{1 to} 83 ₃ = V _CC are set, word lines WL _{0 to} WL ₃ = V _CC are set.

Also in this row decoder, the word line W
L₀~ WL₃With respect to the positive voltage V_CC,Contact
Ground voltage V_SS, High voltage V_PPOr negative voltage V_BBTo supply
You can The potential V_IH= V_CCOr V_PP, Potential V_IN=
V_SSOr V_BB, Control signal LP = V _IH, Control signal LN = V
_INIn case of, the pMOS transistor T_p15 = O
FF, nMOS transistor T_n15 = OFF,
You can latch the current state.

Further, the pMOS transistor T _p 15 = O
FF, nMOS transistor T _n 15 = OFF,
After latching the current state, the potential V _IH or the potential V _IN can be changed to change the voltage supplied to the word line WL. When all row decoders are selected and all V ₃ voltage lines are set to V _CC , V _CC can be supplied to all word lines and all cells can be read.
When all row decoders are selected and all V ₃ voltage lines are set to V _PP , all word lines can be supplied with V _PP and all cells can be written. When all the V ₄ voltage lines are set to V _BB in this state, V _BB can be supplied to all word lines to put all cells in the erased state.

Further, after all row decoders are selected and all V ₃ voltage lines are set to V _CC and V _CC is supplied to all word lines, the level conversion circuit 84 is set to the latch mode, and thereafter,
When all V ₃ voltage lines are set to V _PP , all word lines are V _PP
Can be supplied to put all the cells in the written state. In addition, all row decoders are set to the selected state and all V ₃ voltage lines are set to V
After feeding V _CC to all the word lines as _CC, and the level converting circuit 80 to the latch mode, then all V ₄ voltage line V
_In the case of _BB , V _BB can be supplied to all word lines to put all cells in the erased state.

According to the seventh embodiment flash memory,
The level conversion circuit 80 of the main row decoder 78 includes three pMOS transistors T _p 15, T _p 16, T _p 17
And three nMOS transistors T _n 15, T _n 16,
Since it is composed of T _n 17, the area occupied by the row decoder can be reduced and the chip area can be reduced in the flash memory configured by providing the row decoder with the main row decoder and the sub row decoder.

Next, a flash memory in which the number of transistors forming the sub row decoder of the seventh embodiment is reduced is shown in the eighth embodiment. FIG. 37 is a circuit diagram showing the main part of the flash memory of the eighth embodiment, showing one row decoder. The parts corresponding to those in FIGS. 12, 21, and 30 are designated by the same reference numerals.

In the figure, reference numeral 84 is a sub row decoder. In this sub row decoder 84, the nMOS transistor T provided in the sub row decoder 79 shown in FIG.
_p 21 ₀ ~T _p 21 ₃ has been removed, for the other, have the same structure as the sub-row decoder 79 shown in FIG. 30. Also in this row decoder, the word line W
For L _{0 to} WL ₃ , the power supply voltage V _CC , if necessary,
The zero voltage V _SS , the high voltage V _PP or the negative voltage V _BB can be supplied, and the latch operation and the all cell selection operation can be performed similarly to the row decoder shown in FIG.

According to the flash memory of this embodiment,
The level conversion circuit 80 of the main row decoder 78 includes three pMOS transistors T _p 15, T _p 16, T _p 17
And three nMOS transistors T _n 15, T _n 16,
T _n 17, and the sub-row decoder 8
Since the number of transistors of 4 is smaller than that of the sub-row decoder 79 shown in FIG. 30,
FIG. 30 shows a flash memory including a row decoder provided with a main row decoder and a sub row decoder.
The area occupied by the row decoder can be reduced and the chip area can be reduced as compared with the case shown in FIG.

FIG. 38 is a circuit diagram showing an essential part of the flash memory of the ninth embodiment, showing one row decoder. The parts corresponding to those in FIGS. 12, 21, and 30 are designated by the same reference numerals. In the figure, reference numeral 85 is a main row decoder, T _n 22 is an nMOS transistor forming a transfer gate, 86 is a capacitor formed of an nMOS transistor, and 87 is an inverter.

In the inverter 87, 88 is V
_CC power supply line, T _p 23 is a pMOS transistor, T _n 23
Is an nMOS transistor, and 89 is a control signal input terminal to which a control signal SB whose level is lowered from “H” to “L” is input at the time of reading. Reference numeral 91 is a sub row decoder. In this sub row decoder 91, the pMOS provided by the sub row decoder 79 shown in FIG. 30 is provided.
Transistor _{T p 20 0 ~T p 20 3} , T p 21 0 ~T
_p 21 ₃ has been deleted. Others are shown in FIG.
The sub row decoder 79 shown in FIG.

In this example, the gate of the nMOS transistor T _n 22 is connected to the _VIH power supply line 64, and the output terminal 66 of the level conversion circuit 80 is connected to the nMOS transistor T _n 22 via the nMOS transistor T _n 22.
Is connected to the 21 ₀ ~T _n 21 _3, the output terminal 90 of the inverter 87 is connected to the gate of the nMOS transistor T _n 21 ₀ ~T _n 21 ₃ via a capacitor 86.

In this row decoder, at the time of reading,
From the level conversion circuit 80 to the nMOS transistor T_n21
₀~ T_n21₃V for the gate of_CCIs supplied,
In this case, the control signal SB falls from "H" to "L".
Therefore, the potential of the output terminal 90 of the inverter 96 is
Launched from "L" to "H". As a result, the node
The potential of 93 is due to the coupling action of the capacitor 86.
R V _CCAbove, for example, V_CC+ V_thIs boosted to this boost
The generated voltage is nMOS transistor T_n21₀~ T_nTwo
1₃Is supplied to the gate. In this case, nMOS
Transistor T_n22 is in the OFF state, so the node
A current flows from the 93 side to the level conversion circuit 80 side.
There is no such thing.

Therefore, in this row decoder, at the time of reading, the potential of the selected word line is V _CC -V _th (nM
The threshold voltage of the OS transistor) can be set to V _CC, and the potential of the selected word line can be set to V _PP instead of V _PP -V _th even during writing. it can. This row decoder basically operates in the same manner as the row decoder shown in FIG. 30 except for the operation at this point, and the word lines WL _{0 to} WL ₃ are supplied with the power supply voltage V _CC , if necessary. The ground voltage V _SS , the high voltage V _PP or the negative voltage V _BB can be supplied, and the latch operation and all-cell selection operation can be performed similarly to the row decoder shown in FIG.

According to the flash memory of the ninth embodiment, the level conversion circuit 80 of the main row decoder 85 is
Three pMOS transistors T _p 15, T _p 16, T _p
17 and three nMOS transistors T _n 15 and T _n 1
6 and T _n 17, the area occupied by the row decoder can be reduced and the chip area can be reduced in a flash memory having a row decoder provided with a main row decoder and a sub row decoder. it can.

As described above, since the level conversion circuits of the fourth to ninth embodiments can be composed of two connection switch elements and two inverters, this can be applied to, for example, level conversion. When used in a flash memory that requires a circuit, the chip area can be reduced. If such a level conversion circuit is used for a row decoder of a flash memory, the area occupied by the row decoder can be reduced and the chip area can be reduced.

However, the fourth to ninth embodiments shown in FIG.
The level conversion circuit used in the embodiment has a problem that the through current is large and the balance setting of the transistors is difficult due to the same cause as the level conversion circuit of FIG. The tenth and eleventh embodiments are level conversion circuits which solve these problems. FIG. 39 is a diagram showing a level conversion circuit of the tenth embodiment. As is clear from the figure,
The circuit of FIG. 39 corresponds to the first level conversion circuit of the level conversion circuit of FIG.
P-channel transistor T _p 1 forming an inverter
6 and the n-channel transistor T _n 16 are provided with a first depletion type transistor T18, and the second depletion type transistor T19 is provided between the p-channel transistor T _p 17 and the n-channel transistor T _n 17 which form the second inverter. It is a thing. The input signal is input to both ends of the first depletion type transistor T18 via two n-channel transistors T _n 20 and T _n 21 whose sources are connected to the input terminal and whose gates are connected to the control terminal LN. And two p-channel transistors T _p whose sources are connected to the input terminal and whose gates are connected to the control terminal LP.
It is input to both ends of the second depletion type transistor T19 via 22 and T _p 22.

This depletion type transistor T18
And T19 are similar to those of the depletion transistor T8 of the level conversion circuit of the second embodiment shown in FIG. 9, and other than that are similar to those of the circuit of FIG.
Although a detailed description of the circuit of FIG. 39 is omitted, Table 6 is a truth table of the circuit of FIG.

[0134]

[Table 6]

FIG. 40 shows the level conversion circuit of the eleventh embodiment.
Yes, in the level conversion circuit of FIG. 12, p channel
Transistor T_pAdd 17 sources p channel tiger
Register T_pConnected to the control terminal 63 via 24 and added
p-channel transistor T _pInput terminal of 24 gates
It corresponds to the one connected to 53. This additional p channel
Transistor T_p24 is the p channel of the second inverter
Lutransistor T_p17 is the change of the voltage applied to the gate
When the state changes from conducting to non-conducting in response to
P-channel transition in response to changes in input signal
Star T_pDisconnect the 17 sauce. This makes the second inn
A through current flows through the burner and the potential at point n24 becomes an intermediate potential.
To ensure that the circuit operates more reliably.
It The truth table of the circuit of FIG. 40 is the same as that of the circuit of FIG.
Is.

So far, the embodiments in which the negative voltage is applied to the word line in the flash memory at the time of erasing in the flash memory through the row decoder and the embodiments of the level conversion circuit therefor have been described. When a negative voltage is applied by the row decoder, as described above (see FIGS. 1 and 3), in order to prevent a forward bias current between the diffusion layer and the substrate or well,
The driver substrate or well is biased to a negative potential. However, since no negative potential is used during writing and reading, the substrate or well is set to the power supply potential V _SS .

As a substrate (well) potential control circuit as described above, a circuit as shown in FIG. 41 has been conventionally used. In the circuit of FIG. 41, V _BS is the substrate (well) voltage line, and the substrate (well) voltage line V _BS is between the negative voltage V _BB output from the negative voltage source 100 and the zero (ground) voltage V _SS.
A p-channel depletion type transistor T _p 25 is used to switch the voltage applied to. The gate voltage of the transistor T _p 25 is set to the normal power supply potential V _SS and V
By switching between _CC , the voltage applied to the substrate voltage line V _BS is switched. Zero voltage V on the board power line V _{BS
When SS} is output, the negative voltage source 100 is inactive and does not output the negative voltage V _BB .

In the circuit of FIG. 41, a p-channel depletion type transistor T _p 25 is used for switching the power source, and the threshold voltage V _th of this transistor T _p 25 is set to zero potential V _SS and positive potential V _CC . If the control signal G is "H (V _CC )", the transistor T _p 25
Is turned off, and if it is "L (V _SS )", the transistor T _p 25 is turned on. Table 7 shows a truth table of the circuit shown in FIG.

[0139]

[Table 7]

The substrate (well) potential control circuit shown in FIG. 41 has the advantage of a simple structure, but has the following problems. (1) A separate process is required to manufacture the p-channel depletion, which complicates the process. (2) It is necessary to accurately control the threshold voltage V _th of the p-channel depletion transistor, which makes process control difficult.

(3) Since the p-channel transistor has a larger area than the n-channel transistor, the circuit becomes large. (4) When the negative voltage V _BB is applied to the substrate (well) power supply line V _BS , the positive voltage V _CC is applied to the gate of the transistor T _p 25. Therefore, since the difference between the positive potential V _CC and the negative potential V _BB is applied between the gate and drain, the applied voltage becomes large. Therefore, it is necessary to increase the breakdown voltage between the gate and the drain, and to increase the breakdown voltage, it is necessary to increase the thickness of the gate distribution film, but this causes a problem of increasing the area.

Therefore, a circuit as shown in FIG. 42 has been conventionally used as a substrate (well) potential control circuit which does not use a p-channel depletion type transistor. Figure 4
Table 8 shows a truth table of the second circuit.

[0143]

[Table 8]

In the circuit of FIG. 42, since only enhancement type transistors are used, the number of steps is not increased, but when the substrate (well) power supply line V _{BS is set} to the zero potential V _SS , the point n4 is set.
It is necessary to keep the potential of 1 at a negative voltage, and for that purpose, the negative voltage source 100 must always output a negative voltage.
Therefore, the negative voltage source 100 needs to be always in an operating state, and there is a problem that power consumption increases. Further, among the above problems, the problem (3) of a large circuit and the problem (4) of requiring a large breakdown voltage are the same and cannot be solved.

As described above, the conventional substrate (well) potential control circuit has the problems that the chip area is large, the power consumption during standby is large, and the manufacturing process is complicated. Is requested. Figure 43
FIG. 3 is a principle configuration diagram of a substrate (well) potential control circuit of the present invention which solves the above problems.

As shown in FIG. 43, the substrate (well) potential control circuit of the present invention includes a negative voltage source 100 for outputting a negative voltage to a power supply line V _BS connected to a potential control target portion, a substrate or a well. The source is connected to the negative power supply line V _BS , the drain is connected to the power supply that outputs the zero potential V _SS, and the first n-channel transistor T _n 30 is connected to the negative power supply line V _BS. is connected to, the second n-channel transistor T _n 29 having a drain connected to the gate of the first n-channel transistor T _n 30, the first n-channel transistor T gate of _n 30 and a positive voltage V The first switch SW1 provided between the power supply for outputting _CC and the second n-channel transistor T _n 2
A second switch SW2 capable of selecting whether to connect the gate of 9 to a power source that outputs a positive potential V _CC or a power source that outputs a zero potential V _SS, and to open the second n-channel transistor. A capacitor C connected between the gate and the source of T _n 29 is provided, and when the negative voltage is not applied, the negative voltage source 100 is brought into a non-output state and the first switch S
When W1 is connected, the second switch SW2 is connected to the zero potential side, and a negative voltage is applied, first the first switch SW1 is opened and at the same time the second switch SW is opened.
2 is connected to the positive potential side, and then the second switch SW2
Is opened and the negative voltage source 100 is brought into an output state.

[0147]

[Table 9]

Table 9 is a truth table of FIG. Above
By performing such control, the negative voltage application time n51
The voltage is a transistor due to the charge accumulated in the capacitance means C.
T_nV for 29 substrates (wells)_CCHeld in
Therefore, a transistor can be used without applying a large voltage difference.
T_n29 is maintained in the ON state, and the switching transistor T _n
30 is turned off. Zero voltage V_SSWhen applying,
Dista T_n29 is turned off, and the transistor T_nThree
0 is turned on and the substrate (well) power supply line is connected to zero potential V
_SSTo

Since the circuit of FIG. 43 can be constructed only with enhancement type transistors, it is small in size and has no problem of breakdown voltage. FIG. 44 is a diagram showing the circuit configuration of the twelfth embodiment embodied in accordance with the principle configuration diagram of FIG. FIG. 45 and Table 1
Reference numeral 0 denotes a voltage change of each part and a truth table showing the operation of the circuit of FIG. 45, and the state change of the truth table corresponds to the time axis of the graph.

[0150]

[Table 10]

In the circuit of FIG. 44, the first switch S
W1 is a p-channel transistor T _p31 source voltage
It is realized by switching the second switch SW2
Open / close operation and disconnection of voltage to the terminal of the second switch SW2
Positive power supply V for switching operation_CCAnd zero voltage source V_SSBetween
P-channel transistor T connected in series to_p32
And n-channel transistor T_n32 are provided. To
Langista T_p32 and T_n32 gates are control terminals
Becomes positive potential V_CCAnd zero potential V_SSThe amplitude signals G1 and G2 of
Controlled. 100 is a negative voltage generating circuit,
Input a complementary clock signal to 1φ
Occur. Transistor T_n30 is a power line V_BSThe drive
Therefore, the driving ability is increased.

The operation of the circuit of FIG. 44 is shown in FIG. 45 and Table 10.
Therefore, it will be described. In the first period, G1 and G2 go to "H"
Is set, G3 is set to "L", and V is applied to the terminal S3._CC
Is being applied. And the negative voltage generation circuit 100 operates
Have stopped. To apply a negative voltage from this state
Changes G1 and G2 to “L” in the second period.
The potential signal S3 applied to the terminal 102 to V_SSChanged to
Let As a result, the potential at the point n51 is "H" level, that is,
Wachi V_CCRises to transistor T_n29 is on
Become. Transistor T_p31, the signal S3 is V_SSChanged to
It turns off. This causes the potential at point n52
"L", that is, V_SSBecomes transistor T _n30 is o
I will be in a bad state.

In the third period, G1 changes to "H" level
Then, the operation of the negative voltage generation circuit 100 is started. to this
Therefore, the point n51 is separated. And the fourth and
And power line V in the 5th period_BSVoltage is V_BBStart descent towards
Therefore, the potential at the point n51 is also the power line V_BSAnd capacitor C
It descends because it is connected. But the transistor T _n
The gate-source voltage of 29 is maintained by the capacitor C.
Since it is held, the transistor T_n29 is on
Therefore, the potential at the point n52 also drops and the transistor T_n30 is
It remains off.

Here, the potential of the point n51 drops in accordance with the potential drop of the power supply line V _BS while maintaining the state higher than the power supply line V _BS by the voltage determined by the charges accumulated in the capacitor C. However, when the potential at the point n51 becomes slightly negative with respect to V _{SS and} reaches the threshold voltage of the transistor T _n 32, it does not drop any further. The sixth period corresponds to the application of the negative pressure, and at this time, G2 is set to the "H" level.

When the application of the negative voltage is completed, the operation of the negative voltage generating circuit 100 is stopped and the potential signal S3 applied to the terminal 102 is changed to V _CC . Then the transistor T _p 31
Is turned on, and the potential at the point n52 starts rising. In response to this, the potential of the power supply line V _BS also starts to rise. Since the potential at the time point n51 is V _SS , the transistor T _n 29 is in the off state. Then, since the potential at the point 52 rises, the transistor T _n 30 is turned on and the power supply line V _BS becomes V _SS.
Connected to.

FIG. 46 is a diagram showing the configuration of the substrate (well) potential control circuit of the thirteenth embodiment. The source of the transistor T _p 31 is fixed to the power supply for outputting the positive potential V _{CC in comparison} with the circuit of FIG. And the point that the gate potential of the transistor T _p 31 is controlled, and the other points are the same. The operation is different from the circuit of FIG. 44 in that the transistor T
Instead of switching the voltage applied to the source of _p 31 to V _SS , the transistor T _p 31 is turned off.
Except for this point, the operation is similar to that of the circuit of FIG. Table 11 shows a truth table showing the operation of the circuit of FIG.

[0157]

[Table 11]

When realizing the circuit of FIG. 44, it is necessary to use the triple well structure as shown in FIG. 47 (1) in order to prevent the generation of forward bias current between the substrate or well and the diffusion layer. In the case of the circuit of FIG. 46,
An n-substrate P-well structure such as (2) can be used. In the twelfth and thirteenth embodiments described above, by using a capacitor as shown in the principle configuration diagram shown in FIG. 43, the gate-source voltage of the transistor T _n 29 is prevented from exceeding a predetermined value (V _CC ). Was there. This eliminates the need to increase the breakdown voltage between the gate and the source. However, it is possible to obtain the same effect by controlling the potential of the gate without using a capacitor, and an example thereof is shown in the 14th embodiment.

FIG. 48 is a diagram showing the structure of the substrate (well) potential control circuit of the fourteenth embodiment, and FIG. 49 shows the control signal and potential change of the power supply line V _BS . The circuit of FIG. 48 has substantially the same configuration as the circuit of FIG. 43 as shown, but the capacitance means C is omitted. 102 and 106 are control terminals, which are signals A and B whose logical levels are V _SS and V _CC.
Is applied. The operation of the circuit of FIG. 48 will be described according to the graph of FIG.

As shown in FIG. 49, when V _{SS is} applied, the signal A is set to V _CC and the signal B is set to V _SS . Thus the on-state p-channel transistor T _p 31, the n-channel transistor T _n 29 is turned off, the gate potential of the transistor T _n 30 becomes V _CC, transistor T _n 30 is turned on, the power supply V _SS is output to the line V _BS .

When V _{BB is} applied, the potential of the signal A is switched to V _SS and the potential of the signal B is switched to V _CC . As a result, the transistors T _p 31 and T _n 30 are turned off, and the transistor T _n 29 is turned on. Then, when the negative voltage generating circuit is operated, the potential of the power supply line V _BS gradually drops. Then, when the voltage drops below the threshold voltage of the transistor T4, the signal B is changed to V _SS . Still, the transistor T _n 29 remains on, and the potential of the power supply line V _BS drops as it is. As a result, the power line V
_{Even if} the potential of _BS drops to V _BB , the voltage applied between the gate and the source of the transistor T _n 29 is V _SS -V _BB , that is, -V _B , which can be made smaller than in the conventional example.

As described above, when the substrate (well) potential control circuit shown in the twelfth to fourteenth embodiments is used, the depletion type transistor is not used, and therefore the number of steps is not increased, and the n-channel transistor is used. Therefore, there is an effect that the occupied area is small and the breakdown voltage can be improved, and the yield, the reliability, and the cost can be reduced by downsizing the device and simplifying the process.

As described above, in the flash memory,
It has already been mentioned that when the charge accumulated in the floating gate is erased, the voltage applied between the control gate and the channel or source has a great influence on the erase time. Here, the erasing method in the flash memory will be briefly described.

As methods of erasing the flash memory, there are a channel erasing method in which charges of the floating gate are released to the channel and a source erasing method in which charges are released to the source. A method of applying 0V to the control gate and applying a positive voltage to the channel or source to apply a high voltage V _P , and a negative voltage to apply a negative voltage to the control gate and applying a positive voltage V _CC to the channel or source There is an application method. The negative voltage application method does not require a high voltage from the outside, and is therefore suitable for lowering the voltage of the flash memory and achieving a single power supply.

50 to 53 are diagrams showing a voltage application state in a memory cell when each of the above erasing methods is used. All memory cells are n-channel transistors as an example. FIG. 50 shows a case where the channel erasing method by applying a positive voltage is used. The drain D and the source S are opened to set the control gate CG to 0 V and the P well corresponding to the channel is set to the high potential V _PP . In the case of channel erasing, it has a triple well structure as shown in order to apply a positive bias to the channel.

FIG. 51 shows a source erasing method by applying a positive voltage.
Shows the case of using, and after opening the drain D
Control gate CG to 0V and source S to high voltage.
Rank V _PPTo The substrate is either open or brought to 0V. Figure
52 uses a channel erasing method by applying a negative voltage
In this case, the drain D and the source S are opened and
The control gate CG has a negative potential V_BBTo the channel
Positive potential V is applied to the corresponding P well_CCIs applied. Therefore
V between the Trollgate CG and the channel_BB-V_CCMark
Be added.

FIG. 53 shows the case of using the source erasing method by applying a negative voltage. The drain D is opened, the control gate CG is set to the negative potential V _BB , and the source S is set.
To a positive potential V _CC . The above is the erasing method of the flash memory, but in any case, the voltage applied between the control gate CG and the channel or the source S greatly affects the erasing operation. Therefore, in order to always perform a stable erase operation, it is important to keep the voltage applied between the control gate and the channel or the source constant regardless of the fluctuation of the external power supply. In particular, a storage device of a portable device is currently considered as an application field of a flash memory, and a battery is used as a power source in such a portable device, so that a voltage fluctuation of an external power source cannot be avoided. . Therefore, there is a demand for a flash memory erasing method that can perform stable erasing regardless of fluctuations in the external power supply, and a flash memory that is erased by such an erasing method. The following embodiments are intended to meet such a demand.

FIG. 54 is a diagram showing the structure of the fifteenth embodiment. One memory cell, a row decoder for applying an access signal to the word line connected to the control gate CG of the memory cell, and a negative voltage. 2 shows a circuit for applying a voltage. In the figure, 110 is a negative voltage charge pump circuit, 111 is a negative voltage bias circuit, 112 is a decoder circuit, TC is a cell transistor, and 113 and 114 are n-channel enhancement field effect transistors TN1 to TNn and tn1 to tnm, respectively. MOS
A diode string, n60 and n61 are nodes, WL is a word line, D is a drain, S is a source, BG is a well contact, CG is a control gate, FG is a floating gate, CLK is a clock signal, ES is an erase selection signal, and V _{PP is} Is an external power supply voltage, and V _SS is a zero (ground) potential.

At the time of reading, the erase selection signal ES is set to "L",
The clock signal CLK is fixed at "H". At this time, the decoder circuit 112 outputs "H" when selected and "L" when not selected. When the word line WL is "L", the NOR gate is ready to receive the clock signal CLK, but since the clock signal CLK is fixed to "H", the negative voltage bias circuit 111 does not operate and the word line WL The negative voltage V _BB generated by the negative voltage charge pump 110 is not applied to WL.

At the time of erasing, the erase selection signal ES is set to "H" and the clock signal CLK is input. At this time, the decoder circuit 112 outputs "L" when selected and "H" when not selected. When the word line WL is “L”, the NOR gate is in a state of receiving the clock signal CLK, the negative voltage bias circuit 111 operates and the negative voltage charge pump circuit 110.
Negative voltage V _BB is applied to the word line WL of the occurrence. At this time, the drain D and the source S of the memory cell TC are opened, and the voltage V _PP is applied to the well contact BG.
As a result, if the memory cell TC is written, electrons are released from the floating gate FG to the channel due to the tunnel effect, and erase is performed.

Nodes n60 and n61 are clamped to a predetermined voltage by the MOS diode array formed by the transistor arrays 113 and 114. As described above, in this embodiment, the application of the high voltage V _PP and the positive voltage V _CC to the selected word line WL and the application of the zero voltage V _SS to the non-selected word line during writing and reading are performed. This is performed by the row decoder 112. The negative voltage is applied by the negative voltage charge pump circuit 110, but the row decoder 112 controls to apply the negative voltage only to the selected word line. The row decoder 112 is
Since a logic-inverted output is performed at the time of writing / reading and at the time of erasing, a logic inversion function is provided.

The negative voltage charge pump 110 generates and outputs a negative voltage at all times or when a negative voltage is applied.
The output voltage is regulated to a predetermined value by the transistor string connected between the output voltage and the high voltage source V _PP . The negative voltage bias circuit 111 is described in Japanese Patent Application No. 4-256594, and a detailed description thereof will be omitted here.
By inputting LK, the voltage output from the negative voltage charge pump 110 is output to the word line.

Here, consider the case where V _PP becomes aV lower. With the MOS diode formed by TN1 to n,
The potential difference between V _PP and n60 is always kept at V _PP -V _BB . When V _PP becomes aV lower, the voltage of n60 becomes V _BB -a. Therefore, the voltage between the control gate CG of the memory cell TC and the channel is kept at V _PP -V _BB .

Next, consider the case where V _PP is increased by aV. When V _PP increases by aV, the voltage of n60 becomes V _BB + a. Therefore, the voltage between the control gate CG of the memory cell TC and the channel is kept at V _PP -V _BB .

As described above, even if the external voltage V _PP changes, the voltage between the control gate CG and the channel is always kept constant, and stable erase characteristics can be obtained. In the fifteenth embodiment described above, the output voltage of the negative voltage charge pump 110 is regulated to a predetermined value with respect to the high voltage source V _PP applied to the P well by the transistor array,
A constant voltage can be applied. On the other hand, in the following sixteenth embodiment, both the negative voltage V _BB applied to the control gate CG and the positive voltage V _CC applied to the P well are regulated to the ground (zero) potential V _SS , so that the negative voltage is reduced. And keep the positive voltage difference constant.

FIG. 55 is a diagram showing the structure of the sixteenth embodiment. The difference from the circuit of FIG. 54 is that the output of the inverter that generates the voltage applied to the P well is the transistor row tn.
It is regulated by n to tnz and is always constant with respect to the zero (ground) potential V _SS , and the output of the negative voltage charge pump 110 is constant with respect to the ground potential V _SS by the transistors TN1 to TNn. The point is regulated by.

Here, consider the case where V _PP changes. TN
1 to n and tn1 to m form a MOS diode array, n60 and V _SS , well contacts BG and V
The voltage between _SS is kept constant. Since V _SS is zero (ground) potential is not affected by changes in V _PP, regardless of changes in V _PP, constant voltage is always supplied to the control gate CG and the well contact BG, the control gate CG And the voltage between the channels is always kept constant.

As described above, even if the external voltage V _PP changes, the voltage between the control gate CG and the channel is always kept constant, and a stable erase characteristic can be obtained. FIG. 56 is a diagram showing still another seventeenth embodiment of the channel erasing method. In the figure,
110 is a negative voltage charge pump circuit, 111 is a negative voltage bias circuit, 112 is a decoder circuit, 116, 119,
120 is an inverter, TC is a cell transistor, 11
4,115,117,118 are Tn1 to Tnm, tnm
˜tnz, TN1 to TNp and TN1 to TNq, N-channel enhancement field effect transistor array, n60 to n64 are nodes, WL is word line, D is drain, S is source, BG is well contact, CL
K1 to 3 are clock signals, ES is an erase selection signal, / ES
Is an erase power supply switching signal, V _PP is an external power supply voltage, and V _SS is a ground potential.

Next, the operation of this circuit will be described. At the time of reading, the erase selection signal ES is set to "L" and the erase power supply switching signal / E
S is fixed to "H" and clock signals CLK1 to CLK3 are fixed to "H". At this time, the well contact BG is connected to the inverter 11
Biased to V _SS by 6. Decoder circuit 112
Outputs "H" when selected and "L" when not selected. W
When L is'L ', NOR becomes ready to accept the clock signal CLK1, but since the clock signal CLK1 is fixed at'H', the negative voltage bias circuit 111 does not operate, and the clock signal CLK2 and the clock signal CLK3.
Is also fixed at “H”, the negative voltage charge pump circuit 110 does not generate V _BB either, and a negative voltage is not applied to WL.

At the time of erasing, the erasing selection signal ES is set to "H" and the erasing power source switching signal / ES is set to "L". Clock CLK
A clock signal is input to 1 to 3. Clock signal CL
The clock signals input to K2 and the clock signal CLK3 have opposite phases. The decoder circuit 112 outputs "L" when selected and "H" when not selected. When WL is'L ', NOR becomes ready to receive the clock signal CLK1 and the negative voltage bias circuit 111 operates to apply V _BB generated in the negative voltage charge pump circuit 110 to WL. At this time, S and D of TC are open, and the well contact BG is applied with a high voltage by the inverter 116. As a result, if TC is written, electrons are released from the control gate CG to the channel by the tunnel effect, and erasing is performed.

N61 to 63 and the well contact BG are clamped to a certain voltage with V _SS as a reference voltage by a MOS diode formed of tn1 to tnm, tnn to tnz, TN1 to TNp and TN1 to TNq. Here, consider the case where V _PP changes. The value of the voltage V _BB generated by the negative voltage charge pump circuit 110 is determined by the amplitude of the signal input to the negative voltage charge pump circuit 110, the coupling ratio, and the threshold voltage of the transistor. It is the amplitude of the input signal. However, in this embodiment, the input terminals n63 and n64 of the negative voltage charge pump circuit 110 are clamped to a constant voltage with V _SS as the reference voltage, and are not affected by the change in V _PP . Therefore, the negative voltage charge pump circuit 1
The output voltage V _{BB of} 10 is always constant regardless of the change of V _PP . Similarly, the voltage applied to the well contact BG is also clamped with V _SS as a reference voltage, and V _PP
Therefore, the voltage between the control gate CG and the channel is always kept constant even if V _PP changes.

As described above, even if the external voltage V _PP changes, the voltage between the control gate CG and the channel is always kept constant, and stable erase characteristics can be obtained. The above is the embodiment in which stable erasing can be performed by fixing the voltage applied between the control gate and the channel in the channel erasing method, but the source erasing method is also stable by regulating the applied voltage in the same manner. You will be able to erase it.

57 to 59 are diagrams showing the eighteenth to twentieth embodiments for performing source erasing stably, and FIG.
5 to 57, the voltage applied to the P-well is applied to the source S in the channel erasing embodiment shown in FIG.

[0184]

As described above, in the flash memory of the present invention, the negative voltage for erasing can be applied by a simple row decoder, so that the circuit can be downsized and high integration can be achieved. In addition, reliability can be improved because stable erasing can be performed.

[Brief description of drawings]

FIG. 1 is an operation explanatory diagram of a first aspect of a flash memory of the present invention.

FIG. 2 is an explanatory diagram of a conventional problem, and FIG.
In the case of -sub and Nwell, Fig. 10 (2) shows N-su.
b, Pwell.

FIG. 3 is a structural diagram of a driving unit of the present invention.

FIG. 4 is a configuration diagram of a semiconductor memory device according to a first exemplary embodiment of the present invention.

FIG. 5 (1) is a circuit diagram of a decoding unit of the first embodiment,
(2) is a circuit diagram of the drive unit of the first embodiment.

FIG. 6A is a circuit diagram of a circuit example of another decoding unit of the first embodiment, and FIG. 6B is a circuit diagram of a circuit example of another driving unit.

FIG. 7 is a circuit diagram of a level conversion circuit of the first embodiment.

FIG. 8 is a configuration diagram of a drive unit power supply switching circuit of the first embodiment.

FIG. 9 is a diagram of a level conversion circuit according to a second embodiment.

FIG. 10 is a diagram of a level conversion circuit according to a third embodiment.

FIG. 11 is a diagram illustrating the principle of the level conversion circuit according to the fourth embodiment.

FIG. 12 is a specific circuit diagram of a level conversion circuit according to a fourth embodiment.

13 is a circuit diagram showing an operation (non-conversion mode) of the level conversion circuit of FIG.

14 is a circuit diagram showing an operation (non-conversion mode) of the level conversion circuit of FIG.

15 is a circuit diagram showing an operation (inversion mode) of the level conversion circuit of FIG.

16 is a circuit diagram showing an operation (inversion mode) of the level conversion circuit of FIG.

17 is a circuit diagram showing an operation (high voltage conversion mode) of the level conversion circuit of FIG.

18 is a circuit diagram showing an operation (high voltage conversion mode) of the level conversion circuit of FIG.

19 is a circuit diagram showing an operation (negative voltage conversion mode) of the level conversion circuit of FIG.

20 is a circuit diagram showing an operation (negative voltage conversion mode) of the level conversion circuit of FIG.

21 is a circuit diagram showing a configuration when the level conversion circuit of FIG. 12 is used for a row decoder of a flash memory.

22 is a circuit diagram showing an operation of the row decoder shown in FIG. 21 (when read, selected).

FIG. 23 is a circuit diagram showing an operation of the row decoder shown in FIG. 21 (when unselected at the time of reading).

FIG. 24 is a circuit diagram showing an operation of the row decoder shown in FIG. 21 (in writing, when selected).

FIG. 25 is a circuit diagram showing an operation of the row decoder shown in FIG. 21 (when unselected at the time of writing).

FIG. 26 shows an operation of the row decoder shown in FIG.
It is a circuit diagram showing (when selected).

FIG. 27 is an operation of the row decoder shown in FIG.
FIG. 6 is a circuit diagram showing a case (non-selected).

FIG. 28 is a circuit diagram showing a main part (row decoder) of a flash memory according to a fifth embodiment.

FIG. 29 is a circuit diagram showing a main part (row decoder) of a flash memory according to a sixth embodiment.

FIG. 30 is a circuit diagram showing a main part (row decoder) of a flash memory according to a seventh embodiment.

31 is a circuit diagram showing an operation of the row decoder shown in FIG. 30 (when selected at the time of reading).

32 is a circuit diagram showing an operation of the row decoder shown in FIG. 30 (in the case of being unselected at the time of reading).

FIG. 33 is a circuit diagram showing an operation of the row decoder shown in FIG. 30 (when selected during writing).

FIG. 34 is a circuit diagram showing an operation of the row decoder shown in FIG. 30 (when unselected at the time of writing).

FIG. 35 is an operation of the row decoder shown in FIG.
It is a circuit diagram showing (when selected).

FIG. 36 is an operation of the row decoder shown in FIG.
FIG. 6 is a circuit diagram showing a case (non-selected).

FIG. 37 is a circuit diagram showing an essential part (row decoder) of an eighth embodiment flash memory.

FIG. 38 is a circuit diagram showing a main part (row decoder) of a ninth embodiment flash memory.

FIG. 39 is a diagram of the level conversion circuit of the tenth embodiment.

FIG. 40 is a diagram of the level conversion circuit of the eleventh embodiment.

FIG. 41 is a diagram showing an example of a conventional substrate (well) potential control circuit.

FIG. 42 is a diagram showing another example of a conventional substrate (well) potential control circuit.

FIG. 43 is a principle configurational diagram of a substrate (well) potential control circuit of the present invention.

FIG. 44 is a diagram showing a substrate (well) potential control circuit of the twelfth embodiment.

45 is a time chart showing the operation of the circuit of FIG. 44.

FIG. 46 is a diagram showing a substrate (well) potential control circuit of the thirteenth embodiment.

FIG. 47 is a diagram showing a structural example of a substrate (well) potential control circuit of the present invention.

FIG. 48 is a diagram showing a substrate (well) potential control circuit of the fourteenth embodiment.

49 is a time chart showing control and operation of the circuit of FIG. 48.

FIG. 50 is an explanatory diagram of channel erasing by applying a high voltage.

FIG. 51 is an explanatory diagram of source erase by applying a high voltage.

FIG. 52 is an explanatory diagram of channel erasing by applying a negative voltage.

FIG. 53 is an explanatory diagram of source erase by applying a negative voltage.

FIG. 54 is a diagram showing a circuit configuration of a fifteenth embodiment.

FIG. 55 is a diagram showing a circuit configuration of a sixteenth embodiment.

FIG. 56 is a diagram showing a circuit configuration of a seventeenth embodiment.

FIG. 57 is a diagram showing a circuit configuration of an eighteenth embodiment.

FIG. 58 is a diagram showing a circuit configuration of a nineteenth embodiment.

FIG. 59 is a diagram showing a circuit configuration of a twentieth embodiment.

FIG. 60 is a configuration diagram of a conventional flash memory.

FIG. 61 is a structural diagram of a memory cell.

FIG. 62 is an explanatory diagram of a read / write / erase method of the flash memory.

FIG. 63 is a diagram showing an example in which a negative voltage applying circuit is separately provided.

FIG. 64 is a functional configuration diagram of a row decoder for applying a negative voltage.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory cell array 3 ... Row decoder 4 ... Decoding part 5 ... Drive part 6 ... 1st power supply terminal 7 ... 2nd power supply terminal 9 ... Level conversion circuit 11 ... Drive part power supply switching circuit 13 ... High voltage supply part 14 ... Negative voltage supply unit 15 ... Power supply control circuit 17 ... Address buffer predecoder

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] January 10, 1994

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI Technical indication location H01L 29/792 H01L 29/78 371 (72) Inventor Shoichi Kawamura 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Incorporated (72) Inventor Takao Akagi, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (29)

[Claims] 1. A memory cell array (1) in which a plurality of electrically erasable non-volatile memory cells are arranged, and a decoding unit (4) for decoding a plurality of signals to access the memory cell array (1). A flash memory comprising: a first power supply terminal (6) and a second power supply terminal (7), wherein the output of the decoding unit (4) is input to the first power supply terminal (6).
A drive unit (6) for selectively outputting the voltage applied to the power supply terminal (6) or a voltage close to the voltage and the voltage applied to the second power supply terminal (7) or a voltage close to the voltage. 5), wherein the driving unit (5) has a first power source terminal (6)
A first operating mode in which a second voltage lower than the first voltage is applied to the second power supply terminal (7), and a third voltage is applied to the first power supply terminal (6). And a second operation mode in which a fourth voltage higher than the third voltage is applied to the second power supply terminal (7), respectively, and an output voltage according to the first or second operation mode. Flash memory characterized by switching between. 2. The decoding unit (4) and the driving unit (5)
A row decoder (3) for selecting a column of the memory cell array (1), wherein the flash memory includes a level conversion circuit (9) for converting a level of a signal to the decoding unit (4); A drive unit power supply switching circuit (11) for switching the power supply of the drive unit (5), and a high voltage supply unit (1) for selectively supplying a positive potential and a high potential.
3) and a negative voltage supply unit (1 that selectively supplies zero potential and negative potential)
4) and the positive potential, the high potential, the zero potential, and the negative potential are negative potential <
There is a relation of zero potential <positive potential <high potential, and the drive unit power source switching circuit (11) is configured to read data from the memory cell array (1) at the time of reading data.
The positive potential is supplied to the first power supply terminal (6) of the drive unit (5) and the zero potential is supplied to the second power supply terminal (7), and when data is written in the memory cell array (1),
The high potential is supplied to the first power supply terminal (6) of the drive unit (5) and the zero potential is supplied to the second power supply terminal (7), and when erasing data in the memory cell array (1), The negative potential is applied to the first power supply terminal (6) of the drive section (5),
The flash memory according to claim 1, wherein the positive potential is supplied to each of the second power supply terminals (7). 3. The level conversion circuit (9) includes a first terminal (21) to which an output ( _VIH ) of the high voltage supply section (13) is supplied and a negative voltage supply section (14). A second terminal (22) to which an output (V _IN ) is supplied, and when the input of the level conversion circuit is at “H” level (≦ output of high voltage supply section (13)) Terminal (21)
The voltage applied to the second terminal (22) or the voltage close to the voltage applied to the second terminal (22) when the input is at the “L” level (≧ the output of the negative voltage supply unit (14)). 3. The flash memory according to claim 2, wherein a voltage close to is output selectively. 4. The driving unit (5) is included in a well region (Nwell or Pwell) of a second conductivity type formed on a substrate (P-sub or N-sub) of the first conductivity type. One conductivity type well region (P
well or Nwell) and the well region of the second conductivity type (Nwell or Pwe).
a channel region of a first conductivity type formed in the semiconductor device, and a well region (Pwell or Nwe) of the first conductivity type.
11. The flash memory according to claim 1, 2 or 3, further comprising: a second conductivity type channel transistor formed in 11). 5. The decoding unit (4) has two-phase outputs whose logics are mutually inverted, and the driving unit (5) is provided on a first conductivity type substrate (P-sub or N-sub). The well region (P well) of the first conductivity type included in the well region (Nwell or Pwell) of the second conductivity type to be formed.
well or Nwell) and the first conductivity type well region (Pwell or Nwe).
4. The flash memory according to claim 1, 2 or 3, wherein the flash memory has two second conductivity type channel transistors formed in 11) and each of the two-phase outputs is connected to a gate of the transistor. 6. A p-channel transistor for pull-up.
(T_p6) and n-channel transistor for high voltage blocking
Star (T_n5) and a p-channel transformer for blocking negative voltage
Dista (T_p5) and n-channel tiger for pull-down
Register (T _n6) and transistor connected in series
A column and the pull-up transistor (T_p6) and the high voltage
Blocking transistor (T_nGate is connected to the connection point of 5)
The pull-down transistor (T_n6) Game
Output p-channel transistor with drain connected to
Star (T_p7) and the negative voltage blocking transistor (T_p5) and the Pluda
Untransistor (T_nGate is connected to the connection point of 6)
The pull-up transistor (T_p6) Game
N-channel output transistor with drain connected to
Star (T_n7) and the output p-channel tiger
Register (T_p7) Drain and the output n channel
Transistor (T_n7) The drain is connected
A level conversion circuit characterized by the following. 7. The high voltage blocking transistor (T
_n 5) and drain are connected to each other, and an inversion n-channel transistor (T _n 10) having one gate connected to the other source and the negative voltage blocking transistor (T _p 5) and drain are connected to each other. And an inversion p-channel transistor (T _p 1
0) and the high voltage blocking transistor (T
7. The level conversion circuit according to claim 6, wherein a logically inverted signal is applied to a terminal connected to _n 5) and the gate of the negative voltage blocking transistor (T _p 5), respectively. 8. A resistive element component is provided between the drain of the output p-channel transistor (T _p 7) and the drain of the output n-channel transistor (T _n 7). 7. The level conversion circuit according to any one of 7. 9. The level conversion circuit according to any one of claims 7 to 10 is provided as a level conversion circuit (9) for converting the level of a signal to the decoding section (4). Flash memory described in. 10. A first terminal (47A) receives an input signal (i).
n) is connected to the input terminal (44), and the second terminal (47B) is connected to the first output terminal (45) which outputs the first output signal (S ₁ ). The connection switch element (47) and the first terminal (48A) are connected to the input terminal (44), and the second terminal (48B) outputs the second output signal (S ₂ ). A second connecting switch element (48) connected to the output terminal (46) of the first connecting switch element (47) and an input terminal of the second connecting switch element (47)
Is connected to the second output terminal (46), and the output terminal is connected to the second output terminal (46).
_A first voltage line (51) supplied with a desired voltage (V _IH ) above _CC ) and a desired voltage (V _IN ) below zero voltage (V _SS ).
A first inverter (49) connected to a second voltage line (52) to which is supplied, and an input terminal of the second connection switch element (48)
(48B), the output terminal is connected to the first output terminal (45), and the power source is the first voltage line (51) and the second voltage line (52). And a second inverter (50) connected between the two, and a level conversion circuit. 11. The first switch element (47) comprises:
11. The level conversion according to claim 10, wherein the level conversion is made up of a pMOS transistor having its gate as a control terminal, and the second switch element (48) is made of an nMOS transistor having its gate as a control terminal. circuit. 12. The first voltage line (51) and the p
High voltage conversion is performed by supplying a desired voltage (V _IH ) higher than the power supply voltage (V _CC ) to the gate of the MOS transistor and supplying the power supply voltage (V _CC ) to the gate of the nMOS transistor. The level conversion circuit according to claim 11, wherein the level conversion circuit is controlled by the following. 13. The second voltage line (52) and the n
By supplying a desired voltage (V _IN ) lower than the zero voltage (V _SS ) to the gate of the MOS transistor and supplying a zero voltage (V _SS ) to the gate of the pMOS transistor,
The level conversion circuit according to claim 11, wherein the level conversion circuit is controlled to perform negative voltage conversion. 14. The pMOS transistor and the n
After the current state is latched by turning off the MOS transistor, the power source voltage (V
_12. The level conversion circuit according to claim 11, wherein the level conversion circuit is controlled to perform a high voltage conversion by supplying a desired voltage ( _VIH ) higher than _CC ). 15. The pMOS transistor and the n
After the current state is latched by turning off the MOS transistor, a desired voltage (V _IN ) lower than the zero voltage (V _SS ) is supplied to the second voltage line (52) to thereby obtain a negative voltage. The level conversion circuit according to claim 11, wherein the level conversion circuit is controlled so as to perform conversion. 16. The positive side power supply terminal of the second inverter (50) is not connected to the first voltage line (51) and is connected to the second side via an additional p-channel transistor (T _p 24). 16. The switch element (47) of No. 1 is connected to the gate control terminal of the pMOS transistor, and the gate of the additional p-channel transistor (T _p 24) is connected to the input terminal. The level conversion circuit according to any one of the above. 17. A p-channel transistor for pull-up.
Star (T_p16), the first resistance element component, and pull-down
N-channel transistor (T_n16) and in series
A connected first transistor resistance string and the pull-up transistor (T_p16) and the first
The gate is connected to the connection point of the resistance element component and the drain is
The pull-down transistor (T_n16) at the gate
Connected first type conductivity type transistor (T_p17)
And the pull-down transistor (T_n16) and the first
The gate is connected to the connection point of the resistance element component and the drain is
The pull-up transistor (T_p16) at the gate
Connected second type conductivity type transistor (T_n17)
And the first type conductivity type transistor (T_p17) Dray
And a second type conductivity type transistor (T_n17)
The second resistance element component connected between the rain and the drain are respectively connected to both ends of the first resistance element component.
And the gate and source are connected to each other
Second type conductivity type transistor (T_n20, T _n21)
And the drain is connected to both ends of the second resistance element component, respectively.
And the gate and the source are connected to each other.
The two second-type conductivity type transistors (T_nTwo
0, T_n21) a first type conductivity type connected to the source
Langista (T _p22, T_p23) and
Level conversion circuit to be used. 18. A flash decoder characterized in that a row decoder is provided with the level conversion circuit according to any one of claims 10 to 17, and the word line is driven by the output of the level conversion circuit. memory. 19. A row decoder is provided with the level conversion circuit according to claim 10, a plurality of word line drivers are provided in a stage subsequent to the level conversion circuit, and power supply lines of the plurality of word line drivers are provided. A flash memory characterized by being configured to independently control a voltage and drive a word line. 20. A power supply line connected to a potential control target portion
(V_BS), A negative voltage source (100) for outputting a negative voltage to the substrate, a well or a source and a power source line (V_BS) Connected to
And the drain has zero power supply (V_SS) Connected to the first n
Channel type transistor (T_n30), the substrate or the well and the source are connected to the power source line (V_BS) Connected to
And the drain is the first n-channel transistor
(T_n30) A second n channel connected to the gate
Type transistor (T_n29) and the first n-channel transistor (T_n30)
Gate and positive power supply (V_CC) The first switch provided between
A second n-channel transistor (T1)_n29)
Connect the gate to the positive power supply (V _CC) Or zero power source (V_SS)
Second switch (SW
2), and the second n-channel transistor (T_n29)
Provided with a capacitive element (C) connected between the gate and the source
Well, when no negative voltage is applied, the negative voltage source (100) is turned on.
In the non-output state, the first switch (SW1) is connected.
The second switch (SW2) to the zero power source (V_SS)
When applying a negative voltage, the first switch (SW
At the same time when 1) is opened, the second switch (SW2)
Positive power supply (V_CC), And then the second switch (S
W2) is opened and the negative voltage source (V_BB) Is output
A substrate potential control circuit characterized by the following states. 21. A power supply line connected to a substrate or a well
(V_BS), A negative voltage source (100) for outputting a negative voltage to the substrate, a well or a source and a power source line (V_BS) Connected to
And the drain has zero power supply (V_SS) Connected to the first n
Channel type transistor (T_n30), the substrate or the well and the source are connected to the power source line (V_BS) Connected to
And the drain is the first n-channel transistor
(T_n30) A second n channel connected to the gate
Type transistor (T_n29) and the first n-channel transistor (T_n30)
Positive power supply (V_CC) And zero power supply (V_SS) Voltage
A first gate voltage source (102) that is applied selectively, and the second n-channel transistor (T_n29)
Connect the gate to the positive power supply (V _CC) Or zero power source (V_SS)
Second switch (SW
2), and the second n-channel transistor (T_n29)
Provided with a capacitive element (C) connected between the gate and the source
Well, when no negative voltage is applied, the negative voltage source (100) is turned on.
In the non-output state, the first gate voltage source (102) is positive
Power supply (V_CC) Of the second switch (SW
2) Zero power supply (V_SS), And when applying a negative voltage, first, the first gate voltage source
(102) is a zero power source (V _SS) To output the voltage
At the same time as switching, the second switch (SW2) is used as a positive power source.
(V_CC), And then the second switch (SW2)
The negative voltage source (V_BB) Is the output state
A substrate potential control circuit characterized by: 22. The control gate (C
In G), a negative voltage applied to the control gate (CG) in a method of erasing a flash memory in which stored information is erased by applying a voltage negative to the voltage of the channel of the memory cell,
A method for erasing a flash memory, wherein the channel voltage applied to the channel is regulated to a constant value. 23. A control gate (C of a memory cell
In G), a negative voltage applied to the control gate (CG) is used as a reference voltage in the erasing method of the flash memory for erasing stored information by applying a voltage that is negative with respect to the voltage of the channel of the memory cell. The flash memory erasing method is characterized in that the channel voltage applied to the channel is regulated to a constant value with respect to the reference voltage. 24. A control gate (C of a memory cell
G) is a method for erasing stored information by applying a voltage that is negative with respect to the voltage of the source (S) of the memory cell to a negative voltage applied to the control gate (CG). To
A flash memory which is regulated to have a constant value with respect to a source voltage applied to the source (S). 25. A control gate (C of a memory cell
G) is a method for erasing stored information by applying a voltage that is negative with respect to the voltage of the source (S) of the memory cell to a negative voltage applied to the control gate (CG). To
While regulating to a constant value with respect to the reference voltage,
A method of erasing a flash memory, wherein a source voltage applied to the source (S) is regulated to a constant value with respect to the reference voltage. 26. A floating gate comprising a negative voltage source (110) for generating a voltage negative with respect to a voltage applied to a substrate or a well, and applying the generated negative voltage to a control gate (CG). In a flash memory for erasing the electric charge in (FG), a voltage regulating means (113) for regulating the negative voltage generated by the negative voltage source (110) to a predetermined value with respect to the potential of the substrate or well is provided. A flash memory characterized by being provided. 27. A substrate voltage source (116) for generating a voltage applied to a substrate or a well, and a control gate (C).
And a negative voltage source (110) for generating a negative voltage to be applied to the floating gate (FG) by applying a voltage negative to the potential of the substrate or well to the control gate (CG). In a flash memory for erasing electric charges in the substrate, a substrate voltage regulating means (115) for regulating a voltage generated by the substrate voltage source (116) to a first predetermined value with respect to a reference potential, and the negative voltage. A flash memory, comprising: a negative voltage regulating means (113) which regulates a negative voltage generated by a power source (110) to a second predetermined value at the reference potential. 28. A floating gate (FG) comprising a negative voltage source (110) for generating a voltage negative with respect to the potential of the source (S), and applying the generated negative voltage to the control gate (CG). In the flash memory for erasing the electric charge in the above), the negative voltage source (110) is provided with a voltage regulating means (113) for regulating such that the negative voltage is a predetermined value with respect to the potential of the source (S). Flash memory characterized in that. 29. A source voltage source (116) for generating a voltage applied to the source (S), and a control gate (C).
And a negative voltage source (110) for generating a negative voltage applied to the floating gate (FG) by applying a voltage negative to the potential of the source (S) to the control gate (CG). In the flash memory for erasing the electric charge in the above), source voltage regulating means (115) for regulating the voltage generated by the source voltage source (116) to a first predetermined value with respect to a reference potential; A flash memory, comprising: a negative voltage regulating means (113) for regulating a negative voltage generated by a voltage source (110) so as to reach a second predetermined value at the reference potential.