JP2013236235A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fabricate a semiconductor integrated circuit configured to operate on a plurality of systems of power supplies by a standard CMOS process.SOLUTION: There is a voltage switching circuit including: a decoder for selecting either a voltage VD3 or a voltage VSS to be output as a first signal in response to a signal ERS, selecting either a voltage VD5 (>VD3) or the voltage VSS to be output as a second signal in response to a signal VFY, and outputting a third signal in the same voltage range in response to the first and second signals; a level shifter LS3 for converting a first logic signal into a fourth signal in the range of a voltage VDDH (≥VD5) to the voltage VD5 to output it; a buffer BUF1 for buffering and outputting the second and third signals; and selection means HVSW1 for outputting any one of the voltage VDDH, the voltage VD3 and a voltage VSWL as a voltage VWL in response to the fourth signal and the buffered second and third signals.

Description

  The present invention relates to a semiconductor integrated circuit that operates with a plurality of power supply voltages.

  2. Description of the Related Art In recent years, in semiconductor integrated circuits, the withstand voltage of elements has been reduced along with miniaturization of elements such as MOSFETs (Metal Oxide Field Effect Effect Transistors: transistors of metal-oxide film-semiconductor structure; simply referred to as transistors hereinafter). There is a need to lower the power supply voltage of semiconductor integrated circuits. For example, when the processing technology of the device is about 350 nm, the power supply voltage of the semiconductor integrated circuit is 3 V to 5 V. However, as the processing technology is miniaturized to 130 nm and 65 nm, the withstand voltage of the device decreases, and the semiconductor integrated circuit The power supply voltage is decreasing to 1.8V and 1.2V.

  However, in a system including an analog circuit that drives a liquid crystal, a sensor, or the like, a 3V power source or a 5V power source is necessary to operate the analog circuit. For this reason, when configuring an LSI chip including this type of analog circuit, the miniaturized internal circuit is operated with a low voltage power supply such as 1.2 V, and the analog circuit and the input / output interface circuit are driven with 3 V to 5 V. It is necessary to adopt a multi-power supply configuration such as a

  In addition, nonvolatile memories such as flash memory and EEPROM (Electrically Erasable and Programmable Read Only Memory) are used for many purposes because information does not disappear even when the power is turned off. However, this type of nonvolatile memory requires a high voltage for writing and erasing data. Therefore, this type of non-volatile memory also employs a multi-power supply configuration.

JP 2006-140211 A

  Conventionally, logic circuits that require high-speed operation and require finer technology due to the large number of elements are composed of low-voltage transistors with thin oxide films, and input / output interface circuits and high-voltage circuits have thick oxide films. The high voltage transistor was used.

  Thus, under the conventional technology, it was necessary to make a high voltage transistor in addition to the standard transistor corresponding to miniaturization. For this reason, it is necessary to manufacture a transistor by changing a plurality of types of oxide film thicknesses, and the number of processes is large and the process is expensive. In addition, since the manufacturing process is complicated, it is necessary to pay attention to the yield. In addition, since the process is expensive and the yield is low, there is a problem that the price of the product increases.

  In addition, when making a product composed of a single nonvolatile memory, there is only a problem that the price of the memory is increased. However, a so-called embedded (non-volatile memory) in which a nonvolatile memory and a logic circuit or an analog circuit are mixedly mounted on the same chip. In the case of Embedded products, a more important problem arises. In other words, in addition to the fine standard transistor that constitutes the memory, in order to construct a high breakdown voltage transistor with a thick oxide film, the thermal process of the process is changed, and the characteristics of the standard transistor that constitutes the memory also change. Occur. In particular, analog circuits such as memory sense amplifiers are sensitive to transistor characteristics, and each time the transistor characteristics change, tuning is required. For this reason, there is a problem that a large loss occurs in a semiconductor manufacturer having many analog IPs.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique that makes it possible to configure a semiconductor integrated circuit that is operated by a plurality of power sources by a standard CMOS process.

  In order to solve the above problems, the present invention selects either the voltage of the first high-potential power supply node or the voltage of the low-potential power supply node according to the signal value of the first operation instruction signal. On the other hand, one of the voltage of the second high-potential power node and the voltage of the low-potential power node, which is higher than the first high-potential power node, is used as the signal value of the second operation instruction signal. In response to selection and output as a second logic signal, the voltage of the second high-potential power supply node and the voltage of the low-potential power supply node are set to the signal values of the first and second operation signals, respectively. And a third high-potential power node voltage that is higher than the second high-potential power node, and a voltage of the third high-potential power node. And the voltage of the low-potential power node One of the voltage and the level shifter that outputs as the fourth logic signal, and the second logic signal is buffered and output as the fifth logic signal. A buffer for buffering the third logic signal and outputting it as a sixth logic signal; a voltage at the third high-potential power node; a voltage at the first high-potential power node; Selecting means for selecting and outputting any one of the voltages different from the voltage of the first high potential power supply node in accordance with the fourth, fifth and sixth logic signals, unlike the voltage of the potential power supply node; And a voltage switching circuit.

  As a specific configuration of the selection means, a P-channel transistor and a first N-channel transistor inserted in series between the third high-potential power node and the first high-potential power node, A drain is connected to a common connection point of the drain of the P-channel transistor and the drain of the first N-channel transistor, and an intermediate voltage between the voltage of the first high-potential power supply node and the voltage of the low-potential power supply node is applied. A second N-channel transistor having a source connected to a power supply node, the gate of the P-channel transistor is provided with the fourth logic signal, and the gate of the first N-channel transistor is provided with the second N-channel transistor. 6 logic signal is applied, and the gate of the second N-channel transistor is provided with the fifth logic signal, and the P channel is applied. Configuration common connection point of the drains of said first N-channel transistor of the transistor is an output node is contemplated. Although the details will be described later, according to the high voltage switching circuit having such a configuration, the P-channel transistor and the N-channel transistor constituting the selection means can be used in a flash memory while having a low withstand voltage that can be manufactured by a normal process. High voltage applied to the row selection circuit (voltage switching for generating a word line voltage corresponding to an operation such as writing) can be performed.

  Further, the level shifter is configured to select either the voltage of the third high potential power supply node or the voltage of the low potential power supply node according to the first logic signal and output as a seventh logic signal, The selection means includes a first P-channel transistor and an N-channel transistor inserted in series between the third high-potential power supply node and the first high-potential power supply node, and the second high-potential power supply node. Second and third P channel transistors interposed between a power supply node and a common connection point between drains of the first P channel transistor and the N channel transistor, and the first P channel The gate of the transistor is supplied with the fourth logic signal, the gate of the N-channel transistor is supplied with the sixth logic signal, and the second P-channel is supplied. The fifth logic signal is applied to the gate of the transistor, the seventh logic signal is applied to the gate of the third P-channel transistor, and the drains of the first P-channel transistor and the N-channel transistor. A configuration in which a common connection point between the two nodes is used as an output node is also possible. Although the details will be described later, according to the voltage switching circuit having such a configuration, the P-channel transistor and the N-channel transistor constituting the selection unit can be manufactured using a low-breakdown-voltage transistor that can be manufactured by a normal process. It is possible to switch a high voltage applied to the column selection circuit (voltage switching for generating a bit line voltage corresponding to an operation such as writing).

  As a more preferable configuration, the level shifter for outputting the fourth logic signal and the level shifter for outputting the seventh logic signal are separately provided, and the delay amount in each can be adjusted. A first delay circuit that delays the first logic signal output from the decoder and applies the fourth logic signal to a level shifter; and a first logic output from the decoder A second delay circuit for delaying a signal and providing it to a level shifter for outputting the seventh logic signal; and a third delay circuit for delaying a second logic signal output from the decoder and applying it to the buffer; It is conceivable to further include a fourth delay circuit that delays the third logic signal output from the decoder and supplies the third logic signal to the buffer. According to such a configuration, it is possible to finely adjust the rising timing and falling timing of the output voltage of the selection means by adjusting the delay amount in each of the first to fourth delay circuits. The voltage switching circuit having such a configuration is particularly suitable for a circuit for switching a high voltage applied to a column selection circuit of a flash memory. This is because it is important to be able to finely adjust the rise timing and fall timing at the design stage of this type of circuit. The first to fourth delay circuits have a level shifter that outputs the fourth logic signal and a level shifter that outputs the seventh logic signal, respectively, and each of which can adjust the delay amount. The fourth logic signal output from the level shifter that outputs the fourth logic signal is delayed and provided to the selection means, and the level shifter that outputs the seventh logic signal is output. A second delay circuit for delaying the seventh logic signal to be provided to the selection means, and a third delay circuit for delaying the fifth logic signal output from the buffer to be provided to the selection means; The same effect can be obtained by a configuration including a fourth delay circuit that delays the sixth logic signal output from the buffer and supplies the sixth logic signal to the selection means.

  In order to solve the above problem, the present invention provides a decoder that selects and outputs either the voltage of the first high-potential power supply node or the voltage of the low-potential power supply node according to the signal value of the operation instruction signal; An intermediate voltage which is an intermediate voltage between the voltage of the second high potential power supply node and a voltage of the second high potential power supply node which is higher than the voltage of the first high potential power supply node. Is selected in accordance with the output signal of the decoder, and is output as a first logic signal. The level shifter outputs the second logic signal by logically inverting the output signal of the decoder; Based on a buffer for buffering a logic signal, and the first logic signal and the second logic signal that has been buffered by the buffer, the voltage of the second high potential side power supply node and the low power To provide a voltage switching circuit, characterized by having a selection means for selecting and outputting either one of the voltage side power supply node.

  A specific configuration of the selection means includes a P-channel transistor and an N-channel transistor inserted in series between the first high-potential power supply node and the low-potential power supply node. The gate is supplied with the first logic signal, while the gate of the N-channel transistor is supplied with a second logic signal that has been buffered by the buffer, and the drain of the P-channel transistor and the N-channel transistor. A configuration in which the common connection point of the drains is an output node is conceivable. Although details will be described later, according to the high voltage switching circuit having such a configuration, the P-channel transistor and the N-channel transistor constituting the selection unit can be written while using a low withstand voltage that can be manufactured by a normal process. Depending on the operation, it is possible to switch the voltage applied to the source line or WELL of the flash memory (PWELL if the nonvolatile memory cell is an N-channel floating gate transistor).

  In order to solve the above problems, the present invention selects either the voltage of the first high-potential power supply node or the voltage of the ground node according to the signal value of the operation instruction signal and outputs it as the first logic signal. A decoder; a switch that selects and outputs either the voltage of the first high-potential power supply node or the voltage of the ground node according to the signal value of the operation instruction signal; and the first high-potential power supply node An intermediate voltage, which is an intermediate voltage between the negative voltage and the negative voltage to which a negative voltage is applied, and the negative voltage are selected according to the first logic signal and output as a second logic signal A level shifter that selects one of the output voltage of the switch unit and the negative voltage according to the second logic signal and outputs it as a third logic signal, and the other as a fourth logic signal. A buffer to output, A voltage switching circuit comprising selection means for selecting and outputting either the voltage of the ground node or the negative voltage based on the third and fourth logic signals. .

  As a specific configuration of the selection means, a first P-channel transistor and a first N-channel transistor interposed in series between the ground node and the negative potential node, and the first P-channel transistor A second N-channel transistor connected in parallel to the first P-channel transistor and the gate of the first N-channel transistor to which the fourth logic signal is applied, The third N-channel transistor is supplied with the third logic signal at its gate, and the output node is a common connection point between the drain of the first P-channel transistor and the drain of the first N-channel transistor Can be considered. Although the details will be described later, according to the high voltage switching circuit having such a configuration, the P-channel transistor and the N-channel transistor constituting the selection means can be used in a flash memory while having a low withstand voltage that can be manufactured by a normal process. It is possible to switch the low-potential-side power supply voltage applied to the row selection circuit from the ground voltage to a negative voltage in order to erase data from. In a more preferred aspect, the buffer withstand voltage relaxation operation may be performed by controlling the output voltage of the switch section and the voltage of the negative potential node.

It is a figure which shows the oxide film thickness of the transistor in the MOS integrated circuit corresponding to various power supply voltages, and the limiting pressure | voltage resistance of the oxide film. It is sectional drawing which shows the structure of the CMOS circuit manufactured by the standard CMOS process. It is sectional drawing which shows the structural example of the high voltage | pressure-resistant CMOS circuit which expanded the LDD area | region of both the drain and the source, and improved the proof pressure. It is sectional drawing which shows the structural example of the high voltage | pressure-resistant CMOS circuit which expanded only the LDD area | region of the drain and improved the proof pressure. It is sectional drawing which shows the structure of a floating gate type non-volatile memory cell. It is a figure which shows operation | movement of the non-volatile memory cell. It is a circuit diagram which shows the structure of the non-volatile memory used in embodiment of this invention. 1 is a circuit diagram showing a configuration of a column selection circuit for column selection that is a part of a nonvolatile memory that is an embodiment of the present invention; FIG. It is a circuit diagram which shows the structural example of the 2nd column decoder 4000 contained in the same column selection circuit. 5 is a diagram showing an operation example of the second column decoder 4000. FIG. 5 is a diagram showing an operation example of the second column decoder 4000. FIG. 1 is a circuit diagram showing a configuration of a row selection circuit for row selection that is a part of a nonvolatile memory according to an embodiment of the present invention. FIG. It is a circuit diagram which shows the structure of main decoder 5000-p and selection switch 6000-pk included in the same row selection circuit. It is a figure for demonstrating operation | movement of the main decoder 5000-p and the selection switch 6000-pk. It is a circuit diagram of the subdecoder 7000 included in the same row selection circuit. It is a figure which shows the structural example of the voltage switching circuit of this embodiment. It is a figure which shows the voltage value which the power supply circuit 1 produces | generates at the time of each of the time of data writing, verification, erasing, and reading. 2 is a diagram illustrating a configuration example of a VWL switching circuit 10. FIG. 3 is an operation voltage table of a VWL switching circuit 10; 3 is a diagram illustrating a configuration example of a VWELL switching circuit 20. FIG. 3 is an operation voltage table of a VWELL switching circuit 20; 3 is a diagram illustrating a configuration example of a VCOL switching circuit 30. FIG. 3 is an operation voltage table of a VCOL switching circuit 30. 3 is a diagram illustrating a configuration example of a VBBM switching circuit 40. FIG. 3 is an operation voltage table of a VBBM switching circuit 40. It is a figure which shows the structural example of the VCOL switching circuit of a modification (1). It is a figure which shows the structural example of the VCOL switching circuit of the modification (1). It is a figure which shows the example of an operation | movement waveform of a modification (1). It is a figure which shows the example of an operation | movement waveform of a modification (1).

Embodiments of the present invention will be described below with reference to the drawings.
<High breakdown voltage technology used in the present invention>
In the embodiment of the present invention, a high withstand voltage technique generally used in a CMOS circuit is used. Therefore, prior to the description of the embodiment of the present invention, a technique for increasing the breakdown voltage of the CMOS circuit will be described.

  FIG. 1 shows the oxide film thickness of a transistor in a MOS integrated circuit corresponding to various power supply voltages and the limiting breakdown voltage (voltage that breaks down the gate oxide film in a certain time). Usually, in order to realize a MOS integrated circuit capable of guaranteeing operation for 10 years, the electric field applied to the oxide film is set to about 5 MeV (megaelectron volts), but the upper limit of the electric field that can be applied to the oxide film Is set to approximately 8 MeV.

  FIG. 2 is a cross-sectional view showing a configuration of a CMOS circuit manufactured by a standard CMOS process. This CMOS circuit employs an LDD (Lightly Doped Drain) structure in order to suppress the generation of hot electrons and improve the reliability of the transistor. This LDD structure is a structure in which a low-concentration impurity region is provided between a source, a drain and a channel so that a high electric field is not concentrated here. In order to form a transistor having an LDD structure, a side wall (generally an oxide film) is added to the side wall of the gate of the transistor, and n− or p− is set using the gate with the side wall added as a mask. Injected by implantation. In this case, the transistor can be manufactured by self-alignment, and the required area of the transistor is not increased. For example, when a CMOS circuit having a gate breakdown voltage of 5V is realized by the configuration shown in FIG. 2, the oxide film is set to a thickness of about 90 mm (angstrom), and the breakdown voltage (TDDB: Time Dependent Dielectric Breakdown) is set to about 6V. . In this case, the drain breakdown voltage (Breakdown) is about 7V.

FIG. 3 is a cross-sectional view illustrating a configuration example of an HVDMOS (High Voltage Drain Metal Oxide Semiconductor) transistor in which the breakdown voltages of both the drain and the source of the CMOS circuit illustrated in FIG. 2 are improved. In this high voltage CMOS circuit, the LDD region (n ⁻ or p ⁻ region) in FIG. 2 is wide. By doing so, the drain breakdown voltage can be easily increased to 10 V or more. However, this configuration has the disadvantage that the gate and the diffusion region need to be sufficiently wide, and the layout area becomes large. As shown in FIG. 3, the structure of a P-channel transistor and an N-channel transistor in which both the drain and source LDD regions are expanded is called a double-sided high breakdown voltage structure.

  FIG. 4 is a cross-sectional view showing a configuration example of an HVDMOS transistor adopting a high breakdown voltage structure in which only the LDD region on the drain side of each channel transistor of the CMOS circuit shown in FIG. 2 is expanded. This configuration example has an advantage that the area increase is suppressed as compared with the configuration example of FIG. The structure of the P-channel transistor and the N-channel transistor shown in FIG. 4 is called a one-side high breakdown voltage structure. A technique for increasing the breakdown voltage of a circuit by using a transistor having a one-side high breakdown voltage structure is disclosed in Patent Document 1, for example.

<Configuration of Nonvolatile Memory in Embodiment of the Present Invention>
FIG. 5 is a cross-sectional view showing the configuration of an N-channel floating gate transistor used as a nonvolatile memory cell in the embodiment of the present invention. As shown in FIG. 5, the N-channel floating gate transistor has a floating gate FG arranged in an oxide film between a gate and a region between a source and a drain formed on a substrate (Pwell in the example shown in FIG. 5). It becomes the composition.

  FIG. 6 is a diagram showing an operation of the nonvolatile memory cell shown in FIG. At the time of writing (Program, abbreviated as Prog in FIG. 6), for example, the voltage VD = 5V is applied to the source via the bit line BIT at the drain of an N-channel floating gate transistor which is a nonvolatile memory cell to which data “1” is to be written. A voltage VS = 0V is applied, a voltage VG = 10V is applied to the gate via the word line WL, and 0V is applied to Pwell. As a result, electrons are injected into the floating gate FG, the threshold voltage of the N-channel floating gate transistor rises, and data “1” is written. Here, the N-channel floating gate transistor to which data “1” has not been written is in a state where electrons are not injected into the floating gate FG, the threshold voltage is low, and data “0” is stored. .

  At the time of erasing (Erase), the drain voltage VD, source voltage VS, and Pwell of the N-channel floating gate transistor are set to 10V, and the gate voltage VG is set to 0V or a negative voltage. As a result, electrons are extracted from the floating gate FG to Pwell and erased (that is, data “0” is stored).

  At the time of reading (Read), the drain voltage VD of the N-channel floating gate transistor is 0.6 V, the source voltages VS and Pwell are 0 V, the gate voltage VG is 3 V to 5 V, and the drain that flows through the bit line BIT at that time By determining the current, it is determined whether the N-channel floating gate transistor stores data “1” or “0”. Here, the drain voltage VD is set to a low voltage of about 0.6 V in order to prevent erroneous writing.

<Embodiment>
FIG. 7A is a diagram showing a configuration example of a nonvolatile memory driven by the voltage switching circuit according to one embodiment of the present invention. As shown in FIG. 7A, this nonvolatile memory includes a nonvolatile memory cell array, a column selection circuit, a row selection circuit, and an input circuit. FIG. 7B is a diagram illustrating a configuration example of the nonvolatile memory cell array in FIG. This nonvolatile memory cell is formed by arranging the nonvolatile memory cells shown in FIG. 5 in a matrix. As shown in FIG. 7B, in this nonvolatile memory cell array, word lines WLi (i = 0 to m) wired in the row direction and bit lines BITj (j = 0 to n) wired in the column direction. N-channel floating gate transistors, which are nonvolatile memory cells, are arranged corresponding to the respective intersections. More specifically, the gates of n + 1 N-channel floating gate transistors in the i-th row are connected to the i-th row word line WLi. The drains of m + 1 N-channel floating gate transistors in the j-th column are connected to the bit line BITj in the j-th column. In the example shown in FIG. 7B, the N-channel floating gate transistors in two adjacent rows (for example, the 0th row and the 1st row,..., The (m-1) th row and the mth row) share a common source. The common source is supplied with a source voltage VS through a common source line.

The row selection circuit in FIG. 7A is a circuit that selects one word line WLi indicated by a row address from m + 1 word lines WLi (i = 0 to m) in the nonvolatile memory cell array. The selection circuit is a circuit that selects one bit line BITj indicated by the column address from n + 1 bit lines WBITj (j = 0 to n) in the volatile memory cell array. Although details will be described later, the row selection circuit in FIG. 7A switches the voltage applied to the selected word line WLi according to the voltage VWL and the voltage VBBM supplied from the voltage switching circuit of the present embodiment. The selection circuit switches the voltage applied to the selected bit line BITj in accordance with the voltage VCOL supplied from the voltage switching circuit. This voltage switching circuit is a circuit for generating the source voltage VS and the voltage VWELL used as the above-described Pwell voltage in addition to the voltages VWL, VBBM, and VCOL.
The details of this voltage switching circuit will be clarified later.

<Configuration of column selection circuit>
FIG. 8 is a circuit diagram showing a configuration of a column selection circuit for column selection which is a part of the nonvolatile memory according to the embodiment of the present invention. In FIG. 8, bit lines BITj (j = 0 to n) are connected to the nonvolatile memory cell array shown in FIG.

  In FIG. 8, an input circuit 2000 generates a write voltage DINh at the gate of the data control transistor 1 based on a write signal WE and a data signal Dinh (h = 0-15). As shown in FIG. 4, the data control transistor 1 is an N-channel transistor having a one-side high breakdown voltage structure in which only the drain LDD region is expanded. A high voltage VPP output from a charge pump (not shown) is applied to the drain of the data control transistor 1, and the source of the data control transistor 1 is connected to the data node NA.

  In FIG. 8, q + 1 first column decoders 3000-x (x = 0 to q), k + 1 second column decoders 4000-y (y = 0 to k), a first column switch unit 330, As a whole, the second column switch unit 340 selects one bit line BITj corresponding to the column indicated by the column address YADD from the n + 1 bit lines BITj (j = 0 to n), and sets the data node NA to the data node NA. A column selection circuit to be connected is configured.

  More specifically, in this embodiment, there is a relationship of n + 1 = (k + 1) (q + 1) among the number n + 1 of bit lines, the number q + 1 of the first column decoders, and the number k + 1 of the second column decoders. Yes, n + 1 bit lines BITj (j = 0 to n) are divided into q + 1 groups each of k + 1 bit lines. Then, the second column decoder 4000-y (y = 0 to k) and the second column switch unit 340 respectively add, for example, a lower digit of the column address YADD for each of q + 1 groups x each including k + 1 bit lines. Based on this, one bit line in the group x is selected and connected to the intermediate node NBx.

  Specifically, P channel transistors 4p0y (y = 0 to k) and N are connected between the k + 1 bit lines BIT0 to BITk belonging to the first group x = 0 and the intermediate node NB0 corresponding to the group. Each of k + 1 column selection gates is inserted by a CMOS switch including channel transistors 4n0y (y = 0 to k). Further, between the k + 1 bit lines BITn-k to BITn belonging to the last group x = q and the intermediate node NBq corresponding to the group, a P channel transistor 4pqy (y = 0 to k) and an N channel are respectively provided. Each of k + 1 column selection gates by a CMOS switch including transistors 4nqy (y = 0 to k) is inserted. The same applies to other groups, and k + 1 column selection gates by CMOS switches are interposed between k + 1 bit lines belonging to the group and the intermediate node.

  On the other hand, two column selection lines COLBp0 and COLBn0 are connected to the second column decoder 4000-0. Here, the column selection line COLBp0 is a column selection gate connected to the first bit line in each of the k + 1 groups (in the illustrated example, the bit line BIT0 in the first group, the bit line BITn-k in the last group). The column select line COLBn0 is connected to the gate of the N channel transistor 4nx0 (x = 0 to q) of the same column select gate. In addition, two column selection lines COLBp1 and COLBn1 are connected to the column decoder 4000-1. Here, the column selection line COLBp1 is the column selection connected to the second bit line in each of the k + 1 groups (in the example shown, the bit line BIT1 in the first group, the bit line BITn−k + 1 in the last group). The gate is connected to the gate of the P-channel transistor 4px1 (x = 0 to q), and the column selection line COLBn1 is connected to the gate of the N-channel transistor 4nx1 (x = 0 to q) of the same column selection gate. The same applies to the other column decoders 4000-2 to 4000-k and the column selection lines connected to them.

  The second column decoder 4000-y (y = 0 to k) is associated with each value y that can be taken by the lower digits of the column address YADD. For example, when the lower digit of the column address YADD indicates 1, for example, the second column decoder 4000-1 outputs column selection voltages for turning on the column selection gates of the second column switch unit 340 to the column selection lines COLBp1 and COLBn1, respectively. . On the other hand, the column decoders other than the column decoder 4000-1 each output a column selection voltage for turning off the column selection gate connected to each other via the column selection line. As a result, only the column selection gate connected to the second bit line in each of the k + 1 groups is turned ON, and the bit lines BIT1,..., BITn−k + 1 are connected to the intermediate nodes NB0 to NBq, respectively.

  The first column decoder 3000-x (x = 0 to q) and the first column switch unit 330 are selected from the q + 1 intermediate nodes NBx (x = 0 to q) based on, for example, the upper digit of the column address YADD. A circuit that selects one intermediate node NBx and connects to the data node NA is configured.

  In the first column switch unit 330, between each of the intermediate nodes NBx (x = 0 to q) and the data node NA, the P channel transistor 3px (x = 0 to q) and the N channel transistor 3nx (x = 0 to 0). q + 1 column selection gates are respectively inserted by CMOS switches consisting of q).

  On the other hand, two column selection lines COLAp0 and COLAn0 are connected to the column decoder 3000-0. Here, the column selection line COLAp0 is connected to the gate of the P-channel transistor 3p0 of the column selection gate connected to the first intermediate node NB0, and the column selection line COLAn0 is connected to the gate of the N-channel transistor 3n0 of the same column selection gate. ing.

  Further, two column selection lines COLApq and COLAnq are connected to the last column decoder 3000-q. Here, the column selection line COLApq is connected to the gate of the P-channel transistor 3pq of the column selection gate connected to the last intermediate node NBq, and the column selection line COLAnq is connected to the gate of the N-channel transistor 3nq of the same column selection gate. ing. The same applies to the other column decoders 3000-x (x = 1 to q-1) and the column selection lines connected to them.

  The first column decoder 3000-x (x = 0 to q) is associated with each value x that can be taken by the upper digits of the column address YADD. When the upper digit of the column address YADD indicates 0, for example, the first column decoder 3000-0 outputs a column selection voltage for turning on the column selection gate of the first column switch unit 330 to the column selection lines COLAp0 and COLAn0. On the other hand, the first column decoders other than the first column decoder 3000-0 each output a column selection voltage for turning off the column selection gate connected to each other through the column selection line. As a result, only the column selection gate connected to the intermediate node NB0 is turned ON, and the intermediate node NB0 is connected to the data node NA.

<Configuration and Operation of Second Column Decoder 4000-y>
In the flash memory shown in FIG. 5 and FIG. 6, it is necessary to set the drain voltage VD, the source voltage VS, and the Pwell voltage to 10 V at the time of erasing. At this time, all the column decoders are not selected. However, since the column switch section is composed of CMOS switches, it is necessary to devise settings in order to turn off these CMOS switches.

  FIG. 9 is a circuit diagram showing a configuration example of the second column decoder 4000 corresponding to erasure. FIG. 9 illustrates one CMOS switch among the CMOS switches constituting the second column switch unit 340. This CMOS switch is composed of a P-channel transistor 4p and an N-channel transistor 4n. The Nwell in which the P-channel transistor 4p is formed is supplied with the high potential side power supply voltage VCOL, and the Pwell in which the N channel transistor 4n is formed is supplied with the low potential side power supply voltage VSS. The column decoder shown in FIG. 9 performs ON / OFF control of this CMOS switch.

  In the second column decoder 4000, the address match detection circuit 520, the inverter 530, and the inverter 510 are supplied with the high potential side power supply voltage VD3 and the low potential side power supply voltage VSS. The level shifter 400 and the inverters 540 and 570 are supplied with the high potential side power supply voltage VCOL and the low potential side power supply voltage VSS.

  The inverter 530 logically inverts the erase signal ERS and outputs it. The address match detection circuit 520 receives a lower digit of the column address and the inverted signal ERSB of the erase signal ERS. At the time of erasure (ERSB = L level (“0”)), this address match detection circuit 520 outputs H level (= VD3) regardless of the column address. Further, when it is not during erasure (ERSB = “1”) and the lower digit of the column address indicates a value associated with the column decoder, the address match detection circuit 520 sets the L level (= VSS). Output.

  In level shifter 400, P-channel transistors 410 and 420 have their sources connected to the high potential side power supply node to which power supply voltage VCOL is applied. P channel transistors 410 and 420 have their respective drains connected to their gates.

  Each of P-channel transistors 430 and 440 is a one-side high breakdown voltage transistor in which only the drain LDD region is expanded. The source of the P-channel transistor 430 is connected to the common connection node NN1 between the drain of the P-channel transistor 410 and the gate of the P-channel transistor 420. The source of the P channel transistor 440 is connected to the common connection node NN2 of the drain of the P channel transistor 420 and the gate of the P channel transistor 410. A bias voltage VBIAS2 (5V-Vthp at the time of erasure: Vthp is a threshold voltage of P channel transistors 430 and 440) is applied to each gate of P channel transistors 430 and 440.

  The source of the P channel transistor 430 is connected to the drain of the N channel transistor 490, and the drain of the P channel transistor 430 is connected to the source of the N channel transistor 490. Further, the drain of the N channel transistor 500 is connected to the source of the P channel transistor 440, and the source of the N channel transistor 500 is connected to the drain of the P channel transistor 440. Each of these N-channel transistors 490 and 500 is a one-side high breakdown voltage transistor in which only the drain LDD region is expanded. The gates of N channel transistors 490 and 500 are connected to output node NN5 of inverter 530.

  The address match detection circuit 520 preceding the N channel transistors 450 and 460, the inverter 510 and the level shifter 400 is connected to one drain of the P channel transistor 430 or 440 and the low potential side power supply node in accordance with the output signal of the address match detection circuit 520. Switch means for forming a current path with (VSS = 0V) is configured. Further details are as follows.

  N-channel transistors 450 and 460 are single-sided high breakdown voltage transistors in which only the LDD region of the drain extends, and each drain is connected to each drain of P-channel transistors 430 and 440, respectively. The source of N-channel transistor 450 is connected to output node NN3 of address match detection circuit 520, and the source of N-channel transistor 460 is connected to output node NN4 of inverter 510, respectively. Power supply voltage VD3 is applied to the gates of N channel transistors 450 and 460. N channel transistors 450 and 460 to which the power supply voltage VD3 is applied to the gate serve to regulate the voltages of nodes NN3 and NN4 to which the respective sources are connected so as not to exceed power supply voltage VD3.

  P channel transistor 470 has its source and drain connected to the source and drain of P channel transistor 410, respectively. P channel transistor 480 has its source and drain connected to the source and drain of P channel transistor 420, respectively. Bias voltage VBIAS1 is applied to the gates of P-channel transistors 470 and 480. This bias voltage BIAS1 is a voltage shifted from the voltage VCOL to the low potential side power supply voltage VSS = 0V side by the threshold voltage Vthp of the P-channel transistors 470 and 480.

  P channel transistors 470 and 480 to which bias voltage VBIAS1 is applied to the gate compensates for voltage drops at nodes NN1 and NN2 due to leakage current by supplementing nodes NN1 and NN2 with a small drain current flowing through each of them. Fulfill.

  Inverter 540 includes P-channel transistor 550 and N-channel transistor 560. Each of the P-channel transistor 550 and the N-channel transistor 560 is a one-side high breakdown voltage transistor in which only the LDD region of the drain extends. The P channel transistor 550 has a source connected to the high potential side power supply VCOL and a gate connected to the node NN 2 in the level shifter 400. The N-channel transistor 560 has a source connected to the low potential side power supply VSS and a gate connected to the node NN4 in the level shifter 400. P channel transistor 550 and N channel transistor 560 have their drains connected in common, and the common connection node outputs a column selection voltage to the gate of P channel transistor 4p via column selection line COLBp.

  On the other hand, inverter 570 includes P-channel transistor 580 and N-channel transistor 590. Each of the P-channel transistor 580 and the N-channel transistor 590 is a one-side high voltage structure transistor in which only the drain LDD region is expanded. The P channel transistor 580 has a source connected to the high potential side power supply VCOL and a gate connected to the node NN 1 in the level shifter 400. The N-channel transistor 590 has a source connected to the low potential side power supply VSS and a gate connected to the node NN 3 in the level shifter 400. P channel transistor 580 and N channel transistor 590 have their drains connected in common, and this common connection node outputs a column selection voltage to the gate of N channel transistor 4n via column selection line COLBn.

  Next, the operation at the time of erasing in this embodiment will be described. At the time of erasing (Erase), the power supply voltage VCOL for the level shifter 400 and the inverters 540 and 570 is set to 10 V as the erasing voltage (P well voltage). Since erase signal ERS is at H level, node NN5 is at L level (= VSS = 0V), and N-channel transistors 490 and 500 are turned off.

  Since the input signal ERSB (inverted signal of the erase signal ERS) to the address match detection circuit 520 is at L level, the output node NN3 of the address match detection circuit 520 is at H level (= VD3) regardless of the column address YADD. = 3V). As a result, the N channel transistor 450 and the P channel transistor 430 are turned off, and the drain node NN6 of the N channel transistor 450 and the output node NN1 of the level shifter 400 become 10V.

  On the other hand, since output node NN4 of inverter 510 is at L level (= VSS = 0V), N channel transistor 460 is turned ON, and node NN7 at the drain of N channel transistor 460 is at L level (0V). However, since the bias voltage VBIAS2 is 5V-Vthp, the level of the output node NN2 of the level shifter 400 becomes the lower limit value 5V determined by the bias voltage VBIAS2.

  Inverter 540 outputs 10V to column selection line COLBp because the gate voltage of P-channel transistor 550 is 5V and the gate voltage of N-channel transistor 560 is 0V. Inverter 570 outputs 0 V to column selection line COLBn because the gate voltage of P-channel transistor 580 is 10 V and the gate voltage of N-channel transistor 590 is 3 V (VD3). As a result, all the P channel transistors 4p connected to the column selection line COLBp and all the N channel transistors 4n connected to the column selection line COLBn are turned off.

  The above is the operation at the time of erasing. According to the present embodiment, even when the bit line BITj becomes 10 V at the time of erasing, the electric fields between the gates of the transistors 550, 560, 580, 590, 4p, and 4n and the well can all be reduced to the breakdown voltage or less. The nonvolatile memory can be operated at a high voltage without using a gate high breakdown voltage transistor having a thick oxide film.

  Note that all Nwells of the P-channel transistors 410, 420, 470, 480, 430, and 440 may be connected to the power source of the highest voltage VCOL or may be connected to their own source. If it is connected to its own source, there is a merit that it is not affected by the back bias, but it is necessary to provide Nwell of each transistor independently, and the required area becomes large.

  FIG. 10 shows the operating voltage of each part at the time of writing (Program) of the circuit shown in FIG. In FIG. 10, the power supply voltage VCOL is set to 5V at the time of writing. Since erase signal ERS attains L level, node NN5 becomes 3V, N-channel transistors 490 and 500 are turned ON, and nodes NN1 and NN6 and nodes NN2 and NN7 are short-circuited.

  Further, since the signal ERSB is at H level, when the column address YADD indicates a value associated with the column decoder, the output node NN3 of the address match detection circuit 520 is 0V, the output node NN4 of the inverter 510 is 3V, The output node NN1 of the level shifter 400 is 0V, and the output node NN2 is 5V. Therefore, inverter 540 outputs 0V to column selection line COLBp, and inverter 570 outputs 5V to column selection line COLBn. As a result, all the P channel transistors 4p connected to the column selection line COLBp and all the N channel transistors 4n connected to the column selection line COLBn are turned on. At this time, if the data node NA is set to the write voltage 5V, 5V is output to the selected bit line BITj.

  On the other hand, when the column address YADD does not indicate a value associated with the column decoder, the output node NN3 of the address match detection circuit 520 is 3V, the output node NN4 of the inverter 510 is 0V, and the output node NN1 of the level shifter 400 is 5V. The output node NN2 becomes 0V. Therefore, inverter 540 outputs 5V to column selection line COLBp, and inverter 570 outputs 0V to column selection line COLBn. As a result, all the P channel transistors 4p connected to the column selection line COLBp and all the N channel transistors 4n connected to the column selection line COLBn are turned off.

  FIG. 11 shows the operating voltage of each part at the time of reading (Read) of the circuit shown in FIG. As shown in FIG. 11, at the time of reading, the power supply voltage VCOL is 3V, and all the power supply voltages are 3V. The operation when the column decoder is selected and the operation when it is not selected are the same as those in FIG. At the time of reading, a voltage of 0.6 V is applied to the bit line BITj.

  As described above, in this embodiment, the voltage VCOL applied to the second column decoder 4000-y is switched to 5V / 10V / 3V, thereby performing data writing, erasing, and reading (or verification) to the nonvolatile memory cell. A column selection voltage is generated, and 5 V, 10 V, and 0.6 V are applied to the bit line in accordance with the column selection voltage.

<Configuration of row selection circuit>
FIG. 12 is a diagram illustrating a configuration example of the row selection circuit in FIG.
As shown in FIG. 12, the row selection circuit includes m + 1 selection switches 6000-pk (p = 0 to h, k) connected to each of the word lines WLi (i = 0 to m). = 0 to 3: However, 4 × (h + 1) = m + 1), one main decoder 5000-p (p = p) provided for each of the selection switches 6000-p0, 6000-p1, 6000-p2, and 6000-p3 0-h) and a sub-decoder 7000.

  In the present embodiment, one of the h + 1 main decoders 5000-p is selected based on, for example, the upper digit (hereinafter referred to as address ADDA) of the row address ADD, and the main decoder 5000-p in the selected state is selected. Gives a signal Mp to the four selection switches 6000-pk (k = 0 to 3) connected to the main decoder 5000-p. Although detailed illustration is omitted in FIG. 12, each of the four selection switches 6000-pk (k = 0 to 3) connected to the main decoder 5000-p (p = 0 to h) is connected to the signal line Fk ( k = 0 to 3) to the sub-decoder 7000. That is, h + 1 selection switches 6000-pk (p = 0 to h) are connected to one signal line Fk.

  The subdecoder 7000 is given, for example, a lower digit (hereinafter referred to as an address ADDB) of the row address ADD. The sub-decoder 7000 selects any one of the four signal lines Fk (k = 0 to 3) based on the address ADDB and applies a voltage corresponding to writing or the like. In the present embodiment, one of the four selection switches 6000-pk (k = 0 to 3) to which the signal Mp is given from the main decoder 5000-p is connected to the signal line Fk selected by the sub-decoder 7000. Is in a selected state, and a voltage (voltage VG in FIG. 6) corresponding to a situation such as data writing is applied to the word line WLi connected to the selection switch 6000-pk.

<Configuration of Main Decoder 5000-p and Selection Switch 6000-pk>
FIG. 13 is a diagram illustrating a configuration example of the main decoder 5000-p and the selection switch 6000-pk. In FIG. 13, the main decoder 5000-0 and the selection switches 6000-00 and 6000 among the four selection switches 6000-0k (k = 0 to 3) connected to the main decoder 5000-0. The configuration of -03 is shown. As shown in FIG. 13, the main decoder 5000-p includes a logic gate 380, a first level shifter LS01, and a second level shifter LS02.

  The output terminal of the logic gate 380 is connected to the first level shifter LS01 (more precisely, the inverter 37 in the first level shifter LS01). The logic gate 380 is supplied with the voltage VD3 (= 3V) of the first high potential side power supply node and the voltage VSS (= 0V) of the first low potential side power supply node, and also with the row address ADDA. The logic gate 380 outputs an L level (VSS, that is, 0 V) logic signal when the given row address ADDA matches a predetermined address, and conversely, the given row address ADDA is If it does not match the predetermined address, a logic signal of H level (VD3, that is, 3V) is output.

  First level shifter LS01 includes P channel transistors 35 and 36 and N channel transistors 31, 32, 33, and 34 in addition to inverter 37 described above. In the first level shifter LS01, between the input node N11 of the inverter 37 and the second low potential side power supply node to which the voltage VBBM (VBBM <VD3) is applied, a P channel transistor 35, an N channel transistor 33 and an N channel transistor are provided. 31 is inserted in series. A P-channel transistor 36, an N-channel transistor 34, and an N-channel transistor 32 are inserted in series between the output node N12 of the inverter 37 and the second low potential side power supply node. Each gate of P channel transistors 35 and 36 is always supplied with 0 V as a bias voltage. The drains of N channel transistors 33 and 34 are connected to the drains of P channel transistors 35 and 36, respectively. Bias voltage BIAS5 is applied to the gates of N channel transistors 33 and 34, respectively.

  The source of the N channel transistor 33 is connected to the common connection node N7 of the drain of the N channel transistor 31 and the gate of the N channel transistor 32, and the source of the N channel transistor 34 is connected to the drain of the N channel transistor 32 and the N channel transistor. The gate 31 is connected to a common connection node N8. As shown in FIG. 13, the second level shifter LS02 (more precisely, the inverter 17 included in the second level shifter LS02) is connected to the common connection node N8. Although details will be described later, in this embodiment, the voltages VD3, BIAS5, and VBBM, and VPP, BIAS1 to BIAS4, VDN, and VD5, which will be described later, are set as shown in FIG. Data writing, erasing, reading, etc. are realized. Here, the voltage VPP is a voltage of the high potential side power supply node (hereinafter referred to as the second high potential side power supply node) in the second level shifter LS02, and the voltage VD5 is a first intermediate voltage between the voltage VPP and the voltage VBBM. The voltage VDN is also a second intermediate voltage between the voltage VPP and the voltage VBBM (in this embodiment, VBBM <VDN ≦ VD3).

  The first level shifter LS01 of the present embodiment level-shifts the output signal of the logic gate 380, converts the output signal to a second logic signal having the voltage VBBM at the L level and the second intermediate voltage VDN at the H level. It plays the role of supplying to LS02. Although details will be described later, when writing or erasing data in the nonvolatile memory cell, the bias voltage BIAS 5 is set to a voltage higher than the voltage VDN by the threshold voltage Vthn of the N-channel transistors 33 and 34. Therefore, when data is written or erased, the N-channel transistor 33 has a gate-source voltage lower than the threshold voltage Vthn when the voltage of the node N7 connected to the source is higher than the voltage VDN. It becomes OFF. Further, when the voltage at the node N8 is to be higher than VDN, the N-channel transistor 34 is turned OFF because the gate-source voltage is lower than the threshold voltage Vthn. That is, when data is written or erased, the N-channel transistors 33 and 34 serve as separation means for separating the nodes from the high potential side so that the voltages at the nodes N7 and N8 do not exceed VDN. .

  Based on the output signal of the first level shifter LS01, the second level shifter LS02 generates a low potential side inverted logic signal ML obtained by inverting the high potential side logic signal MHB, the low potential side logic signal MLB, and the low potential side logic signal MLB. To each of the selection switches 6000-pk (k = 0 to 3). Here, the voltage level of the high potential side logic signal MHB is from the first intermediate voltage VD5 to the voltage VPP (VD5 <VPP) of the second high potential side power supply node, and the voltage level of the low potential side logic signal MLB is It is from the voltage VBBM of the second low potential side power supply node to the second intermediate voltage VDN (VBBM <VDN ≦ VD3). In the present embodiment, a combination of the high potential side logic signal MHB, the low potential side logic signal MLB, and the low potential side inversion logic signal ML is used as the signal Mp described above.

  As shown in FIG. 13, the second level shifter LS02 includes P-channel transistors 11, 12, 13, 14, 19, and 20, N-channel transistors 15, 16, 21, and 22, inverters 17, 18, 23, 24, And 25. Inverters 17, 18, 23, 24 and 25 are all CMOS inverters. Inverters 17, 18, 24, and 25 are supplied with voltage VDN and voltage VBBM as power supply voltages, and inverter 23 is supplied with voltage VPP and voltage VD5 as power supply voltages. In this embodiment, the output voltage of the inverter 23 is output as the high potential side logic signal MHB, the output voltage of the inverter 24 is output as the low potential side logic signal MLB, and the output voltage of the inverter 25 is output as the low potential side inverted logic signal ML. The

  In the second level shifter LS02, the P-channel transistors 11 and 12 are transistors having a gate breakdown voltage of 5V. The sources of P channel transistors 11 and 12 are connected to a second high potential side power supply node (a power supply node to which voltage VPP is applied). P channel transistors 11 and 12 have their respective drains connected to the respective gates. Each of the P-channel transistors 13 and 14 is a one-side high breakdown voltage structure transistor in which only the drain LDD region is expanded. The source of the P-channel transistor 13 is connected to the common connection node N 1 between the drain of the P-channel transistor 11 and the gate of the P-channel transistor 12. The source of the P-channel transistor 14 is connected to the common connection node N2 between the drain of the P-channel transistor 12 and the gate of the P-channel transistor 11. An inverter 23 is connected to the node N2.

  Bias voltage BIAS2 is applied to the gates of P-channel transistors 13 and 14. As shown in FIG. 14, the bias voltage BIAS2 is a voltage that is lowered from the first intermediate voltage VD5 by the threshold voltage Vthp of the P-channel transistors 13 and 14 when data is written to or erased from the nonvolatile memory cell. Is set. When writing or erasing data, if the voltage of the node N1 is going to be lower than the voltage VD5, the P-channel transistor 13 is turned OFF because the gate-source voltage becomes lower than the threshold voltage Vthp. On the other hand, when the voltage at the node N2 becomes lower than the voltage VD5, the P-channel transistor 14 is turned OFF because the gate-source voltage becomes lower than the threshold voltage Vthp. As described above, the P-channel transistors 13 and 14 serve as separation means for separating the nodes from the low potential side so that the voltages at the nodes N1 and N2 do not fall below VD5 when data is written or erased. .

  N channel transistors 15 and 16 have their drains connected to the drains of P channel transistors 13 and 14, respectively. The source of the N channel transistor 15 is connected to the output node N5 of the inverter 17, and the source of the N channel transistor 16 is connected to the output node N6 of the inverter 18. An inverter 24 is further connected to the output node N 6 of the inverter 18, and the output node of the inverter 24 is connected to the inverter 25. Bias voltage BIAS 4 is applied to the gates of N channel transistors 15 and 16. When writing or erasing data, the bias voltage BIAS4 is set to the same value as the voltage VDN. N-channel transistors 15 and 16 serve as separation means for separating these nodes from the high potential side so that the voltages at nodes N5 and N6 do not exceed VDN when data is written or erased.

  P channel transistor 19 has its source and drain connected to the source and drain of P channel transistor 11, respectively. That is, the P channel transistor 19 is connected in parallel with the P channel transistor 11. P channel transistor 20 has its source and drain connected to the source and drain of P channel transistor 12, respectively. That is, the P channel transistor 20 is connected in parallel with the P channel transistor 12. Bias voltage BIAS1 is applied to the gates of P-channel transistors 19 and 20. The bias voltage BIAS1 is a voltage shifted from the voltage VPP to the voltage VSS (= 0V) side by the threshold voltage Vthp of the P-channel transistors 19 and 20.

  A slight drain current flows through the P-channel transistors 19 and 20 to which the bias voltage BIAS1 is applied to the gate, and functions as a constant current source. Thus, if the P-channel transistors 19 and 20 that function as constant current sources are not provided, the voltages at the nodes N1 and N2 may drop due to the leakage current. However, in this embodiment, the drain current of each of the P-channel transistors 19 and 20 flows into the nodes N1 and N2, so that the voltage drop at the nodes N1 and N2 due to the leakage current is compensated. That is, P-channel transistors 19 and 20 serve as compensation means for compensating for voltage drops at nodes N1 and N2 due to leakage current. In the present embodiment, P channel transistors 19 and 20 each functioning as a constant current source are connected to each of nodes N1 and N2 in order to prevent the voltage at nodes N1 and N2 from dropping due to a leakage current. However, another circuit may be used as the constant current source, and a simple resistor may be used instead of the P-channel transistors 19 and 20 within a range where the leakage current does not cause a problem.

  N-channel transistor 21 is connected in parallel with P-channel transistor 13, and N-channel transistor 22 is connected in parallel with P-channel transistor 14. N-channel transistors 21 and 22 are each one-side high breakdown voltage transistors, and a bias voltage BIAS3 is applied to each gate. As shown in FIG. 14, the bias voltage BIAS3 is set to 0V when data is written, -5V when data is erased, and 3V when data is read. That is, N-channel transistors 21 and 22 are turned off at the time of data writing and erasing, and turned on at the time of data reading. That is, the N channel transistors 21 and 22 function as switches that are turned off when the node N1 and the node N2 are separated by the P channel transistors 13 and 14, and are turned on when the separation is not performed. Although details will be described later, when the N-channel transistors 21 and 22 are turned on, the second level shifter LS02 functions as a normal level shifter having an operating voltage of 3V.

Select switch 6000-pk includes P channel transistor 710 and N channel transistors 720 and 730. Here, the P-channel transistor 710 is formed in Nwell to which the voltage VPP is applied, and the N-channel transistors 720 and 730 are formed in Pwell to which the voltage VBBM is applied. Each of the P-channel transistor 710 and the N-channel transistor 720 is a high breakdown voltage transistor in which both the drain and source LDD regions are expanded. The P-channel transistor 710 and the N-channel transistor 720 are inserted in parallel between the signal line Fk and the word line WLi (i = 4 × p + k), and a high-potential side logic signal is connected to the gate of the P-channel transistor 710. MHB (= VPP or VD5) is applied, and the low-potential-side inversion logic signal ML is applied to the gate of the N-channel transistor 720. That is, the P-channel transistor 710 and the N-channel transistor 720 connect / disconnect the signal line Fk and the word line WLi in accordance with the high potential side logic signal MHB and the low potential side inversion logic signal ML (= VDN or VBBM). Functions as a switching CMOS switch. The N-channel transistor 730 is a transistor that selectively connects the word line WLi to the power supply VBBM, and a low potential side logic signal MLB (= VDN or VBBM) is applied to the gate.
The above is the configuration of the main decoder 5000-p and the selection switch 6000-pk.

<Operations of Main Decoder 5000-p and Selection Switch 6000-pk>
Next, operations of the main decoder 5000-p and the selection switch 6000-pk will be described.
<Operation during writing (Program)>
First, the operation at the time of data writing will be described. As shown in FIG. 14, when data is written, VPP = 10V, VD3 = 3V, VD5 = 5V, VBBM = 0V, VDN = 3V, BIAS1 = VPP-Vthp, BIAS2 = VD5-Vthp, BIAS3 = 0V, BIAS4 = 3V and BIAS5 = VDN (3V) + Vthn.

  When address ADDA matches a predetermined address, the output of logic gate 380 goes to L level (0 V). Therefore, the voltage at the node N11 of the first level shifter LS01 is at L level (0V), and the voltage at the node N12 is at H level (VD3, that is, 3V). In first level shifter LS01, the gate voltages of P-channel transistors 35 and 36 are 0V. Therefore, the P-channel transistor 35 is turned off, while the P-channel transistor 36 is turned on, and the voltage at the node N10 becomes VD3 (3V). Since the voltage of the node N10 is 3V and the gate voltage of the N-channel transistor 34 is VDN (3V) + Vthn, the N-channel transistor 34 is turned on and the voltage of the node N8 is 3V. Therefore, the N channel transistor 31 is turned on. On the other hand, the N-channel transistor 33 is turned off because the P-channel transistor 35 to which it is connected is turned off, and the voltage at the node N7 becomes 0V.

  In second level shifter LS02, since BIAS1 = VPP−Vthp is set, P channel transistors 19 and 20 operate at a constant current, and a voltage drop at nodes N1 and N2 due to a leakage current is prevented. In this operation example, since the bias voltage BIAS3 = 0V is applied to the gates of the N-channel transistors 21 and 22, the transistors 21 and 22 are turned off. Also, since the bias voltage BIAS2 applied to the gates of the P-channel transistors 13 and 14 is VD5-Vthp, if the voltage at the node N1 (or N2) is going to be lower than VD5, the P-channel transistor 13 (or 14) The node N1 (or the node N2) is kept at VD5 or higher. In this operation example, since the bias voltage BIAS4 = 3V (= VDN) is applied to the gates of the N-channel transistors 15 and 16, when the voltage at the node N5 (or N6) rises to 3V, The channel transistor 15 (or 16) is turned off, and the voltages at the nodes N5 and N6 are maintained at 3 V (= VDN) or lower.

  In this operation example, the voltage at the node N8 of the first level shifter LS01 is 3V (that is, H level), and the inverters 17 and 18 have the high potential side power supply voltage VDN (= 3V) and the low potential side power supply voltage VBBM (= 0V) is supplied, the voltage at the node N5 becomes L level (0V), and the voltage at the node N6 becomes H level (3V). Since the voltage at the node N5 is 0V, the N-channel transistor 15 is turned on, and the voltage at the node N3 is also 0V. The voltage at the node N1 is maintained at VD5 (= BIAS2 + Vthp = 5V) by the P-channel transistor 13. Since the voltage at the node N6 is 3V, the N-channel transistor 16 is turned off. At this time, since both the P-channel transistors 12 and 14 are turned on, the voltages at the nodes N2 and N4 are both 10 V (= VPP).

  As described above, the inverter 23 connected to the node N2 operates between the voltage VPP (= 10V) and the voltage VD5 (= 5V). In this operation example, the voltage at the node N2 (that is, the input voltage to the inverter 23) is H level (10V), so the output voltage of the inverter 23 is L level (5V). On the other hand, the inverter 24 connected to the node N6 and the inverter 25 connected to the output node of the inverter 24 are between the voltage VDN (3V in this operation example) and the voltage VBBM (0V in this operation example). Works with. In this operation example, since the voltage of the node N6 is 3V, the output of the inverter 24 is L level (0V), and the output of the inverter 25 is H level (3V). Therefore, the high potential side logic signal MHB becomes L level (5V) and the P channel transistor 710 is turned on, and the low potential side inverted logic signal ML becomes H level (3V) and the N channel transistor 720 is turned on. Then, the low potential side logic signal MLB becomes L level (= VBBM = 0V), the N-channel transistor 730 is turned off, and the selection switch 6000-pk is selected. On the other hand, when the address ADDA does not match the predetermined address, the operation is reversed, and the high potential side logic signal MHB becomes H level (= VPP = 10V), the P channel transistor 710 is turned off, and the low potential The side inversion logic signal ML becomes L level (= VBBM = 0V) and the N channel transistor 720 is turned off, and the low potential side logic signal MLB becomes H level (= VDN = 3V) and the N channel transistor 730 is turned on. The selection switch 6000-pk is in a non-selected state.

  Here, when the selection switch 6000-0p (p = 0 to 3) is in the selected state and the signal line F0 is selected by the sub-decoder 7000 (details will be described later, the voltage of the signal line F0 is 10V). When the voltages of the other signal lines F1, F2, and F3 are set to 0V), in the selection switch 6000-00, the P-channel transistor 710 and the N-channel transistor 720 are turned on, and the N-channel transistor 730 is turned off. In this case, the CMOS switch including the P-channel transistor 710 and the N-channel transistor 720 transmits the 10V voltage of the signal line F0 to the word line WL0 with almost no decrease. Since the voltages of the signal lines F1, F2, and F3 are 0V, the voltages of the word lines WL1, WL2, and WL3 are 0V. In this state, when a voltage of 5V is applied to the bit line BITj connected to the nonvolatile memory cell to which data is to be written, a voltage of 0V is applied to the source line, and a voltage of 0V is applied to Pwell, data “1” to the nonvolatile memory is supplied. "Is written. Note that if the address ADDA does not match the predetermined address, the P-channel transistor 710 and the N-channel transistor 720 are turned off and the N-channel transistor 730 is turned on, regardless of the voltage of the signal lines F0 to F3. The voltages of the word lines WL0 to WL3 are 0V, and data “1” is not written to the nonvolatile memory cells connected to these word lines.

  In this operation example, the transistors that require attention to the gate breakdown voltage are the P-channel transistors 13 and 14, the transistors constituting the inverter 23, the P-channel transistor 710, and the N-channel transistors 720 and 730. A voltage of 5V-Vthp is applied to each gate of P-channel transistors 13 and 14. Therefore, there is no problem with the gate breakdown voltage of P-channel transistors 13 and 14 even if NWell becomes 10V. Further, since the amplitude of the voltage applied to the gates of the N-channel transistor and P-channel transistor constituting the inverter 23 is 5V, there is no problem with the gate breakdown voltage of these transistors. Also for the P-channel transistor 710, there is no problem with the gate breakdown voltage because the gate voltage is 5V and the voltage applied to NWell is 10V. Since the amplitude of the voltage applied to the gates of N-channel transistors 720 and 730 is 3V, there is no problem with the gate breakdown voltage.

<Erase operation>
When data is erased, as shown in FIG. 14, VPP = 3V, VD3 = 3V, VD5 = 0V, VBBM = -5V, VDN = 0V, BIAS1 = VPP-Vthp (= 3V-Vthp), BIAS2 = VD5- Vthp (= 0V−Vthp = −Vthp), BIAS3 = −5V (= VBBM), BIAS4 = 0V, BIAS5 = VDN + Vthn (= 0V + Vthn = Vthn). In the case of a flash memory, data erasure is “batch erasure” in which data in all nonvolatile memory cells is erased at once. Therefore, in the nonvolatile memory of the present embodiment, when erasing data, it is necessary to select all the word lines WLi and apply an erase level voltage (-5 V in the present embodiment) to each word line WLi. is there.

  In this embodiment, an erase signal is given to each logic gate 380 of the main decoder 5000-p, and all the logic gates 380 are not selected (H level output). Then, the voltage at the node N11 of the first level shifter LS01 becomes H level (VD3 = 3V), and the voltage at the node N12 becomes L level (0V). At this time, 0 V is applied to the gates of the P-channel transistors 35 and 36 as the gate voltage. On the other hand, bias voltage BIAS5 applied to the gates of N channel transistors 33 and 34 is set to VDN (0 V) + Vthn. Therefore, the P-channel transistor 35 and the N-channel transistor 33 are turned on, the voltage at the node N9 is 3V, and the voltage at the node N7 is 0V. Since the voltage at the node N7 is 0V and VBBM = −5V, the N-channel transistor 32 is turned on, but the P-channel transistor 36 is turned off, and the voltage at the node N8 is −5V (= VBBM).

  In this operation example, the inverters 17 and 18 of the second level shifter LS02 operate between the voltage VDN (= 0V) and the voltage VBBM (= −5V). Since the input voltage of the inverter 17 is L level (−5V), the output of the inverter 17 (ie, the voltage at the node N5) is H level (0V), and the output of the inverter 18 (ie, the voltage at the node N6) is L. It becomes level (-5V). Therefore, the output of the inverter 24 becomes H level (0V), the output of the inverter 25 becomes L level (−5V), the voltage of the low potential side inversion logic signal ML becomes L level (−5V), and the low potential side logic. The voltage of the signal MLB becomes H level (0V).

  As described above, bias voltage BIAS4 applied to the gates of N channel transistors 15 and 16 at the time of erasing is 0V. Since the voltage of the source of the N-channel transistor 15 (that is, the node N5) is 0V, the N-channel transistor 15 is turned off. At this time, since both the P-channel transistors 11 and 13 are turned on, the voltages at the nodes N1 and N3 are both 3V (= VPP). On the other hand, since the voltage at the node N6 is −5V, the N-channel transistor 16 is turned on, and the voltage at the node N4 is −5V. Further, since the bias voltage BIAS2 (= VD5 (0 V in this operation example) −Vthp) is applied to the gate of the P-channel transistor 14, the voltage of the node N2 is maintained at 0 V by the P-channel transistor 14. That is, the output of the inverter 23 (high potential side logic signal MHB) becomes H level (3V). Therefore, in each of the selection switches 6000-pk, the P-channel transistor 710 and the N-channel transistor 720 are turned off, and the N-channel transistor 730 is turned on. As a result, all the word lines WLi are connected to the second low potential side power supply node, and the voltage becomes −5V. Note that the voltage of the signal lines F0 to F3 may be 0 V (non-selected) or 3 V (selected).

  Since a voltage of −5V is applied to all the word lines WLi in this way, if a voltage of 10V is applied to all the bit lines BITj, all the data lines, and Pwell, the data of all the nonvolatile memory cells are erased. (See FIG. 6).

<Read operation>
As shown in FIG. 14, when reading data, VPP = 3V, VD3 = 3V, VD5 = 0V, VBBM = 0V, VDN = 3V, BIAS1 = 3V, BIAS2 = 0V, BIAS3 = 3V, BIAS4 = 3V, BIAS5 = 3V (= VDN = VD3) + Vthn.

  As described above, when the address ADDA matches the predetermined address, the output of the logic gate 380 becomes L level (0V), the voltage of the node N11 becomes L level (0V), and the voltage of the node N12 becomes H level ( VD3 = 3V). In this operation example, VBBM = 0V and BIAS5 = 3V + Vthn are set as in the case of data writing. Therefore, the voltage at the node N7 becomes L level (0V), and the voltage at the node N8 becomes H level (3V).

  On the other hand, in the second level shifter LS02, the voltage applied to the sources of the P-channel transistors 19 and 20 is 3V (= VPP), and the bias voltage BIAS1 applied to the gate is also 3V. Both 19 and 20 are turned off. In this operation example, bias voltage BIAS4 = 3V is applied to the gates of N channel transistors 15 and 16, both N channel transistors 15 and 16 are turned on, and bias voltages are applied to the gates of N channel transistors 21 and 22, respectively. BIAS3 = 3V is applied, and both N-channel transistors 21 and 22 are also turned on. As a result, the voltage of the high potential side logic signal MHB is L level (0V), the voltage of the low potential side logic signal MLB is L level (0V), and the voltage of the low potential side inversion logic signal ML is H level (3V). become. That is, in this case, the second level shifter LS02 operates as a normal level shifter for 3V operation.

  The voltage of the high potential side logic signal MHB is L level (0V), the voltage of the low potential side logic signal MLB is L level (0V), and the voltage of the low potential side logic signal ML is H level (3V). P-channel transistor 710 and N-channel transistor 720 of switch 6000-pk are each turned on, and N-channel transistor 730 is turned off. Accordingly, the signal lines F0 to F3 selected by the sub-decoder 7000 are connected to the word line WLi as in the case of the read operation described above. When the address ADDA does not match the predetermined address, the voltage of the high potential side logic signal MHB is H level (3V), the voltage of the low potential side logic signal MLB is H level (3V), and the low potential side The voltage of the inverted logic signal ML becomes L level (0 V), the P-channel transistor 710 and the N-channel transistor 720 are turned off, and the N-channel transistor 730 is turned on. As a result, the voltages of all the word lines WLi become VBBM (= 0V).

<Configuration and Operation of Subdecoder 7000>
Next, the configuration of the sub-decoder 7000 will be described. The sub-decoder 7000 has one set of the decoder DEC01, the third level shifter LS03, and the buffer BUF01 shown in FIG. 15 for each of the signal lines Fk (k = 0 to 3), that is, a total of four sets. The decoder DEC01 includes a logic gate 64 and an inverter 63. Logic gate 64 is given address ADDB. When this address ADDB matches a predetermined address, the output of the logic gate 64 becomes L level (VSS = 0V), and when it does not match, it becomes H level (VD3 = 3V). As shown in FIG. 15, the output of the logic gate 64 is given to the third level shifter LS03 through the logic inversion by the inverter 63.

  As shown in FIG. 15, third level shifter LS03 includes P-channel transistors 51, 52, 53, 54, 59 and 60, N-channel transistors 55, 56, 61 and 62, and inverters 57 and 58. As apparent from the comparison between FIG. 15 and FIG. 13, the configuration of the third level shifter LS03 is similar to the configuration of the second level shifter LS02 of the main decoder 5000-p. More specifically, each of P channel transistors 51, 52, 53, 54, 59 and 60 corresponds to each of P channel transistors 11, 12, 13, 14, 19 and 20 of second level shifter LS02, and N channel Each of transistors 55, 56, 61, and 62 corresponds to each of N-channel transistors 15, 16, 21, and 22 of second level shifter LS02. Inverters 57 and 58 correspond to inverters 17 and 18 of second level shifter LS02. That is, the third level shifter LS03 is configured by removing the inverters 23, 24 and 25 from the second level shifter LS02. As shown in FIG. 15, in this embodiment, the voltage at the node N1 of the third level shifter LS03 is the high-potential side logic signal FHB, the voltage at the node N5 is the low-potential side logic signal FLB, and the voltage at the node N6 is The low potential side inversion logic signal FL is supplied to the buffer BUF01.

  The buffer BUF01 includes a CMOS switch composed of a P-channel transistor 650 and an N-channel transistor 660 and an N-channel transistor 670 on a high-potential side power supply node (hereinafter referred to as a third high-potential-side power supply node) and a low-potential side. A power supply node (node of voltage VSS) is inserted in series. The reason why the voltage of the high potential side power supply node of the buffer BUF01 is VWL while the voltage of the high potential side power supply node of the third level shifter LS03 is VPP is that writing (Program) and writing verification (Program Verify). This is because the voltage applied to the word line WLi needs to be variously changed in accordance with the operation contents when performing the operations of erasing (Erase) and erasing verification (Erase Verify).

  As shown in FIG. 15, the P-channel transistor 650 and the N-channel transistor 670 are single-side high withstand voltage structure transistors, and the N-channel transistor 660 is a double-side high withstand voltage structure transistor. The gate of the P channel transistor 650 is supplied with the high potential side logic signal FHB, the gate of the N channel transistor 660 is supplied with the low potential side logic signal FL, and the gate of the N channel transistor 670 is supplied with the low potential side logic signal FLB. It is done. A signal line Fk is connected to the common connection point of the CMOS switch and the drain of the N channel transistor 670 (that is, the common connection point of the drain of the P channel transistor 650 and the source of the N channel transistor 660 and the drain of the N channel transistor 670). Has been.

  In the present embodiment, by setting the voltages VPP, VWL, VD3, VSS, BIAS1 to BIAS4 as shown in FIG. 14, data writing to the nonvolatile memory cell, writing verification, reading, erasing, and erasing are performed. Validation is performed. For example, at the time of writing (Program), VPP = VWL = 10V, VD3 = 3V, VSS = 0V, BIAS1 = 10V-Vthp, BIAS2 = 5V-Vthp, BIAS3 = 0V, and BIAS4 = 3V are set. In this case, when the address ADDB coincides with a predetermined address, the voltage at the node N8 (input node of the inverter 57) becomes H level (3V), so that the voltage at the node N5 becomes L level (0V) and the node N6 Becomes the H level (3 V). That is, the low potential side logic signal FLB becomes L level (0V), and the low potential side inversion logic signal FL becomes H level (3V). The voltage at the node N3 is 0V, and the voltage at the node N1 (high potential side logic signal FHB) is at L level (5V). Therefore, the P-channel transistor 650 and the N-channel transistor 660 of the buffer BUF01 are turned on, and the N-channel transistor 670 is turned off. As a result, the voltage of the signal line Fk connected to the common connection point of the drain of the P-channel transistor 650, the source of the N-channel transistor 660, and the drain of the N-channel transistor 670 becomes H level (= VWL = 10V).

  On the other hand, when the address ADDB does not match the predetermined address, the voltage at the node N8 is at L level (0V), so the low potential side logic signal FLB is at H level (3V), and the low potential side inverted logic signal is FL becomes L level (0 V). Further, the high potential side logic signal FHB becomes H level (10 V). Therefore, the P-channel transistor 650 and the N-channel transistor 660 of the buffer BUF01 are turned off, and the N-channel transistor 670 is turned on. As a result, the voltage of the signal line Fk connected to the common connection point between the drain of the P-channel transistor 650 and the source of the N-channel transistor 660 and the drain of the N-channel transistor 670 becomes L level (VSS = 0 V). Note that in the program verification operation, the voltage VWL is changed to about 4 V to 5 V in this state, and thereby the state of the memory cell is confirmed.

  Next, an operation during reading (Read) will be described. Since the operation is almost the same during erasing and erasing verification, the case of reading will be described as a representative. When data is read from the nonvolatile memory cell, VPP = VWL = 3V, VD3 = 3V, VSS = 0V, BIAS1 = 3V, BIAS2 = 0V, BIAS3 = 3V, and BIAS4 = 3V are set. At this time, when the address ADDB matches a predetermined address, the voltage at the node N8 becomes 3V, the voltage at the node N5 becomes 0V, and the voltage at the node N6 becomes 3V. That is, the low potential side logic signal FLB becomes L level (0V), and the low potential side inversion logic signal FL becomes H level (3V). Further, the voltage of the node N3 becomes 0V, and the high potential side logic signal FHB also becomes L level (0V). Therefore, the P-channel transistor 650 and the N-channel transistor 660 of the buffer BUF01 are turned on, and the N-channel transistor 670 is turned off. As a result, the voltage of the signal line Fk connected to the common connection point between the drain of the P-channel transistor 650 and the source of the N-channel transistor 660 and the drain of the N-channel transistor 670 becomes H level (VWL = 3V).

  On the other hand, when the address ADDB does not match the predetermined address, the voltage at the node N8 is at the L level (0V), so the low potential side logic signal FLB is at the H level (3V) and the low potential side inversion logic signal FL. Becomes L level (0V). Further, the high potential side logic signal FHB becomes H level (3 V). Accordingly, the P-channel transistor 650 and the N-channel transistor 660 of the buffer BUF01 are turned off, the N-channel transistor 670 is turned on, and the voltage of the signal line Fk becomes the L level (0 V). The erase operation is exactly the same as the read operation. In the case of erasure, the operation of the main decoder 5000-p is also described. However, since all the main decoders 5000-p are not selected, the output of the sub decoder 7000 (voltage of the signal line Fk) may be 3V. Moreover, 0V may be sufficient. The erase verification is an operation for checking the erase state of the memory cell by setting the voltage VWL to an optimum value in the range of 0.8V to 2V in this state.

  As described above, in this embodiment, by switching the voltages VWL and VBBM applied to the row selection circuit, a row selection voltage (word line) for performing data writing, erasing, and reading (or verification) to the nonvolatile memory cell. A voltage VD applied to the gate of the N-channel floating gate transistor through WLi is generated.

<Configuration of voltage switching circuit>
As described above, data writing (Program) to each nonvolatile memory cell (N-channel floating gate transistor) constituting the nonvolatile memory cell array (see FIG. 7B) of the nonvolatile memory of the present embodiment, When erasing (Erase), verifying data (Verify), or reading data (Read), each of the drain voltage VD, source voltage VS, gate voltage VG, and Pwell voltage WELL of the N-channel floating gate transistor It is necessary to switch the voltages VD5, BIAS1 to 5, VBBM, VWELL, VWL, and voltage VCOL so that the voltage values shown in FIG. 6 are obtained. The voltage switching circuit of the present embodiment is for realizing the voltage switching.

  FIG. 16 is a diagram illustrating a configuration example of the voltage switching circuit of the present embodiment. As shown in FIG. 16, the voltage switching circuit includes a power supply circuit 1, a bias circuit 2, a VWL switching circuit 10, a VWELL switching circuit 20, a VCOL switching circuit 30, and a VBBM switching circuit 40.

  The power supply circuit 1 includes, for example, a power supply pump and a regulator (not shown in FIG. 16). The power supply circuit 1 has voltages VDDH, VD5, VD3, VSWL, and VBB by the action of the power supply pump and the regulator at the time of writing (Program), at the time of verification (Verify), at the time of erasing (Erase), and at the time of reading (Read) , BIASA, BIASB, BIASC, BIASD, and BIASE are generated at the voltage values shown in FIG.

  The bias circuit 2 reads five of the voltages VDDH, VD5, VD3, BIASA, BIASB, BIASC, BIASD, BIASE and the ground voltage VSS (0 V) generated by the power supply circuit 1 as a read signal READ, a write signal PROG, and an erase The signal ERS and the verification signal VFY are selected according to the signal value of each signal and output as BIAS1, BIAS2, BIAS3, BIAS4, and BIAS5. More specifically, at the time of writing (ie, PROG = H level (“1”), READ, ERS and VFY = L level (“0”)), the bias circuit 2 uses the voltage BIASA ( VDH (10V) −Vthp), bias voltage BIAS2 as voltage BIASB (5V−Vthp), bias voltage BIAS3 as ground voltage VSS (0V), bias voltage BIAS4 as voltage VD3 (3V), and bias voltage BIAS5 as voltage BIASC (3V + Vthn) is selected and output. The same applies at the time of verification (that is, VFY = H level (“1”), READ, PROG, and ERS = L level (“0”)). At the time of erasing (that is, ERS = H level (“1”), READ, PROG, and VFY = L level (“0”)), the voltage BIASD (Vthn) is selected and output as the bias voltage BIAS5. Different from writing and verification. At the time of reading (that is, READ = H level (“1”), PROG, ERS, and VFY = L level (“0”)), the bias circuit 2 uses the voltage VD3 as the bias voltages BIAS1, BIAS3, and BIAS4. The ground voltage VSS is selected as the bias voltage BIAS2, and the voltage BIASC (3V + Vthn) is selected and output as the bias voltage BIAS5.

  The VWL switching circuit 10 is a circuit that switches the voltage VWL supplied to the sub-decoder 7000 described above. The VWL switching circuit 10 includes voltages VDDH, VD5, VD3 and VSWL among voltages generated by the power supply circuit 1, voltages BIAS1, BIAS2, BIAS3 and BIAS4 output from the bias circuit 2, an enable signal SWEN, and a write signal. PROG and verification signal VFY are provided. The VWL switching circuit 10 selects any one of the voltages VDDH, VD3, and VSWL according to the voltages BIAS1, BIAS2, BIAS3, and BIAS4 and the signals SWEN, PROG, and VFY, and outputs the selected voltage as the voltage VWL.

  The VWELL switching circuit 20 is a circuit for switching the voltage VWELL (= voltage VS) shown in FIG. The VWELL switching circuit 20 is supplied with voltages VDDH and VD3 among the voltages generated by the power supply circuit 1, voltages BIAS1, BIAS2, BIAS3 and BIAS4 output from the bias circuit 2, an enable signal SWEN and an erase signal ERS. . The VWELL switching circuit 20 selects one of the voltages VDDH and VSS according to the voltages BIAS1, BIAS2, BIAS3, and BIAS4, and the signals ERS and SWEN, and outputs the selected voltage as the voltage VWELL.

  The VCOL switching circuit 30 is a circuit that switches the voltage VCOL applied to the second column decoder 4000-y described above. The VCOL switching circuit 30 is supplied with voltages VDDH, VD5 and VD3, voltages BIAS1, BIAS2, BIAS3 and BIAS4 output from the bias circuit 2 and signals SWEN, PROG and ERS among the voltages generated by the power supply circuit 1. It is done. The VCOL switching circuit 30 selects any one of the voltages VDDH, VD5, and VD3 according to the voltages BIAS1, BIAS2, BIAS3, and BIAS4 and the signals SWEN, PROG, and ERS, and uses the second column decoder 4000-y as the voltage VCOL. To give.

  The VBBM switching circuit 40 is a circuit that switches the voltage VBBM supplied to each of the main decoder 5000-p and the selection switch 6000-pk. The VBBM switching circuit 40 is supplied with voltages VD3 and VBB out of the voltages generated by the power supply circuit 1, the voltage BIAS5 output from the bias circuit 2, and signals SWEN and ERS. VBBM switching circuit 40 selects either voltage VSS or VBB in accordance with voltage BIAS5 and signals SWEN and ERS, and supplies the selected voltage to VBBM as main voltage 5000-p and selection means 6000-pk.

<Configuration of VWL switching circuit 10>
FIG. 18 is a diagram illustrating a configuration example of the VWL switching circuit 10. As shown in FIG. 18, the VWL switching circuit 10 includes a decoder DEC1, a level shifter LS3, a buffer BUF1, and a high breakdown voltage switch unit HVSW1. As apparent from a comparison between FIG. 18 and FIG. 15, the configuration of the level shifter LS3 is the same as the configuration of the third level shifter LS03 in FIG. The voltage appearing at the node N1 of the level shifter LS3 is applied as a signal PCT1 to the high breakdown voltage switch unit HVSW1.

  Decoder DEC1 includes inverters 63, 65 and 67 and logic gates 64, 66 and 68. As shown in FIG. 18, the inverter 63 is supplied with the voltage VD3 and the voltage VSS as power supply voltages, and the inverters 65 and 67 are supplied with the voltage VD5 and the voltage VSS as power supply voltages. Signals SWEN and PROG are applied to logic gate 64, and an output signal of logic gate 64 (a signal obtained by logically inverting the logical product signal of signals SWEN and PROG) is applied to inverter 63. The inverter 63 inverts the output signal of the logic gate 64 and outputs the result. Signals SWEN and VFY are applied to logic gate 68, and an output signal of logic gate 68 (a signal obtained by logically inverting the logical product signal of signals SWEN and VFY) is applied to inverter 67. Inverter 67 inverts the output signal of logic gate 68 and outputs the result. The logic gate 66 is supplied with the output signal of the logic gate 64 and the output signal of the logic gate 68, and the output signal of the logic gate 66 is supplied to the inverter 65. The inverter 65 inverts the output signal of the logic gate 66 and outputs it.

  The buffer BUF1 includes inverters 69, 70, 71 and 72. Each of inverters 69, 70, 71 and 72 is supplied with voltage VD5 and voltage VSS as power supply voltages. Inverters 69 and 70 are for buffering the output node N9 of the decoder DEC1. As shown in FIG. 18, the inverter 69 is connected to the output node N <b> 9 (the output node of the inverter 65), and the inverter 70 is connected to the output node of the inverter 69. The output voltage (output signal) of the inverter 70 is given to the high voltage switch part HVSW1 as the signal PCT2. Inverters 71 and 72 are for buffering the output node N10 of the decoder DEC1. As shown in FIG. 18, the inverter 71 is connected to the output node N <b> 10 (the output node of the inverter 67), and the inverter 72 is connected to the output node of the inverter 71. The output voltage (output signal) of the inverter 72 is given to the high voltage switch part HVSW1 as the signal PCT3.

  High breakdown voltage switch unit HVSW1 includes a P-channel transistor 73 and N-channel transistors 74 and 75. Each of the P-channel transistor 73 and the N-channel transistors 74 and 75 is a one-side high voltage structure transistor in which only the drain LDD region is expanded. As shown in FIG. 18, the voltage VDDH is applied to the Nwell in which the P-channel transistor 73 is formed, and the voltage VSS = 0V is applied to the Pwell in which the N-channel transistors 74 and 75 are formed.

As shown in FIG. 18, P channel transistor 73 and N channel transistor 75 are inserted in series between a power supply node to which voltage VDDH is applied and a power supply node to which voltage VSWL is applied. A signal PCT1 is applied to the gate of the P-channel transistor 73, and a signal PCT3 is applied to the gate of the N-channel transistor 75. N-channel transistor 74 has a drain connected to a common connection point CN1 between the drain of P-channel transistor 73 and the drain of N-channel transistor 75, and a source connected to a power supply node to which voltage VD3 is applied. Signal PCT2 is applied to the gate of N-channel transistor 74. As shown in FIG. 18, in this embodiment, the common connection point CN1 is an output node that outputs the voltage VWL.
The above is the configuration of the VWL switching circuit 10.

<Operation of VWL Switching Circuit 10 at Writing>
FIG. 19 is a diagram illustrating an operation voltage table of the VWL switching circuit 10. Hereinafter, the operation of the VWL switching circuit 10 will be described with reference to the operation voltage table shown in FIG.
First, the operation of the VWL switching circuit 10 at the time of writing (Program) will be described. As described above, at the time of writing, as shown in FIG. 19, the voltages VDDH = 10V, VD3 = 3V, and VD5 = 5V are applied from the power supply circuit 1 to the VWL switching circuit 10, and BIAS1 = 10V−Vthp, Each voltage of BIAS2 = 5V−Vthp, BIAS3 = 0V and BIAS4 = 3V is applied from the bias circuit 2 to the VWL switching circuit 10. At the time of writing, both the enable signal SWEN and the write signal PROG given to the VWL switching circuit 10 are at the H level, and the read signal READ, the verification signal VFY, and the erase signal ERS are all at the L level.

  The enable signal SWEN and the write signal PROG which are input signals to the logic gate 64 of the decoder DEC1 are both at the H level (“1”). Therefore, the output of logic gate 64 is at L level (0 V), and the output voltage of inverter 63 (that is, the voltage at node N8) is at H level (3 V). On the other hand, since the verification signal VFY is at L level (“0”), the output of the logic gate 68 is at H level (3 V). Therefore, the output of inverter 67 (that is, the voltage at node N10) is at L level (0 V). The logic gate 66 is supplied with an L level signal from the logic gate 64, and an H level signal is input from the logic gate 68. Therefore, the output of the logic gate 66 becomes H level, and the output voltage of the inverter 65 (That is, the voltage at the node N9) becomes L level (0 V).

  Since the voltage at the node N8 is at the H level (3V), the voltage at the node N5 of the level shifter LS3 is at the L level (0V), and the voltage at the node N6 is at the H level (3V). At this time, the output signal PCT1 of the level shifter LS3 becomes L level (5V), and the P-channel transistor 73 to which this signal PCT1 is applied to the gate is turned ON. The reason why the output signal PCT1 of the level shifter LS3 is 5V is that, in the level shifter LS3, the P-channel transistor 53 and the P-channel transistor 54 are clamped by BIAS2 (5V-Vthp) (for details, refer to the above description). (See the operation of the third level shifter LS03). On the other hand, since the voltages at nodes N9 and N10 are both at L level (0V), output signals PCT2 and PCT3 of buffer BUF1 are both at L level (0V). For this reason, both the N-channel transistors 74 and 75 of the high breakdown voltage switch unit HVSW1 are turned off.

  As described above, at the time of writing, the P-channel transistor 73 of the high breakdown voltage switch unit HVSW1 is turned ON and the N-channel transistors 74 and 75 are both turned OFF, so that the output voltage VWL of the high breakdown voltage switch unit HVSW1 is VDDH (10V). It becomes.

<Operation of VWL Switching Circuit 10 at Verification>
Next, the operation of the VWL switching circuit 10 at the time of verification will be described. At the time of verification, the voltage values of the voltages VDDH, VD3, VD5, BIAS1, BIAS2, BIAS3, and BIAS4 are the same as at the time of writing, the write signal PROG is at L level, and the verification signal VFY is at H level. The point is different from that at the time of writing (see FIG. 19).

  Since the write signal PROG is at the L level, the output of the logic gate 64 is at the H level (3 V), and the output voltage of the inverter 63 (that is, the voltage at the node N8) is at the L level (0 V). On the other hand, since both the verification signal VFY and the enable signal SWEN which are input signals to the logic gate 68 are at the H level, the output of the logic gate 68 is at the L level (3 V). Therefore, the output of inverter 67 (that is, the voltage at node N10) is at the H level (5V). Further, since the logic gate 66 is supplied with an H level signal from the logic gate 64 and an L level signal is input from the logic gate 68, the output of the logic gate 66 becomes H level, and the output voltage of the inverter 65 (That is, the voltage at the node N9) becomes L level (0 V).

  Since the voltage of the node N8 is L level (0V), the voltage of the node N5 of the level shifter LS3 is H level (3V), and the voltage of the node N6 is L level (0V). At this time, the output signal PCT1 of the level shifter LS3 becomes H level (10V), and the P channel transistor 73 is turned OFF. On the other hand, since the node N9 is at L level (0V), the signal PCT2 is at L level (0V), and since the node N10 is at H level (5V), the signal PCT3 is at H level (5V). For this reason, the N channel transistor 74 of the high breakdown voltage switch unit HVSW1 is turned OFF and the N channel transistor 75 is turned ON. Therefore, the output voltage VWL of the high withstand voltage switch unit HVSW1 is VSWL. For example, if the threshold voltage of the N-channel transistor 75 is about 0.2V, the output voltage VWL of the high breakdown voltage switch unit HVSW1 is 0.8V if the voltage VSWL is set to 1V. Therefore, if the voltage VSWL is varied in the range of 1V to 3V + Vthn, a voltage VWL of 0.8V to 3V is output.

<Operation of the VWL switching circuit 10 at the time of erasing or reading>
Next, the operation of the VWL switching circuit 10 at the time of erasing or reading will be described. At the time of erasing or reading, both the write signal PROG and the verification signal VFY are at the L level. When the enable signal SWEN is at the H level and both the write signal PROG and the verification signal VFY are at the L level, or when the enable signal SWEN is at the L level, the output signal and the logic gate of the logic gate 64 of the decoder DEC1 The output signals 68 are both at the H level. Therefore, both the output of inverter 63 (node N8) and the output of inverter 67 (node N10) are at L level (0 V). Further, the output of logic gate 66 becomes L level, and the output of inverter 65 (node N9) becomes H level (5V).

  Since the node N8 becomes L level, the output signal PCT1 of the level shifter LS3 becomes H level (10V), and the P-channel transistor 73 is turned OFF. Further, since the node N9 is at the H level (5V), the output signal PCT2 of the buffer BUF1 is at the H level (5V), and the N-channel transistor 74 of the high breakdown voltage switch unit HVSW1 is turned on. Since the node N10 is at L level (0V), the output signal PCT3 of the buffer BUF1 is at L level (0V), and the N-channel transistor 75 of the high breakdown voltage switch unit HVSW1 is turned off. For this reason, the output voltage VWL of the high breakdown voltage switch unit HVSW1 is VD3 (3V).

  As described above, according to the VWL switching circuit 10 of the present embodiment, switching of a high voltage of 10V / 0.8V / 3V necessary for row selection in the flash memory is realized by using a MOS transistor having a low gate breakdown voltage. Is possible.

<Configuration of VWELL switching circuit 20>
FIG. 20 is a diagram illustrating a configuration example of the VWELL switching circuit 20.
20, the same components as those in FIG. 18 are denoted by the same reference numerals. As apparent from the comparison between FIG. 20 and FIG. 18, the configuration of the VWELL switching circuit 20 is that a decoder DEC2 is provided instead of the decoder DEC1, a buffer BUF2 is provided instead of the buffer BUF1, and a high breakdown voltage is provided. The difference from the configuration of the VWL switching circuit 10 is that a high withstand voltage switch unit HVSW2 is provided instead of the switch unit HVSW1.

  The decoder DEC2 is configured by removing the logic gates 66 and 68 and the inverters 65 and 67 from the decoder DEC1. In addition, the signal ERS is applied to the logic gate 64 in place of the signal RROG, which is different from the decoder DEC1. The buffer BUF2 has a configuration in which the inverters 69 and 70 are removed from the buffer BUF1. In addition, the point that the inverter 71 is connected to the output node N5 of the inverter 57 of the level shifter LS3 is different from the buffer BUF1. As shown in FIG. 20, in the VWELL switching circuit 20, the voltage appearing at the node N1 of the level shifter LS3 is applied to the high voltage switch unit HVSW2 as the signal WCT1, and the voltage appearing at the node N5 of the level shifter LS3 is buffered by the buffer BUF2. Then, the signal WCT2 is supplied to the high breakdown voltage switch unit HVSW2.

The high withstand voltage switch unit HVSW2 includes a P-channel transistor 76 and an N-channel transistor 77. Each of the P-channel transistor 76 and the N-channel transistor 77 is a one-side high-breakdown-voltage transistor in which only the drain LDD region is expanded. As shown in FIG. 20, the voltage VDDH is applied to the Nwell in which the P channel transistor 76 is formed, and the voltage VSS is applied to the Pwell in which the N channel transistor 77 is formed. P-channel transistor 76 and N-channel transistor 77 are inserted in series between a power supply node to which voltage VDDH is applied and a power supply node to which voltage VSS is applied. Signal WCT1 is applied to the gate of P channel transistor 76, and signal WCT2 is applied to the gate of N channel transistor 77. As shown in FIG. 20, in this embodiment, a common connection point CN2 between the drain of the P-channel transistor 76 and the drain of the N-channel transistor 77 is an output node that outputs the voltage VWELL.
The above is the configuration of the VWELL switching circuit 20.

<Operation of VWELL switching circuit 20 during erasing>
FIG. 21 is a diagram illustrating an operating voltage table of the VWELL switching circuit 20. The operation of the VWELL switching circuit will be described below with reference to the operating voltage table shown in FIG.
First, the operation of the VWELL switching circuit 20 at the time of erasing (Erase) will be described. As described above, at the time of erasing, as shown in FIG. 21, VDDH = 10V and VD3 = 3V are supplied from the power supply circuit 1 to the VWELL switching circuit 20, and BIAS1 = 10V-Vthp, BIAS2 = 5V-Vthp , BIAS3 = 0V and BIAS4 = 3V are applied from the bias circuit 2 to the VWELL switching circuit 20. At the time of erasing, both the enable signal SWEN and the signal ERS applied to the VWELL switching circuit 20 are at the H level (“1”).

  Since both the signal SWEN and the signal ERS, which are input signals to the logic gate 64 of the decoder DEC2, are at the H level, the output of the logic gate 64 is at the L level, and the output of the inverter 63 (node N8) is at the H level (3V). Become. When the node N8 is at the H level (3V), the level shifter LS3 of the VWELL switching circuit 20 performs the same operation as the level shifter LS3 of the VWL switching circuit 10, and the signal WCT1 becomes the L level (5V). Since the signal WCT1 is at the L level, the P-channel transistor 76 of the high breakdown voltage switch unit HVSW2 is turned on. Further, since the node N8 is at the H level, the node N5 is at the L level (0V), and the signal WCT2 buffered by the buffer BUF2 is at the L level (0V). For this reason, the N-channel transistor 77 of the high breakdown voltage switch unit HVSW2 is turned off. Since the P-channel transistor 76 is turned on and the N-channel transistor 77 is turned off, the high withstand voltage switch unit HVSW2 outputs the voltage VDDH (10 V) as the voltage VWELL.

<Operation of VWELL switching circuit 20 other than at the time of erasing>
Next, the operation of the VWEL switching circuit 20 other than at the time of erasing (that is, at the time of writing, verification or reading) will be described. In this case, the enable signal SWEN is at the H level (“1”) and the signal ERS is at the L level. Therefore, the output (node N8) of the inverter 63 of the decoder DEC2 becomes L level (0 V). When the node N8 is at L level (0V), the level shifter LS3 of the VWELL switching circuit 20 performs the same operation as the level shifter LS3 of the VWL switching circuit 10, and the signal WCT1 becomes H level (10V). For this reason, the P-channel transistor 76 is turned off. Further, since the node N8 is at the L level, the node N5 is at the H level (3V), the signal WCT2 buffered by the buffer BUF2 is at the H level (3V), and the N-channel transistor 77 is turned on. Since the P-channel transistor 76 is turned OFF and the N-channel transistor 77 is turned ON, the high breakdown voltage switch unit HVSW2 outputs the voltage VSS (0 V) as the voltage VWELL. Note that when the signal SWEN is at the L level (“0”), the voltage VWELL is 0 V regardless of whether the signal ERS is at the H level or the L level.

  As described above, according to the VWELL switching circuit 20 of the present embodiment, switching of 0V / 10V with respect to the voltage applied to the source line (voltage applied to Pwell) in the flash memory is realized using the MOS transistor having a low gate breakdown voltage. It becomes possible.

<Configuration of VCOL switching circuit 30>
FIG. 22 is a diagram illustrating a configuration example of the VCOL switching circuit 30.
In FIG. 22, the same components as those in FIG. 18 are denoted by the same reference numerals. As apparent from comparison between FIG. 22 and FIG. 18, the configuration of the VCOL switching circuit 30 is that a decoder DEC3 is provided instead of the decoder DEC1, a buffer BUF3 is provided instead of the buffer BUF1, and a high breakdown voltage. The difference from the configuration of the VWL switching circuit 10 is that a high withstand voltage switch unit HVSW3 is provided instead of the switch unit HVSW1. The configuration of the decoder DEC3 is the same as that of the decoder DEC1, but the erase signal ERS is applied to the logic gate 64 in place of the write signal PROG, and the write signal PROG in place of the verification signal VFY is supplied to the logic gate 68. This is different from the decoder DEC1 of the VWL switching circuit 10.

  The buffer BUF3 has a configuration in which the inverter 72 is deleted from the buffer BUF1. As shown in FIG. 22, in this embodiment, the voltage appearing at the node N9 of the decode DEC3 is applied to the high voltage switch unit HVSW3 as the signal CCT2 through the buffering by the inverters 69 and 70, and the voltage appearing at the node N10 of the decode DEC3 is After being buffered by the inverter 71, the signal CCT3 is supplied to the high breakdown voltage switch unit HVSW3. Further, in the VCOL switching circuit 30, the voltage appearing at the node N1 of the level shifter LS3 is given as the signal CCT1 to the high withstand voltage switch unit HVSW3.

  High breakdown voltage switch unit HVSW3 includes P-channel transistors 79, 81 and 82 and N-channel transistor 80. P-channel transistors 79, 81 and 82 and N-channel transistor 80 are all transistors having a single-side high breakdown voltage structure in which only the drain LDD region is expanded. As shown in FIG. 22, a voltage VDDH is applied to the Nwell in which the P channel transistor 79 is formed, and a voltage VD5 is applied to the NWELL in which the P channel transistor 81 is formed. The NWELL on which the P-channel transistor 82 is formed is connected to the source of the P-channel transistor 82. On the other hand, the voltage VSS is applied to the Pwell in which the N-channel transistor 80 is formed.

P channel transistor 79 and N channel transistor 80 are inserted in series between a power supply node to which voltage VDDH is applied and a power supply node to which voltage VD3 is applied. Signal CCT1 is applied to the gate of P-channel transistor 79, and signal CCT2 is applied to the gate of N-channel transistor 80. P-channel transistor 81 and P-channel transistor 82 are inserted in series between a power supply node to which voltage VD5 is applied and a common connection point CN3 of the drain of P-channel transistor 79 and the drain of N-channel transistor 80. Signal CCT3 is applied to the gate of P channel transistor 81, and the gate of P channel transistor 82 is connected to node N4 of level shifter LS1. As shown in FIG. 22, in the present embodiment, the common connection point CN3 is an output node that outputs the voltage VCOL.
The above is the configuration of the VCOL switching circuit 30.

<Operation of VCOL switching circuit 30 during erasing>
FIG. 23 is a diagram illustrating an operating voltage table of the VCOL switching circuit 30. The operation of the VCOL switching circuit 30 will be described below with reference to the operating voltage table shown in FIG.
First, the operation of the VCOL switching circuit 30 at the time of erasing will be described. As described above, at the time of erasing, as shown in FIG. 23, VDDH = 10V, VD5 = 5V and VD3 = 3V are supplied from the power supply circuit 1 to the VCOL switching circuit 30, and BIAS1 = 10V−Vthp, BIAS2 = 5V-Vthp, BIAS3 = 0V, and BIAS4 = 3V are applied from the bias circuit 2 to the VCOL switching circuit 30. At the time of erasing, both the enable signal SWEN and the erasing signal ERS applied to the VCOL switching circuit 30 are at the H level (“1”), and the write signal PROG is at the L level (“0”). .

  Since the enable signal SWEN is at the H level and the erase signal ERS is also at the H level, the output of the logic gate 64 of the decoder DEC3 is at the L level, and the output of the inverter 63 (node N8) is at the H level (3V). Since the enable signal SWEN is at the H level and the write signal PROG is at the L level, the output of the logic gate 68 of the decoder DEC3 is at the H level, and the output of the inverter 67 (node N10) is at the L level (0 V). At this time, the output of the logic gate 66 of the decoder DEC3 becomes H level, and the output of the inverter 65 (node N9) becomes L level (0V).

  Since the node N8 is at the H level, the node N5 of the level shifter LS3 is at the L level (0V), the node N6 is at the H level (3V), and the output signal CCT1 of the level shifter LS3 is at the L level (5V). This is because, as described above, in the level shifter LS3, the P-channel transistors 53 and 54 are clamped by BIAS2 (5V-Vthp). Since the output signal CCT1 of the level shifter LS3 becomes L level (5V), the P-channel transistor 79 of the high breakdown voltage switch unit HVSW3 is turned on. Further, the node N4 of the level shifter LS3 becomes H level (10V), and the P-channel transistor 82 of the high breakdown voltage switch unit HVSW3 is turned OFF.

  Since both the node N9 and the node N10 are at the L level (0V), the output signal CCT2 of the buffer BUF3 is at the L level (0V), and the output signal CCT3 is at the H level (5V). For this reason, both the N-channel transistor 80 and the P-channel transistor 81 of the high breakdown voltage switch unit HVSW3 are turned OFF, and the output voltage VCOL of the high breakdown voltage switch unit HVSW3 is VDDH (10V). The back gate potential of the high breakdown voltage switch unit HVSW3 is connected to the VCOL side. By this connection, it is possible to suppress a leakage current when the P-channel transistor 82 is turned off.

<Operation of VCOL switching circuit 30 at the time of writing>
Next, the operation of the VCOL switching circuit 30 at the time of writing will be described. As shown in FIG. 23, at the time of writing, the enable signal SWEN is at the H level (“1”), the write signal PROG is also at the H level (“1”), and the erase signal ERS is at the L level (“0”). It has become. At this time, the node N8 is at L level (0V), the node N9 is also at L level (0V), and the node N10 is at H level (5V).

  Since the node N8 is at L level, the node N5 is at H level (3V), the node N6 is at L level (0V), the output signal CCT1 of the level shifter LS3 is at H level (10V), and the node N4 is at L level (5V) )become. Therefore, the P-channel transistor 79 is turned off and the P-channel transistor 82 is turned on. On the other hand, since the node N9 is at the L level, the output signal CCT2 of the buffer BUF3 is at the L level (0 V). Further, since the node N10 is at the H level, the output signal CCT3 of the buffer BUF3 becomes the L level (0 V). Therefore, the N-channel transistor 80 of the high breakdown voltage switch unit HVSW3 is turned off and the P-channel transistor 81 is turned on. For this reason, the output voltage VCOL of the high breakdown voltage switch unit HVSW3 is VD5 (5V).

<Operation of VCOL Switching Circuit 30 at Verification or Reading>
Next, the operation of the VCOL switching circuit 30 at the time of verification or reading will be described. At the time of verification or reading, both the write signal PROG and the erase signal ERS are at the L level. As shown in FIG. 22, when the enable signal SWEN is at H level and both the write signal PROG and the erase signal ERS are at L level, or when the enable signal SWEN is at L level, the node N8 is at L level (0V), and the node N9 is at The H level (5V) and the node N10 are at the L level (0V). As described above, when the node N8 is at L level, the output signal CCT1 of the level shifter LS3 is at H level (10V), the node N4 is at L level (5V), the P channel transistor 79 is turned off, and the P channel transistor 82 is turned off. Becomes ON. Further, since the node N9 is at the H level, the output signal CCT2 of the buffer BUF3 is at the H level (5V), and since the node N10 is at the L level (0V), the output signal CCT3 of the buffer BUF3 is at the H level (5V). become. For this reason, the N-channel transistor 80 of the high breakdown voltage switch unit HVSW3 is turned on, and the P-channel transistor 81 is turned off. Therefore, the output voltage VCOL of the high withstand voltage switch unit HVSW3 is VD3 (3V).

  Thus, according to the VCOL switching circuit 30 of the present embodiment, switching of 3V / 10V / 5V can be realized with respect to the voltage VCOL applied to the column selection circuit in the flash memory, using a MOS transistor having a low gate breakdown voltage.

<Configuration of VBBM switching circuit 40>
FIG. 24 is a diagram illustrating a configuration example of the VBBM switching circuit 40.
As shown in FIG. 24, the VBBM switching circuit 40 includes a logic gate 38, a level shifter LS2, a buffer BUF4, a high breakdown voltage switch unit HVSW4, and a switch unit SW1.

  Switch SW1 includes a logic gate 39, inverters 40 and 41, P-channel transistors 42 and 44, and N-channel transistors 43 and 45. As shown in FIG. 24, the voltage VD3 is applied to the NWELL in which the P-channel transistors 42 and 44 are formed, and the voltage VSS is applied to the PWELL in which the N-channel transistors 43 and 45 are formed. The logic gate 39 and the inverters 40 and 41 are supplied with the voltage VD3 and the voltage VSS as power supply voltages.

  The logic gate 39 is supplied with a signal SWEN and a signal ERS. The output node N13 of the logic gate 39 is connected to the inverter 40, and the output node N14 of the inverter 40 is connected to the inverter 41. The output node N14 of the inverter 40 is also connected to the gate of the P-channel transistor 42 and the gate of the N-channel transistor 45. P-channel transistor 42 and N-channel transistor 45 are inserted in series between a power supply node to which voltage VD3 is applied and a power supply node to which voltage VSS is applied. N channel transistor 43 is connected in parallel to P channel transistor 42, and P channel transistor 44 is connected in parallel to N channel transistor 45. The gate of the N channel transistor 43 and the gate of the P channel transistor 44 are connected to the output node of the inverter 41. As shown in FIG. 24, in this embodiment, a voltage appearing at a common connection point between the drain of the P-channel transistor 42 and the drain of the N-channel transistor 45 is applied to the buffer BUF4 as the voltage VDN.

  The output node of the logic gate 38 is connected to the input node N11 of the level shifter LS2 (more precisely, the input node N11 of the inverter 37 in the level shifter LS2). The logic gate 38 is supplied with the voltage VD3 and the voltage VSS as power supply voltages. The logic gate 38 receives the signal SWEN and the signal ERS and outputs a signal obtained by logically inverting the logical product of the signals SWEN and ERS.

  Level shifter LS2 includes P-channel transistors 35 and 36 and N-channel transistors 31, 32, 33, and 34 in addition to inverter 37 described above. In level shifter LS2, P channel transistor 35, N channel transistor 33 and N channel transistor 31 are inserted in series between input node N11 of inverter 37 and the power supply node to which voltage VBB is applied. A P-channel transistor 36, an N-channel transistor 34, and an N-channel transistor 32 are inserted in series between the output node N12 of the inverter 37 and the power supply node to which the voltage VBB is applied. Each gate of P channel transistors 35 and 36 is always supplied with 0 V as a bias voltage, and each gate of N channel transistors 33 and 34 is supplied with voltage BIAS5 (= VDN + Vthn).

  The source of the N channel transistor 33 is connected to the common connection node N7 of the drain of the N channel transistor 31 and the gate of the N channel transistor 32, and the source of the N channel transistor 34 is connected to the drain of the N channel transistor 32 and the N channel transistor. The gate 31 is connected to a common connection node N8. As shown in FIG. 24, the common connection node N8 is an output node of the level shifter LS2.

  The level shifter LS2 shown in FIG. 24 shifts the output signal of the logic gate 38, converts the voltage VBB (−5V) to a logic signal having the L level and the voltage VDN to the H level, and supplies the logic signal to the buffer BUF4. . Bias voltage BIAS5 is set to a voltage higher than voltage VDN by threshold voltage Vthn of N-channel transistors 33 and 34. For this reason, when the voltage of the node N7 to which the source is connected becomes higher than the voltage VDN, the N-channel transistor 33 becomes OFF because the gate-source voltage becomes lower than the threshold voltage Vthn. Further, when the voltage at the node N8 is to be higher than VDN, the N-channel transistor 34 is turned OFF because the gate-source voltage is lower than the threshold voltage Vthn. That is, when data is written or erased, the N-channel transistors 33 and 34 serve as separation means for separating the nodes from the high potential side so that the voltages at the nodes N7 and N8 do not exceed VDN. .

  The buffer BUF 4 includes an inverter 17 and an inverter 18. As shown in FIG. 24, the voltage VDN and the voltage VBB are supplied to the inverter 17 and the inverter 18 as power supply voltages. The inverter 17 is connected to the output node N8 of the level shifter LS2, and the output node NCT1 of the inverter 17 is connected to the inverter 18. The output node NCT1 is connected to the gate of the N channel transistor 47 included in the high breakdown voltage switch unit HVSW4. The output node NCT2 of the inverter 18 is connected to the gate of the P channel transistor 46 included in the high breakdown voltage switch unit HVSW4 and N The gate of the channel transistor 48 is connected.

The high breakdown voltage switch unit HVSW4 includes a P-channel transistor 46 and an N-channel transistor 48 inserted in series between a power supply node to which the voltage VSS is applied and a power supply node to which the voltage VBB is applied. The channel transistor 46 is connected in parallel. As shown in FIG. 24, the voltage VDN is applied to the NWELL in which the P channel transistor 46 is formed, and the voltage VBB is applied to the PWELL in which the N channel transistors 47 and 48 are formed. In the high breakdown voltage switch unit HVSW4, a common connection point CN4 of the drain of the P-channel transistor 46 and the drain of the N-channel transistor 48 serves as an output node, and a voltage appearing at the common connection point CN4 is output as the voltage VBBM. .
The above is the configuration of the VBBM switching circuit 40.

<Operation of VBBM switching circuit 40 at the time of erasing>
FIG. 25 is a diagram showing an operating voltage table of the VBBM switching circuit 40. In the following, the operation of the VBBM switching circuit 40 at the time of erasing will be described first by taking the case of VBB = −5V as an example. At the time of erasing, as shown in FIG. 25, the voltages VD3 = 3V and VBB = −5V are applied from the power supply circuit 1 to the VBBM switching circuit 40, and BIAS5 = Vthn is applied from the bias circuit 2 to the VBBM switching circuit 40. It is done. At the time of erasing, both the enable signal SWEN and the erasing signal ERS applied to the VBBM switching circuit 40 are at the H level (“1”).

  Since both the enable signal SWEN and the erase signal ERS are at the H level, the output (node N13) of the logic gate 39 of the switch unit SW1 is at the L level (0V), and the output of the inverter 40 (node N14) is at the H level (3V). In addition, the output of the inverter 41 (node N15) becomes L level (0 V). For this reason, the P-channel transistor 42 and the N-channel transistor 43 of the switch unit SW1 are turned off, and the P-channel transistor 44 and the N-channel transistor 45 are turned on. Therefore, the output voltage VDN of the switch unit SW1 is VSS (0V).

  When enable signal SWEN and erase signal ERS are both at the H level, the output of logic gate 38 (node N11) is also at the L level (0 V), and the output of inverter 37 (node N12) is at the H level (3 V). At this time, the node N8 of the level shifter LS2 becomes H level (0V), and the node N7 of the level shifter LS2 becomes L level (−5V). The reason why the node N8 is at the H level (0 V) is that the N channel transistor 34 is clamped at the voltage Vthn in the level shifter LS2 (for details, see the operation of the first level shifter LS01 described above). Since the voltage VDN = 0V and the voltage VBB = −5V, the output signal NCT1 of the inverter 17 of the buffer BUF4 is L level (−5V), and the output signal NCT2 of the inverter 18 is H level (0V).

  Since the signal NCT2 is at the H level, the P-channel transistor 46 of the high breakdown voltage switch unit HVSW4 is turned off and the N-channel transistor 48 is turned on. Further, since the signal NCT1 is at the L level, the N-channel transistor 47 of the high breakdown voltage switch unit HVSW4 is turned off. For this reason, the output voltage VBBM of the high withstand voltage switch unit HVSW4 is VBB (−5V). The same operation is performed when VBB is -2V, and the output voltage of VBBM is VBB (-2V).

<Operation of VBBM Switching Circuit 40 Other than During Erasure>
Next, the operation of the VBBM switching circuit 40 other than at the time of erasing will be described. As shown in FIG. 25, when not erasing (that is, at the time of writing, verifying, or reading), as shown in FIG. 25, the voltages VD3 = 3V and VBB = 0V are switched from the power supply circuit 1 to the VBBM. BIAS5 = 3V + Vthn is supplied from the bias circuit 2 to the VBBM switching circuit 40. Further, the enable signal SWEN = H level and the erase signal ERS = L level during writing or verification, and the enable signal SWEN = L level during reading.

  When the enable signal SWEN = H level and the erase signal ERS = L level, or when the enable signal SWEN = L level, the output (node N13) of the logic gate 39 of the switch unit SW1 is set to H level (3V), and the inverter 40 The output (node N14) becomes L level (0V), and the output (node N15) of the inverter 41 becomes H level (3V). Therefore, the P-channel transistor 42 and the N-channel transistor 43 of the switch unit SW1 are turned on, and the P-channel transistor 44 and the N-channel transistor 45 are turned off. Therefore, the output voltage VDN of the switch unit SW1 is VD3 (3V).

  When the enable signal SWEN = H level and the erase signal ERS = L level, or when the enable signal SWEN = L level, the output of the logic gate 38 (node N11) is also at H level (3V) and the output of the inverter 37 (node N12) ) Becomes L level (0V). Since the gates of N-channel transistors 33 and 34 of level shifter LS2 are clamped by BIAS5 (3V + Vthn), node N7 is at H level (3V) and node N8 is at L level (0V). At this time, since the voltage VDN = the voltage VD3 (3 V) and the voltage VBB = 0 V, the output signal NCT1 of the inverter 17 of the buffer BUF4 becomes H level (3 V), and the output signal NCT2 of the inverter 18 becomes L level (0 V). Become. For this reason, the P-channel transistor 46 and the N-channel transistor 47 of the high breakdown voltage switch unit HVSW4 are turned on, and the N-channel transistor 48 is turned off. Therefore, the output voltage of VBBM of the high breakdown voltage switch unit HVSW4 is VSS (0V).

  Thus, according to the VBBM switching circuit 40 of the present embodiment, switching between the ground voltage (0 V) and the negative voltage is realized for the voltage VBBM applied to the row selection circuit in the flash memory, using a MOS transistor having a low gate breakdown voltage. it can.

<Other embodiments>
Although the embodiments of the present invention have been described above, these embodiments may be modified as follows.
(1) The ON / OFF timings of the P-channel transistors 79, 81 and 82 and the N-channel transistor 80 in the high breakdown voltage switch unit HVSW3 of the VCOL switching circuit 30 may be adjusted independently. Specifically, as shown in FIG. 26, delay circuits DELAY1 and DELAY4 are connected in parallel to the node N8 of the decoder DEC3. The level shifter LS3 is connected to each of the delay circuits DELAY1 and DELAY4, and the voltage of the node N1 of the level shifter LS3 connected to the node N8 via the delay circuit DELAY1 is given to the high voltage switch unit HVSW3 as the signal CCT1. The voltage of the node N4 of the level shifter LS3 connected to the node N8 via DELAY4 is supplied to the high voltage switch part HVSW3. Further, the buffer BUF3 is connected to the node N9 via the delay circuit DELAY2, and the buffer BUF3 is connected to the node N10 via the delay circuit DELAY3. As a result, the ON / OFF timings of P-channel transistors 79, 81 and 82 and N-channel transistor 80 can be adjusted independently.

  For example, when VDDH (10 V) is connected to VCOL, when the node N8 becomes H level, the delay circuit DELAY1 sets the timing at which the node N8_D1 becomes H level to several tens nanoseconds to several hundred nanoseconds (N-channel transistor). 80, the time until the P-channel transistors 81 and 82 are turned OFF). Thereby, the timing at which the P-channel transistor 79 is turned on can be delayed, and the timing at which VDDH is connected to VCOL can be delayed. When VD3 (3V) is connected to VCOL, when the node N9 becomes H level, the delay circuit DELAY2 sets the timing at which the node N9_D2 becomes H level from several tens nanoseconds to several hundred nanoseconds (P channel transistor). Delay until 79, 81 and 82 are turned off). Thereby, the timing at which the N-channel transistor 80 is turned on can be delayed, and the timing at which VD3 is connected to VCOL can be delayed. In the example shown in FIG. 26, delay circuits are inserted between the decoder DEC3 and the level shifter LS3 and between the decoder DEC3 and the buffer BUF3. However, as shown in FIG. 27, between the level shifter LS3 and the high withstand voltage switch unit HVSW3, In addition, a delay circuit may be interposed between the buffer BUF3 and the high breakdown voltage switch unit HVSW3, and the ON / OFF timings of the P channel transistors 79, 81 and 82 and the N channel transistor 80 may be adjusted independently. The waveform of the voltage of each part of the VCOL switching circuit that can adjust the ON / OFF timing of the P-channel transistors 79, 81, and 82 and the N-channel transistor 80 according to the mode shown in FIG. 26 (or FIG. 27) is shown in FIG. Or it becomes like FIG. FIG. 28 is a diagram showing the waveform of the voltage of each part of the VCOL switching circuit when the voltage VCOL is switched from 3V → 10V → 3V. FIG. 29 is a VCOL switching circuit when the voltage VCOL is switched from 3V → 5V → 3V. It is a figure which shows the waveform of the voltage of each part.

(2) In the above embodiment, as the P-channel transistors 53, 54, 73, 76, 79, 81, and 82, transistors having a single-side high breakdown voltage structure are used to increase the breakdown voltage. A transistor having a structure may be used. Similarly, the N-channel transistors 55, 56, 74, 75, 77, and 80 may be transistors having a high voltage structure on both sides.

  DESCRIPTION OF SYMBOLS 1 ... Power supply circuit, 2 ... Bias circuit, 10 ... VWL switching circuit, 20 ... VWELL switching circuit, 30 ... VCOL switching circuit, 40 ... VBBM switching circuit, DEC1, DEC2, DEC3, DEC01 ... Decoder, LS3, LS2, LS01 ... Level shifter, BUF1, BUF2, BUF3, BUF4, BUF01 ... buffer, HVSW1, HVSW2, HVSW3, HVSW4 ... high withstand voltage switch part, SW1 ... switch part, 35, 36, 42, 44, 51, 52, 53, 54, 59, 60, 73, 76, 79, 81, 82 ... P-channel transistor, 31, 32, 33, 34, 43, 45, 55, 56, 61, 62, 74, 75, 77, 80 ... N-channel transistor, 17, 18, 37, 40, 41, 57, 58, 63, 65, 67, 9,70,71,72 ... inverter, 38,39,64,66,68 ... logic gate.

Claims (10)

Either the voltage of the first high-potential power supply node or the voltage of the low-potential power supply node is selected according to the signal value of the first operation instruction signal and is output as the first logic signal. Either one of the voltage of the second high-potential power supply node having a voltage higher than that of the power supply node or the voltage of the low-potential power supply node is selected according to the signal value of the second operation instruction signal and output as the second logic signal. In addition, the voltage of the second high-potential power supply node and the voltage of the low-potential power supply node are selected in accordance with the signal values of the first and second operation signals as the third logic signal. An output decoder;
Any one of a voltage of a third high potential power supply node that is equal to or higher than the second high potential power supply node, and a voltage intermediate between the voltage of the third high potential power supply node and the voltage of the low potential power supply node. A level shifter that selects the first logic signal according to the first logic signal and outputs it as a fourth logic signal;
A buffer for buffering the second logic signal and outputting it as a fifth logic signal, while buffering the third logic signal and outputting it as a sixth logic signal;
Unlike the voltage of the third high potential power supply node, the voltage of the first high potential power supply node, and the voltage of the first high potential power supply node, which are different from the voltage of the first high potential power supply node. Selecting means for selecting and outputting any one of them according to the fourth, fifth and sixth logic signals;
A voltage switching circuit comprising: The selecting means includes a P-channel transistor and a first N-channel transistor interposed in series between the third high-potential power node and the first high-potential power node, and a drain of the P-channel transistor And a drain connected to a common connection point of the drain of the first N-channel transistor, and a source is connected to a power supply node to which an intermediate voltage between the voltage of the first high potential power supply node and the voltage of the low potential power supply node is applied. A second N-channel transistor connected,
The fourth logic signal is applied to the gate of the P-channel transistor, the sixth logic signal is applied to the gate of the first N-channel transistor, and the gate of the second N-channel transistor is applied to the gate of the second N-channel transistor. 2. The voltage switching according to claim 1, wherein the fifth logic signal is supplied, and a common connection point between the drain of the P-channel transistor and the drain of the first N-channel transistor is an output node. circuit. The level shifter selects either the voltage of the third high potential power supply node or the voltage of the low potential power supply node according to the first logic signal and outputs it as a seventh logic signal;
The selecting means includes a first P-channel transistor and an N-channel transistor inserted in series between the third high-potential power node and the first high-potential power node, and the second high-potential node. Second and third P channel transistors interposed in series between a power supply node and a common connection point between the drains of the first P channel transistor and the N channel transistor;
The fourth logic signal is applied to the gate of the first P-channel transistor, the sixth logic signal is applied to the gate of the N-channel transistor, and the gate of the second P-channel transistor is applied to the gate of the second P-channel transistor. The fifth logic signal is supplied, the gate of the third P-channel transistor is supplied with the seventh logic signal, and a common connection point between the drains of the first P-channel transistor and the N-channel transistor The voltage switching circuit according to claim 1, wherein is an output node. The level shifter for outputting the fourth logic signal and the level shifter for outputting the seventh logic signal are separately provided, and
First to fourth delay circuits each capable of adjusting a delay amount, wherein a first logic signal output from the decoder is delayed and applied to a level shifter that outputs the fourth logic signal. Delay circuit, a second delay circuit that delays the first logic signal output from the decoder and applies it to a level shifter that outputs the seventh logic signal, and a second logic signal output from the decoder A third delay circuit that delays and supplies the buffer to the buffer, and a fourth delay circuit that delays and applies the third logic signal output from the decoder to the buffer;
The voltage switching circuit according to claim 3, further comprising: The level shifter for outputting the fourth logic signal and the level shifter for outputting the seventh logic signal are separately provided, and
First to fourth delay circuits each capable of adjusting a delay amount, and delaying the fourth logic signal output from the level shifter that outputs the fourth logic signal and supplying the delayed signal to the selection means A first delay circuit; a second delay circuit that delays the seventh logic signal output from the level shifter that outputs the seventh logic signal and applies the delayed signal to the selection means; and a second delay circuit that is output from the buffer. A third delay circuit that delays the logic signal of 5 and supplies the selection means to the selection means; and a fourth delay circuit that delays and applies the sixth logic signal output from the buffer to the selection means;
The voltage switching circuit according to claim 3, further comprising: A decoder that selects and outputs either the voltage of the first high-potential power supply node or the voltage of the low-potential power supply node according to the signal value of the operation instruction signal;
An intermediate voltage which is an intermediate voltage between the voltage of the second high potential power supply node and a voltage of the second high potential power supply node which is higher than the voltage of the first high potential power supply node. Is selected according to the output signal of the decoder and output as a first logic signal, and a level shifter that logically inverts the output signal of the decoder and outputs it as a second logic signal;
A buffer for buffering the second logic signal;
Based on the first logic signal and the second logic signal that has been buffered by the buffer, one of the voltage of the second high potential side power supply node and the voltage of the low potential side power supply node is selected. Selecting means for outputting,
A voltage switching circuit comprising:   The selection means includes a P-channel transistor and an N-channel transistor interposed in series between the first high-potential power supply node and the low-potential power supply node, and the gate of the P-channel transistor has the first channel 1 logic signal is applied to the gate of the N channel transistor, and a second logic signal that has been buffered by the buffer is applied to the gate of the N channel transistor, and a common connection point between the drain of the P channel transistor and the drain of the N channel transistor. The voltage switching circuit according to claim 6, wherein is an output node. A decoder that selects one of the voltage of the first high-potential power supply node and the voltage of the ground node according to the signal value of the operation instruction signal and outputs it as a first logic signal;
A switch unit that selects and outputs either the voltage of the first high-potential power supply node or the voltage of the ground node according to the signal value of the operation instruction signal;
An intermediate voltage, which is an intermediate voltage between the voltage of the first high-potential power supply node and the voltage of the negative potential node to which a negative voltage is applied, and the negative voltage are selected according to the first logic signal. A level shifter for outputting as a second logic signal;
A buffer that selects one of the output voltage of the switch unit and the negative voltage in accordance with the second logic signal and outputs it as a third logic signal, and outputs the other as a fourth logic signal; ,
Selection means for selecting and outputting either the voltage of the ground node or the negative voltage based on the third and fourth logic signals;
A voltage switching circuit comprising:   The selecting means is connected in parallel to the first P-channel transistor and a first P-channel transistor and a first N-channel transistor interposed in series between the ground node and the negative potential node. A second N-channel transistor, wherein the fourth logic signal is applied to the gate of the first P-channel transistor and the gate of the first N-channel transistor, and the second N-channel transistor The third logic signal is supplied to the gate of the first N-channel transistor, and a common connection point between the drain of the first P-channel transistor and the drain of the first N-channel transistor is an output node. Item 9. The voltage switching circuit according to Item 8. 10. The voltage switching circuit according to claim 8, wherein a withstand voltage relaxation operation of the buffer is performed by controlling an output voltage of the switch unit and a voltage of the negative potential node. 11.

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