JP2008269712A - Thin-film magnetic substance semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To supply a large bit line write current without reducing a size of a bit line driver while guaranteeing the pressure resistance of a memory cell transistor in a magnetic random access memory (MRAM). <P>SOLUTION: In a memory array 1, according to the voltage of a bit line BL during data writing, at least one of voltage levels of a word line WL, a source line SL, and a backgate line BGL is set to a voltage level so as to preventing application of a high voltage exceeding a pressure resistance on the coupled part or the gate insulating film of the select transistor of a memory cell MC. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a thin film magnetic semiconductor memory device that stores data according to the resistance value of a magnetoresistive element, and more particularly, to a current for writing data by setting the magnetization direction of the magnetoresistive element by a magnetic field induced by a current. The present invention relates to an induced magnetic field writing type thin film magnetic semiconductor memory device.

  The nonvolatile semiconductor memory device can store data in a nonvolatile manner, and is not required to supply power for data retention. One such nonvolatile semiconductor memory device is a flash memory. In this flash memory, a memory cell is composed of one stacked gate type transistor. Data is stored in the floating gate of the memory cell transistor according to the amount of accumulated charge. That is, the threshold voltage of the memory cell transistor differs depending on the amount of charge stored in the floating gate, and the threshold voltage of the memory cell transistor is associated with the stored data.

  In a flash memory, a memory cell is composed of one transistor, so that a memory device having a small memory area and a large storage capacity can be realized with a small memory cell array area. For recent storage devices, large storage capacity, low power consumption, miniaturization, and the like are required to improve system performance. In order to satisfy such a requirement, miniaturization of the memory cell transistor is one countermeasure. However, in the flash memory, a high voltage is required for writing and erasing, and the gate insulating film of the transistor cannot be thinned. Therefore, there is a limit in reducing the size of the memory cell transistor. In addition, as the gate insulating film is made thinner, the leakage current from the floating gate increases, resulting in a problem that data retention characteristics deteriorate.

  In order to solve the problems associated with the miniaturization of flash memory elements as described above, a magnetoresistive RAM (MRAM: Magnetic Random Access Memory) using a magnetoresistive element as a memory element is provided. It is being developed and put into practical use. The memory element of the MRAM includes a fixed layer whose magnetization direction is fixed, a free layer whose magnetization direction is set according to stored data, and a barrier layer between the fixed layer and the free layer. When the magnetization directions of the fixed layer and the free layer are parallel, the resistance value becomes small, and when the magnetization directions of the fixed layer and the free layer are antiparallel, the resistance value becomes high. Using such a magnetoresistance effect, the magnitude of the resistance value is associated with stored data.

  The memory cell includes a magnetoresistive element of a storage element and a selection transistor. These magnetoresistive elements and select transistors are connected in series between the bit line and the source line. At the time of data reading, the selection transistor is turned on to form a path for current to flow through the magnetoresistive element. The current flowing through the memory cell differs depending on the resistance value of the magnetoresistive element. Data is read by detecting this amount of current.

  The configuration of such an MRAM is described in, for example, Non-Patent Document 1 (T. Tsuji, et al., “A 1.2V 1 Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture”, in 2004 Symposium on VLSI Circuits, Digest of Technical. Papers, pp. 450-453, June 2004., Non-Patent Document 2 (TW Andre, et al., “A 4-Mb 0.18-μm 1T1MTJ Toggle MRAM with Balanced Three Input Sensing Scheme and Locally Mirrored Unidirectional Write Drivers,” in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.40, NO.1, January 2005.) and Patent Document 1 (US Pat. No. 6,545,906).

  In the MRAM described in Non-Patent Document 1 (Atsuji et al.) Described above, a storage element (magnetoresistance element) is disposed at each intersection of a write word line (digit line) and a bit line. On the other hand, for the read word line, the memory cell (select transistor) is arranged in a folded bit line structure corresponding to the intersection between the read word line and the bit line. At the time of data writing, a current is passed through a write word line and a bit line arranged orthogonal to each other. The magnetization direction of the free layer of the magnetoresistive element is set by the combined magnetic field induced by the write word line current and the bit line current. A write current flows through the write digit line in a fixed direction regardless of the logical value of the write data. On the other hand, for the bit line, the direction of the bit line write current is set according to the logical value of the write data.

  In this non-patent document 1, when memory cell data is read, a selected memory cell is connected to one bit line, and a dummy cell is connected to the other bit line. Data is read in units of 2-bit memory cells. The dummy cell includes a reference cell in a high resistance state and a reference cell in a low resistance state. The reference cell in the high resistance state and the reference cell in the low resistance state are coupled in parallel to the sense amplifier. By short-circuiting the reference node of the 2-bit sense amplifier, an average value of currents flowing through the reference cell in the high resistance state and the reference cell in the low resistance state is generated as the reference current. Using this reference current, the amount of current flowing through the memory cell is determined, and data is read.

  At the time of writing, this Non-Patent Document 1 uses the “distributed gate voltage control method” in order to generate a large bidirectional write current even under a low power supply voltage. In this distributed gate voltage control system, the bit line is precharged to the ground voltage level during standby. At the time of writing, the selected bit line is first precharged to the power supply voltage level. Next, a current is supplied to the write word line. This voltage application order prevents erroneous switching of the magnetization state of the selected memory cell due to the peak current during precharge of the selected bit line. Next, a current is passed through the bit line in a direction corresponding to the write data. When the bit line current flows, the gate voltage of the drive transistor that discharges the bit line is adjusted to adjust the magnitude of the bit line current.

  The aforementioned Patent Document 1 (US Pat. No. '906) discloses a basic configuration of a toggle MRAM. In the toggle MRAM disclosed in Patent Document 1, each magnetoresistive element included in a memory cell includes a multi-layered free layer and a fixed layer, and a tunnel barrier layer between the free layer and the fixed layer. Is done. Each of the free layer and the fixed layer includes a ferromagnetic layer that is antiferromagnetically coupled. An antiferromagnetic coupling spacer layer is disposed between the antiferromagnetically coupled ferromagnetic layers. The direction of the combined magnetic field of the ferromagnetic layer of the free layer coincides with the current-induced magnetic field of the digit line and the bit line. The magnetic field easy axis of the magnetoresistive element is arranged to form an angle of 45 ° with the write word line (digit line) and the bit line. The timing for supplying current to the write word line and the bit line is shifted so as to have an overlapping period. First, a current is passed through the write word line to rotate the magnetization direction of the free layer of the magnetoresistive element. In this case, the combined magnetization direction of the free layer coincides with the direction of the magnetic field induced by the write word line. Accordingly, the magnetization direction of the antiferromagnetically coupled ferromagnetic layer also rotates. Next, a current is further passed through the bit line while a current is passed through the write word line. This bit line current induced magnetic field further rotates the magnetic field of the free layer. At this time, the magnetization direction of each ferromagnetic layer of the free layer slightly exceeds the hard axis direction. Next, the write word line current is cut off, and the write current is allowed to flow only to the bit line. Thereby, the magnetization direction of the free layer further rotates, and the magnetization direction of each ferromagnetic layer approaches the easy magnetization axis direction beyond the hard magnetization axis. Thereafter, when the bit line current is cut off, the magnetization direction of the ferromagnetic layer reaches the stable easy axis direction.

  Therefore, when one write sequence for passing current to the write word line and the bit line is completed, the magnetization direction of the magnetoresistive element of this memory cell is rotated by 180 °. That is, the storage state of the memory cell is switched by passing a current through the write word line and the bit line in a fixed direction regardless of the logical value of the write data.

  In Patent Document 1, the easy axis is set in a direction that forms an angle of 45 ° with the write word line and the bit line. With this arrangement, even when the element is miniaturized, the writing selectivity of the memory cell is increased and the memory state of the memory cell in the half-selected state is prevented from changing.

  Non-Patent Document 2 (Andre paper) also discloses a toggle MRAM. In Non-Patent Document 2, a read word line and a read bit line are electrically separated from a write word line and a write bit line by a local wiring. This local wiring is arranged between the magnetoresistive element (MTJ element) of the memory cell and the write bit line. For a memory cell group having a plurality of memory cells, local wiring is used as a local read bit line, and the magnetoresistive elements of the memory cells in the group are connected to the local wiring. This local interconnection is coupled to a global read bit line via a group selection gate. The read bit line has a hierarchical structure of local and global read bit lines to reduce the load on the read bit line (global read bit line) during reading. Further, by providing a write path and a read path, a low voltage transistor is used as a read transistor (memory cell transistor, group selection transistor, etc.), and a high voltage is applied to the write bit line and write word line. To generate a write current.

  At the time of reading, the reference cells in the high resistance state and the low resistance state are short-circuited at the reference current input portion of the preamplifier. A mirror current that is ½ times the current flowing through these high-resistance elements and low-resistance elements is supplied to the selected bit line to read data. At the time of data writing, the mirror current of the reference current is supplied as a write current to the selected bit line using a current mirror circuit for writing. One write driver is provided for a plurality of columns.

In the toggle MRAM, the storage state of the memory cell is changed by passing a write current. Therefore, before writing data, it is determined whether the write data and the data stored in the selected memory cell have the same logical value, and data is written according to the determination result.
US Pat. No. 6,545,906 T. Tsuji, et al., “A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture”, in 2004 Symposium on VLSI Circuits, Digest of Technical Papers, pp.450-453, June 2004. TW Andre, et al., “A 4-Mb 0.18-μm 1T1MTJ Toggle MRAM with Balanced Three Input Sensing Scheme and Locally Mirrored Unidirectional Write Drivers,” in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.40, NO.1, January 2005.

  Data writing in the MRAM is performed by a magnetoresistive element of a memory cell by a magnetic field induced by currents flowing through digit lines (write word lines) and bit lines orthogonal to each other, as shown in the above-mentioned documents 1 to 3. The direction of magnetization of the (MTJ element or TMR element) is set.

  In order to switch the magnetization state, it is necessary to generate a magnetic field of a certain magnitude and apply it to the magnetoresistive element. Therefore, it is necessary to pass a current IBLwr required for writing to the bit line against the parasitic resistance Rp of the bit line. In this case, it is required to apply a voltage of IBLwr · Rp between both ends of the bit line. Supply of current / voltage to the bit line is performed by bit line drivers provided at both ends of the bit line. Consider a case where a low voltage / high speed transistor used as a memory cell transistor (select transistor) is used as a transistor constituting this bit line driver. The memory cell transistor has a power supply voltage Vdd of 1.2 V, a low breakdown voltage, and a threshold voltage is reduced to ensure high-speed operation.

  A transistor having the same configuration as the memory cell transistor is used for the bit line driver. In this case, the power supply of the bit line driver needs to be set to a voltage level comparable to that of the memory cell power supply. For this reason, in order to secure a sufficiently large bit line write current IBLwr, it is necessary to reduce the on-resistance of the transistor of the bit line driver, and it is necessary to increase the transistor size. In this case, the size of the bit line driver becomes large, and it becomes difficult to arrange the bit line driver corresponding to each bit line. Therefore, a high voltage / low speed transistor having a high withstand voltage and a high threshold voltage of power supply voltage Vdd = 3.3V is conventionally used as the transistor of this bit line driver. For example, consider a case where 2.4 V is applied to one end of a bit line to generate a bit line write current. In this case, 0 V is applied to the gate (read word line), back gate and source (source line) of the select transistor of the memory cell. The source line is a signal line to which the selection transistor of the memory cell is connected, and a current flows through the path of the bit line, the magnetoresistive element, the selection transistor and the source line at the time of reading. At the time of data writing, the memory cell selection transistor is non-conductive. However, at the time of data writing, if the resistance value of the magnetoresistive element is small, the bit line voltage is applied to the selection transistor of the memory cell. Therefore, the memory cell transistor needs to withstand a voltage of 2.4 V at one end of the bit line. When the withstand voltage of the memory cell transistor is insufficient, it is necessary to reduce the voltage (2.4 V) applied to the bit line. In this case, in order to secure the bit line write current, it is necessary to increase the size of the transistor of the bit line driver, which causes a problem that the layout area of the bit line driver increases.

  In Non-Patent Document 1, although a configuration in which writing is performed at high speed under a low power supply voltage is considered, no consideration is given to the problem of the breakdown voltage of the memory cell transistor when the bit line write current is supplied. Absent.

  Patent Document 1 merely shows a configuration in which the magnetization direction of a memory cell (magnetoresistance element) is rotated by a current-induced magnetic field of a write word line and a bit line. No consideration is given to the breakdown voltage of the selection transistor of the memory cell.

  The problem of withstand voltage when supplying the write current occurs when the magnetoresistive element is directly connected to the bit line. Therefore, as shown in FIG. 4 of Non-Patent Document 2, it is conceivable to separately provide a read bit line connected to the magnetoresistive element and a write bit line through which a write bit line current flows. However, in this configuration, the distance between the write bit line and the magnetoresistive element is increased. As a result, in order to apply a sufficiently large magnetic field to the magnetoresistive element, it is necessary to further increase the bit line write current, resulting in a problem that the size of the transistor of the bit line driver is further increased.

  Alternatively, it is conceivable to shorten the bit line and reduce the bit line parasitic resistance. However, in this case, the number of bit lines to which the memory cells are connected increases, and the number of bit line drivers increases accordingly. Accordingly, the chip area or module area increases, which is an obstacle to miniaturization.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film magnetic semiconductor memory device capable of supplying a sufficiently large bit line write current without increasing the layout area.

  Another object of the present invention is to provide a thin film magnetic semiconductor memory device capable of supplying a sufficiently large bit line write current without increasing the area occupied by the driver while ensuring a sufficient breakdown voltage of the memory cell selection transistor. Is to provide.

  In the thin film magnetic semiconductor memory device according to the present invention, the word line is divided into a plurality of blocks in the column direction, and at the time of data writing, the memory cell of the block closest to the end where the high voltage is applied to the selected bit line For the selection transistor, at least one voltage level of the source voltage, the gate voltage, and the back gate voltage is set to a voltage level with which a withstand voltage is guaranteed with respect to the voltage of the corresponding bit line.

  That is, a thin film magnetic semiconductor memory device according to an embodiment of the present invention includes a plurality of memory cells arranged in a matrix, a plurality of bit lines arranged corresponding to each memory cell column, and a memory cell row. And a source line arranged along one direction of the column. The memory cell includes a magnetoresistive memory element, a first electrode coupled to the magnetoresistive memory element, a second electrode coupled to a source line, a gate electrode coupled to a corresponding word line, a back electrode And a selection transistor having a gate. The plurality of word lines are divided into a plurality of blocks along the column direction in which the bit lines extend. In one embodiment of the present invention, the thin film magnetic semiconductor memory device further includes a plurality of first bit line drivers provided corresponding to the first ends of the bit lines, and a second bit line of each bit line. And a plurality of second bit line drivers arranged corresponding to the end portions of the first and second bit lines. When this first bit line driver is selected during data writing, it supplies a first voltage to the first end of the corresponding bit line. When selected during data writing, the second bit line driver supplies a second voltage lower than the first voltage to the second end of the corresponding bit line.

  The thin film magnetic semiconductor memory device according to the embodiment further includes a voltage control circuit for setting a voltage applied to the selection transistor of the memory cell at the time of data writing. The voltage control circuit maintains a voltage level difference between at least one of the gate electrode, the second electrode, and the back gate of the selection transistor of the memory cell and the corresponding bit line at a voltage level between the first and second voltages. As described above, at least one voltage of the back gate voltages of the selection transistors of the plurality of word lines, the plurality of source lines, and the plurality of memory cells is set.

  Preferably, the voltage control circuit adjusts the voltage level applied to each block according to the distance from the first end of the bit line.

  During data writing, the voltage applied to the selection transistor of the memory cell is adjusted. Therefore, even when a high voltage is applied to the first end of the bit line, the voltage applied to the gate insulating film or junction of the select transistor of each memory cell is set to a voltage level below the withstand voltage value. be able to. As a result, a high voltage can be applied to the bit line to supply a large bit line write current without increasing the size of the memory cell transistor or the bit line driver.

[Embodiment 1]
FIG. 1 schematically shows an overall configuration of a thin film magnetic semiconductor memory device according to the first embodiment of the present invention. In FIG. 1, a thin film magnetic semiconductor memory device (hereinafter referred to as MRAM) includes a memory cell array 1 in which memory cells MC are arranged in a matrix. In this memory cell array 1, bit lines BL are arranged corresponding to each column of memory cells MC. A digit line DL, a word line WL, and a source line SL are arranged corresponding to each row of memory cells MC.

  The memory cell MC includes a magnetoresistive element and a selection transistor, the configuration of which will be described in detail later. The selection transistor is formed of an N-channel MOS transistor (insulated gate field effect transistor). The voltage of the back gate (substrate region) of the selection transistor is controlled by the back gate line BGL in units of memory cells aligned in the row direction.

  The MRAM further includes a digit line selection drive circuit 2, a word line selection drive circuit 3, a source line selection drive circuit 4, and a back gate line selection drive circuit 5 as row related circuits.

  Digit line selection drive circuit 2 supplies current to digit line DL of the selected row in accordance with a row address signal (not shown) during data writing. The direction in which the digit line selection drive circuit 2 passes a current through the selection digit line DL is always constant regardless of the logical value of the write data.

  Word line selection drive circuit 3 drives word line WL in a selected row to a selected state in accordance with a row address signal (not shown) at the time of data reading. At the time of data writing, the word line selection drive circuit 3 also adjusts the voltage level of the word line according to the potential of the selected bit line.

  Source line selection drive circuit 4 sets the voltage level of the source line to a voltage level corresponding to the bit line voltage during data writing, and sets the source line to the ground voltage during data reading and standby.

  Back gate line selection drive circuit 5 sets the back gate of the selection transistor of the memory cell to a voltage level corresponding to the bit line voltage at the time of data writing, and the selection transistor of this memory cell at the time of standby and reading Set the back gate to the ground voltage level.

  The voltages adjusted by these drive circuits 3, 4 and 5 are voltage levels at which the voltage difference between the corresponding bit line and the corresponding word line, source line and back gate line does not exceed the breakdown voltage (cell power supply voltage) of the selection transistor. It is.

  The MRAM further includes a column decode circuit 6, bit line drive circuits 7L and 7R, a bit line precharge circuit 8, and a read column selection circuit 9 as column-related paths. Column decode circuit 6 decodes a column address signal (not shown) at the time of data writing / reading, and generates a column selection signal for selecting an addressed column.

  Bit line drive circuits 7L and 7R are arranged to face both sides of the bit line, and each includes a bit line driver arranged corresponding to each bit line. Bit line drive circuits 7L and 7R are arranged opposite to both sides of the bit line, and at the time of data writing, a write current is supplied to the selected column in a direction corresponding to the write data. The bit line driver corresponding to the non-selected column is set to the output high impedance state at the time of data writing. At the time of data reading, all the bit line drivers included in bit line drive circuits 7L and 7R are set to the output high impedance state.

  Bit line precharge circuit 8 sets all bit lines to an intermediate voltage level during data writing. Thereafter, the supply of the precharge voltage (intermediate voltage level) to the selected column is stopped, while the intermediate voltage is continuously supplied to the bit lines of the non-selected columns. Bit line precharge circuit 8 is set to an output high impedance state during a standby cycle and during data reading.

  Read column select circuit 9 couples the bit line of the selected column to an internal data line (not shown) in accordance with a column select signal from column decode circuit 6 during data read. At the time of data writing and in the standby cycle, read column selection circuit 9 is set to a non-conductive state.

  The MRAM further includes an input / output circuit 10 and a control circuit 11. The input / output circuit 10 inputs / outputs external data DQ. In data writing, input / output circuit 10 generates complementary internal write data D and / D in accordance with external write data DQ and transmits them to bit line drive circuits 7L and 7R (in FIG. 1, the data The transmission path is shown only for the bit line drive circuit 7R).

  At the time of data reading, the input / output circuit 10 supplies a constant current to the bit line selected by the read column selection circuit 9, and the internal read data and the external data according to whether the current flowing through the bit line is larger or smaller than the reference current. Generate output data.

  The control circuit 11 generates a necessary internal operation timing control signal in accordance with a command CMD indicating an external operation mode.

  For example, a 3.3V power supply voltage (peripheral power supply voltage) VDDH and a 1.2V power supply voltage (cell power supply voltage) VDDL are supplied to the MRAM from the outside. Peripheral power supply voltage VDDH is supplied to bit line drive circuits 7L and 7R, and cell power supply voltage VDDL is transmitted to other row-related circuits and bit line precharge circuit 8 (the transmission path of these power supply voltages is not shown) ).

  FIG. 2 is a diagram showing a configuration of the memory cell MC. In memory cell MC, magnetoresistive element (MTJ element or TMR element) VR and select transistor ST are connected in series between bit line BL and source line SL. One end (upper electrode) of the magnetoresistive element VR is connected to the bit line BL. The select transistor ST is connected between the other end (lower electrode) of the magnetoresistive element VR and the source line SL, and its gate is connected to the word line WL. The back gate (substrate region) of the selection transistor ST is also connected to the back gate line BGL.

  At the time of data writing, the magnetization direction of the free layer of the magnetoresistive element VR is set by the magnetic field induced by the current flowing through the digit line DL and the bit line BL, and accordingly, the resistance value is a value corresponding to the write data. Set to

  FIG. 3 is a diagram specifically showing a configuration of a main part of the MRAM shown in FIG. In FIG. 3, the memory cell array 1 is divided into two memory blocks 1L and 1R along the column direction (bit line extending direction). As bit lines, bit lines BL2n and BL2n + 1 are representatively shown. At least the substrate regions (well regions) of the memory blocks 1L and 1R are separated from each other, and the substrate voltage (back gate voltage) can be set individually.

  Memory block 1L includes digit lines DL0-DLM-1, word lines WL0-WLM-1, source lines SL0-SLM-1, and back gate lines BGL0-BGLM-1. Memory block 1R includes word lines WLM-WL2M, digit lines DLM-DL2M, source lines SLM-SL2M, and back gate lines BGLM-BGL2M.

  Word line selection drive circuit 3 includes word line drivers DWR0 to DWR2M provided for word lines WL0 to WL2M, respectively. These word line drivers DWR0 to DWR2M transmit one of cell power supply voltage VDDL (1.2V) and ground voltage (0V) to the corresponding word lines in accordance with word line selection signals WLB0 to WLB2M, respectively.

  Source line selection drive circuit 4 includes source line drivers DSR0-DSR2M provided corresponding to source lines SL0-SL2M, respectively. These source line drivers DSR0 to DSR2M set the voltage levels of the corresponding source lines to the cell power supply voltage (1.2V) or the ground voltage level in accordance with the source line selection signals SLB0 to SLB2M, respectively.

  The back gate line selection drive circuit 5 includes back gate line drivers DBG0 to DBG2M provided corresponding to the back gate lines BGL0 to BGL2M, respectively. These back gate line drivers DBG0-DBG2M respectively set the voltage level of the corresponding back gate line to the cell power supply voltage (1.2V) and the ground voltage (0V) during data writing in accordance with back gate line selection signals BGB0-BGB2M. )

  These word line drivers DBR0 to DBR2M, source line drivers DSR0 to DSR2M, and back gate line drivers DBG0 to DBG2M have an output drive stage including a P channel MOS transistor (insulated gate field effect transistor) and an N channel MOS transistor, respectively. It has a CMOS inverter. A more detailed configuration of these drivers will be described later.

  Bit line drive circuit 7L includes bit line drivers DBL2n and DBL2n + 1 provided corresponding to bit lines BL2n and BL2n + 1, respectively. Bit line drive circuit 7R also includes bit line drivers DBR2n and DBR2n + 1 provided corresponding to bit lines BL2n and BL2n + 1, respectively. Each of these bit line drivers has an output stage composed of a CMOS inverter. P channel MOS transistors of bit line driver DBL / DBR receive bit line drive control signals BLL / BLR at their gates, and N channel MOS transistors receive bit line drive control signals BLLB / BLRB at their gates.

  By arranging the bit line drivers DBL2n and DBL2n + 1 on both sides of the bit line so as to face the bit line drivers DBR2n and DBR2n + 1, the direction of current flow can be changed according to the write data. These bit line drivers DBL2n, DBL2n + 1, DBR2n and DBR2n + 1 receive the peripheral power supply voltage VDDH (3.3V) as a high-side power supply voltage.

  Bit line precharge circuit 8 includes precharge gates PG2n and PG2n + 1 provided corresponding to bit lines BL2n and BL2n + 1, respectively. Bit line precharge gates PG2n and PG2n + 1 are each formed of a P-channel MOS transistor, and when selected, transmits a cell power supply voltage (1.2V) to the corresponding bit line.

  Read column select circuit 9 includes read column select gates RG2n and RG2n + 1 provided corresponding to bit lines BL2n and BL2n + 1, respectively. These read column select gates RG2n and RG2n + 1 are selectively turned on in accordance with read column select signals CSR2n and CSR2n + 1, respectively, and couple the corresponding bit line to internal read data line LIO when turned on. The read column selection signal is generated at the time of data reading based on the column selection signal from column decode circuit 6 shown in FIG.

  Next, the operation of the MRAM shown in FIG. 3 will be described with reference to the timing chart shown in FIG. In FIG. 4, a read column selection signal CSLRx (x is arbitrary) is generically shown as a read column selection signal. Bit line BL2n is selected during writing. In reading, word line WLM + 1 is selected.

  Now, it is assumed that the unit parasitic resistance Rpu is distributed in the bit line BL (all bit lines are generically shown). It is assumed that bit line write line current IBLwr flows from bit line drive circuit 7L toward bit line drive circuit 7R. At the time of writing, in the bit line driver DBL2n, the P-channel MOS transistor is turned on and the N-channel MOS transistor is kept off. In bit line driver DBR2n, on the contrary, the PMOS transistor is off and the N-channel MOS transistor is on. The on-resistance of the P-channel MOS transistor is larger than the on-resistance of the N-channel MOS transistor. Accordingly, in the bit line BL2n, at the time of writing, a voltage of 2.4V is applied to the node N0 at one end (first end) by resistance voltage division, and the other end (second end) of the bit line. Suppose that node N2M is substantially equal to the voltage level of ground voltage (0V).

  In the standby state, bit line drive control signals BLLB2n + 1 and BLRB2n + 1 are both at the H level, and bit lines BL2n and BL2n + 1 are maintained at the ground voltage level. At this time, bit line drive control signals BLL2n and BLR2n are both at the H level, and the P-channel MOS transistor is in the off state.

  At time t1, the write cycle starts. Accordingly, precharge control signals UB2n and UB2n + 1 both attain an L level, and bit lines BL2n and BL2n + 1 are precharged to a voltage level of 1.2 V (cell power supply voltage level) by precharge gates PG2n and PG2n + 1, respectively.

  During this precharge operation, all of the bit line drive control signals BLRB2n, BLLB2n + 1 and BLRB2n + 1 are driven to the L level, and all the N channel MOS transistors in the bit line drivers DBL2n, DBL2n + 1, DBR2n and DBR2n + 1 are turned off (P channel MOS) The transistor is off). Thereby, each bit line is precharged to the memory cell power supply voltage (1.2 V) level.

  It is assumed that digit line DL0 is selected and writing to memory cell MC connected to node N0 of bit line BL2n is performed. At this time, since the node N0 of the bit line is set to the high voltage level at time t2, the word lines WL0 to WLM-1, the source lines SL0 to SLM-1, and the back gate lines BGL0 to BGLM-1 are set in the array block 1L. Are driven to the voltage level of the memory cell power supply voltage (1.2 V). The cell power supply voltage VDDL is at a voltage level lower than the voltage 2.4V transmitted from the bit line driver corresponding to the node N0 at one end of the bit line.

  On the other hand, in array block 1R, word line WLM-WL2M, source line SLM-SL2M, and back gate line BGM-BGL2M are maintained at the ground voltage level. Therefore, in this state, all the memory cells included in array blocks 1L and 1R have the same voltage level on the source line, back gate line and word line.

  At time t3, the precharge control signal UB2n rises to the H level, and the precharge operation of the precharge gate PG2n is completed. Precharge control signal UB2n + 1 is at the L level, and bit line BL2n + 1 is maintained at the cell power supply voltage level of 1.2V.

  At this time, the bit line drive control signal BL2n becomes L level, the P channel MOS transistor of the bit line driver DBL2n becomes conductive, the write voltage 2.4V is transmitted to the bit line BL2n, and the bit line write current IBLwr Flows. Due to the write current IBLwr, the voltage of the bit line BL2n sequentially decreases from the node N0 toward the node N2M according to the unit parasitic resistance Rpu. That is, in the bit line BL2n, the node N0 is 2.4V, and the intermediate nodes NM-1 and NM have the same intermediate voltage 1.2V. Node N2M (second end) is at the ground voltage level. The magnitude of the bit line write current IBLwr is determined by the combined resistance Rp of the unit parasitic resistance Rpu of the bit line BL2n and the voltage difference 2.4V. At time t3, a current also flows through digit line DL (not shown), and data is written into memory cell MC arranged corresponding to the intersection of digit line DL0 and bit line BL2n.

  At the time of writing, memory nodes 1 are divided into array blocks 1L and 1R by central nodes NM-1 and NM. Therefore, in the selected bit line BL2n, a maximum voltage of 1 or 2V is only applied to the selection transistor of the memory cell.

  At the time of writing, the non-selected bit line BL2n + 1 is maintained at a voltage level of 1.2V by the precharge gate PG2n + 1. Therefore, only a maximum voltage of 1.2 V is applied to the select transistor of memory cell MC connected to bit line BL2n + 1 (in array block 1R).

  Here, the reason why the non-selected bit line BL2n + 1 is maintained at the intermediate voltage level of 1.2V (the intermediate value of the voltage across the bit line) is as follows. That is, in the array block 1L, the word line, the source line, and the back gate are set to the cell power supply voltage (1.2V). When the non-selected bit line is maintained at the ground voltage level, the non-selected bit line functions as the source of the selection transistor ST of the memory cell, and is connected to the non-selected bit line and passes through the memory cell in the selected row. Current may flow. Accordingly, the back gate, source line, and word line voltages of the memory cells in the selected column are lowered, and the effect of suppressing the voltage applied to the selection transistors of the memory cells in the array block 1L may be hindered. In addition, current consumption during writing increases. In order to avoid this problem, the bit line BL2n + 1 of the non-selected column is maintained at an intermediate voltage (cell power supply voltage) level of 1.2V between the write voltages 2 and 4V of the bit line of the selected column.

  During this writing period, in the bit line BL2n, the voltage level of the node N0 is 2.4V, the voltage levels of the nodes NM-1 and NM are 1.2V of the intermediate voltage, and the farthest end node N2M The voltage level is approximately the ground voltage level. In unselected bit line BL2n + 1, nodes N0-N2M are all maintained at the 1.2V level. Therefore, the selection transistor of the memory cell has the gate and the source at the same voltage level and maintains the off state.

  When the data writing is completed at time t4, the bit line drive control signal BLL2n is driven to the H level, and the supply of the write current to the bit line 2n is finished. Further, the precharge control signal UB2n is driven to the L level, and a precharge current is supplied from the cell power supply node to the bit line BL2n by the precharge gate PG2n. At this time, bit line drive control signal BLR2n is driven to the L level to turn off the N channel MOS transistor of bit line driver DBR2n. Thereby, nodes N0-N2M of bit line BL2n are precharged to the cell power supply voltage level. The precharge of the bit line BL2n to the intermediate voltage level is performed for the following reason.

  That is, when writing is completed and bit line BL2n is discharged to the ground voltage level at time t4, in array block 1L, the voltage level of source line SL of the selection transistor of the memory cell is higher than the voltage level of bit line BL2n. Become. In this state, the source of the selection transistor ST is a bit line. There is a possibility that the word line is at a voltage level of 1.2 V, the selection transistor ST is turned on, current flows from the source lines SL0 to SLM to the bit line BL2n, and current consumption during writing increases. In order to suppress this discharge current, the bit line BL2n is temporarily set to a voltage application state similar to that of the non-selected bit line BL2n + 1.

  At time t5, the write cycle is completed, and word lines WL0-WLM-1, source lines SL0-SLM-1, and back gate lines BGL0-BGLM-1 are all driven to the ground voltage level. Further, precharge control signals GB2n and GB2n + 1 attain H level, and bit line drive control signals BLRB2n, BLLB2n, BLLB2n + 1 and BLRB2n + 1 are driven to H level. Thereby, bit lines BL2n and BL2n + 1 are precharged to the ground voltage level. When the write cycle is completed, the bit line is precharged to the ground voltage level and waits for the next access.

  In data reading, first, at time t6, bit line drive control signals BLRB2n, BLLB2n, BLLB2n + 1 and BLRB2n + 1 are set to L level in order to complete precharging of bit lines BL2n and BL2n + 1 to the ground voltage level. Bit line drive control signals BLL2n and BLL2n maintain the H level. Precharge control signals GB2n and GB2n + 1 are maintained at the H level.

  In this state, at time t7, according to column selection signal CSLRx, read column selection gate RGx (x is arbitrary) of the selected column is turned on, a read current is supplied to the selected bit line, and the voltage level of bit line BL2n is set to the read voltage. Set to level. For bit line BL2n + 1 of the non-selected column, read column select gate RG2n + 1 is non-conductive, and no read voltage / current is transmitted. In this state, word line WLM is driven to a selected state, a bit line current is detected by a sense amplifier included in the input / output circuit shown in FIG. 2, and data is read out.

  When the read cycle is completed at time t8, column selection signal CSLRx is driven to a non-selected state, and word line WLM is also driven to a non-selected state. At this time, the bit lines BL2n and BL2n + 1 are all precharged to the ground voltage level by the bit line drive circuit by the bit line drive control signal BLRB2n.

  FIG. 5 shows the relationship between the bit line voltage and the voltages of word line WL, back gate line BGL and source line SL during data writing in the first embodiment of the present invention. In FIG. 5, the horizontal axis indicates the node number on the bit line, and the vertical axis indicates the voltage. The voltage of the selected bit line sequentially decreases from 2.4V to 0V from the node N0 toward the node N2M. The voltage of the non-selected bit line is at a level of 1.2V (cell power supply voltage).

  At the nodes NM-1 and NM where the voltage of the selected bit line is equal to the voltage of the non-selected bit line, the voltage levels of the word line WL, the back gate line BGL and the source line SL are the intermediate voltage (cell power supply voltage). The voltage is switched from 1.2V to the ground voltage 0V. Therefore, the maximum voltage applied to the select transistor of the memory cell is 1.2V. On the other hand, when the word line WL, the back gate line BGL, and the source line SL are maintained at the ground voltage level at the time of data writing as in the prior art, a voltage of up to 2.4 V is applied to the selection transistor of the memory cell, The breakdown voltage cannot be guaranteed. By adjusting the voltage levels of the word line WL, the back gate line BGL, and the source line SL according to the voltage across the bit line, the voltage applied to the select transistor of the memory cell can be relaxed. That is, by adjusting the voltages of the source line, the word line, and the back gate line so that the difference from the voltage of the bit line during writing is equal to or lower than the breakdown voltage of the selection transistor of the memory cell, A sufficiently large bit line write current can be supplied by applying a voltage.

  In this manner, a bit line driver can be configured using high breakdown voltage and low speed transistors as in the conventional case. It is not necessary to increase the transistor size of the bit line driver, and an increase in chip area can be suppressed.

  FIG. 6 is a diagram schematically showing the voltage applied to the selection transistor of the memory cell MC in the array block 1L. In FIG. 6, select transistor ST of memory cell MC includes impurity regions 21a and 21b formed on the surface of substrate region (back gate) 20 and a substrate region between impurity regions 21a and 21b. And a word line 22 formed through a gate insulating film (not shown). Impurity region 21a is coupled to corresponding bit line BL via magnetoresistive element VR. Source line SL is coupled to impurity region 21b. Substrate region 20 is coupled to back gate line BGL. As an example, the substrate region 20 of the select transistor is electrically isolated from the select transistor of the memory cell in the adjacent row by the isolation regions 24a and 24b.

  In the array block 1L, a voltage between 2.4V and 1.2V is applied to the bit line BL. Therefore, a maximum voltage of 2.4 V is applied to impurity region 21a. The impurity power supply voltage of 1.2V is applied to the impurity region 21b through the source line SL, and the substrate region 20 is set to 1.2V through the back gate line BGL. 1.2V is applied to the gate 22 constituting the word line WL. Therefore, since impurity region 21b functions as a source in select transistor ST, select transistor ST has a gate-source voltage Vgs of 0 V and maintains a non-conductive state. The PN junction between the substrate region 20 and the impurity regions 21a and 21b is maintained in a non-conductive state by the built-in voltage. The voltage applied to the gate insulating film and the source / drain junction is 1.2 V or less, and the breakdown voltage is guaranteed.

  In the select transistor of the memory cell in the non-selected column, the bit line voltage is 1.2V. Therefore, the bit line, the word line, the source line and the back gate line are at the same voltage level, the breakdown voltage is guaranteed, and the selection transistor is maintained in the off state.

  FIG. 7 shows a voltage applied to memory cell MC in array block 1R during data writing. The selection transistor ST has the same structure as that of the selection transistor ST shown in FIG. 6, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  0V is applied to the impurity region 21b through the source line SL, and 0V is applied to the substrate region 20 through the back gate line BGL. 0V is applied to the gate 22 through the word line WL. The voltage of the bit line BL is 1.2V to 0V, and a maximum voltage of 1.2V is applied also to the impurity region 21a. Accordingly, also in this case, the impurity region 21b is the source in the selection transistor ST, the gate-source voltage Vgs is 0 V, and the selection transistor ST maintains the off state. Further, the voltage level of the impurity region 21a is equal to or higher than the voltage level of the substrate region 20, and conduction between the substrate region 20 and the impurity region 21a is prevented. Further, the substrate region 20 and the impurity region 21b are at the same potential, and the non-conducting state is maintained by the built-in voltage of the PN junction.

  In the non-selected column, the voltage of the bit line is 1.2V. Therefore, in the selection transistor of the memory cell in the non-selected column, the source line SL is the source, the selection transistor is kept off, and the applied voltage is 1.2 V or less, so that the withstand voltage of the selection transistor is guaranteed. The

  Therefore, by setting the voltage levels of the word line WL, the source line SL, and the back gate line BGL according to the bit line voltage, the selection transistor ST can be maintained in the off state while ensuring the withstand voltage. As a result, the bit line write current is shunted through the select transistor of the memory cell. Thus, a magnetic field can be generated by the bit line write current and reliably applied to the magnetoresistive element in accordance with the bit line write voltage.

  Note that, when current flows in the reverse direction to the bit lines, the applied voltages to the word lines WL, source lines SL, and back gate lines BGL in the array blocks 1R and 1L are set in reverse. Also in the bit line driver, the generated voltages of the bit line drive circuits 7L and 7R are set in reverse. In this case, the first end to which the high voltage of the bit line is applied is the bit line end closest to the output of the bit line drive circuit 1R, and the second end is the end closest to the bit line drive circuit 1L. Part.

  FIG. 8 schematically shows an example of the configuration of a portion related to column selection at the time of writing by control circuit 11 shown in FIG. In FIG. 8, the control circuit 11 includes a command decoder 30 that decodes an external command CMD, a falling delay circuit 31 that receives a write instruction signal (write enable signal) WE from each command decoder 30, and a delay circuit 32. And a one-shot pulse generation circuit 33. When the command CMD instructs data writing, the command decoder 30 asserts the write enable signal WE (drives to the H level). When command CMD designates the data read mode, command decoder 30 asserts read enable signal RE.

  The fall delay circuit 31 delays the fall (negation) of the write enable signal WE for a predetermined time to generate a write enable delay signal WED. Delay circuit 32 delays write enable signal WE for a predetermined time to generate delayed write enable signal WRX. Delayed write enable signal WRX determines the voltage drive timing of word line WL, back gate line BGL, and source line SL during data writing.

  The one-shot pulse generation circuit 33 generates a one-shot pulse signal WRP having a predetermined time width in response to the assertion of the write enable signal WE.

  Control circuit 11 further includes a gate circuit 34 that receives write enable signal WE and read enable signal RE from command decoder 30 and generates internal access operation activation signal ACT. When one of write enable signal WE and read enable signal RE is asserted, gate circuit 34 asserts internal access operation activation signal ACT. Internal access operation activation signal ACT from gate circuit 34 is applied to column decoder 36 included in column decode circuit 6 shown in FIG. The column decoder 36 is provided corresponding to each column of the memory cell array. When the internal access operation activation signal ACT is asserted, the column decoder 36 decodes a column address signal ADY given from the outside and generates a column selection signal CSLi. .

  The control circuit 11 further receives the write enable delay signal WED, the one-shot pulse signal WRP from the falling delay circuit 31, and the column selection signal CSLi from the column decoder 36, and receives the write column selection signal Yi (CSLWi: i is , An integer between 0 and the number of bit lines −1), and a gate circuit 38 that receives the write column selection signal Yi and the write enable delay signal WED and generates the precharge control signal UBi. including.

  When the write enable delay signal WED is asserted, the one-shot pulse signal WRP is in the negated state and the column selection signal CSLi is asserted, the gate circuit 37 asserts the write column selection signal Yi (drives to the selected state). To do).

  The gate circuit 38 negates the precharge control signal UBi and maintains it at the H level when the write enable delay signal WED is in the negated state or the write column selection signal Yi is in the asserted state. Precharge control signal UBi from gate circuit 38 is applied to precharge gate PGi provided for bit line BLi.

  The column selection signal CSLi from the column decoder 36 is generated for each column (bit line) in accordance with the column address signal ADY. Therefore, gate circuits 37 and 38 are provided for each bit line.

  FIG. 9 is a timing chart showing the operation of the control circuit 11 shown in FIG. The operation of the control circuit 11 shown in FIG. 8 will be described below with reference to FIG.

  First, when the write operation is designated by the command CMD, the command decoder 30 asserts the write enable signal WE. Accordingly, write enable delay signal WED from falling delay circuit 31 is asserted. The one-shot pulse signal WRP from the one-shot pulse generator 33 is also at the H level for a predetermined period. In accordance with the assertion of write enable signal WE, internal access operation activation signal ACT from gate circuit 34 is asserted. In response, column decoder 36 performs a decoding operation to assert column selection signal CSLi corresponding to the addressed column.

  While the one-shot pulse signal WRP is at the H level, the write column selection signal Yi from the gate circuit 37 is in the negated state (L level). Therefore, when the write enable delay signal WED from the rising delay circuit 31 is asserted, the precharge control signal UBi from the gate circuit 38 is asserted to become L level. In response, precharge gate PGi precharges corresponding bit line BLi to the level of power supply voltage VDDL (1.2 V).

  When the one-shot pulse signal WRP falls to the L level, the gate circuit 37 is enabled and the write column selection signal Yi is asserted according to the column selection signal CSLi. In response, precharge control signal UBi from gate circuit 38 is negated and goes to the H level. At this time, when the corresponding bit line BLi is a non-selected column, the write column selection signal Yi is maintained in a negated state, so that the precharge control signal UBi is maintained at the L level. Therefore, the bit line BLi of the non-selected column is maintained in a state precharged to the cell power supply voltage VDDL (1.2 V) level during data writing.

  When a predetermined time required for writing elapses, the write enable signal WE from the command decoder 30 is negated. Accordingly, column select signal CSLi from column decoder 36 is negated, and write column select signal Yi from gate circuit 37 is negated accordingly. At this time, since the write enable delay signal WED is still in the asserted state, the precharge control signal UBi from the gate circuit 38 becomes L level, the precharge gate PGi is activated, and the bit line BLi of the selected column is activated. Is precharged again.

  When the write enable delay signal WED is negated after a predetermined time has elapsed, the precharge control signal UBi from the gate circuit 38 becomes H level, the precharge gate PGi is disabled, and the bit line BLi is precharged. Stop.

  Delayed write enable signal WRX from delay circuit 32 is used to drive word line WL, source line SL, and back gate line BGL at the time of data writing. That is, word line WL, source line SL, and back gate line BGL are maintained at the intermediate voltage level or the ground voltage level in accordance with the assertion period of delayed write enable signal WRX and the write data.

  At the time of data reading, read enable signal RE from command decoder 30 is asserted, and internal access operation activation signal ACT from gate circuit 34 is asserted accordingly. When the corresponding bit line BLi is a selected column, the column selection signal CSLi from the column decoder 36 is asserted. However, the write enable delay signal WED is in a negated state. Therefore, the gate circuit 37 is disabled, and the write column selection signal Yi maintains the negated state. Further, since the write enable delay signal WED is in the negated state, the precharge control signal UBi from the gate circuit 38 is maintained at the H level, and the precharge gate PGi is maintained in the non-conductive state (disabled state). Is done. In this state, the bit line current is detected to read data.

  FIG. 10 shows an example of the configuration of bit line drivers DBLi and DBRi provided for bit line BLi. As described above, the bit line drivers DBLi and DBRi each include a CMOS inverter as a drive stage of the output unit. The CMOS inverter in the drive stage of the bit line driver DBLi includes a P channel MOS transistor PQL and an N channel MOS transistor NQL that drive the node N0 of the bit line BLi to the peripheral power supply voltage VDDH (3.3 V) or the ground voltage (0 V). Including. The CMOS inverter in the drive stage of bit line driver DBRi includes P and N channel MOS transistors PQR and NQR that drive node N2M of bit line BLi.

  P channel MOS transistors PQL and PQR supply current from peripheral power supply voltage VDDH to corresponding bit line BLi when conductive. N channel MOS transistors NQL and NQR couple bit line BLi to the ground node when conductive.

  Bit line driver DBLi further includes a gate circuit 40l for controlling the conduction of P channel MOS transistor PQL. Gate circuit 40l receives write column selection signal Yi and write data D and generates bit line drive control signal BLLi. Gate circuit 40l is, for example, a NAND gate, and drives bit line drive control signal BLLi to L level when write column select signal Yi is asserted and write data D is at H level. In the following description, it is assumed that node N0 of bit line BLi is set at a high potential and node N2M is set at the ground voltage level when write data D is at H level.

  Bit line driver DBLi further includes gate circuits 42l, 44l and 46l in order to control conduction of N channel MOS transistor NQL. Gate circuit 42l receives read enable signal RE and write enable delay signal WED, and when one of read enable signal RE or write enable delay signal WED attains H level, its output signal is set to L level. Gate circuit 44l receives write column selection signal Yi and complementary write data / D. When write column selection signal Yi and complementary write data / D are both at the H level, its output signal is set to H Drive to level. Gate circuit 46l drives bit line drive control signal BLLBi to H level when one of the output signals of gate circuits 42l and 44l is at H level.

  Similarly, bit line driver DBRi includes gate circuits 40r, 42r, 44r and 46r. Gate circuit 40r receives write column selection signal Yi and complementary write data / D, and when these write column selection signal Yi and complementary write data / D are both at the H level, bit line drive control is performed. Signal BLRi is driven to L level. Gate circuit 42r receives read enable signal RE and write enable delay signal WED, and when one of these signals is at H level, it drives its output signal to L level. Gate circuit 44r receives write column selection signal Yi and write data D, and drives the output signal to H level when both write column selection signal Yi and write data D are at H level. Gate circuit 46r drives bit line drive control signal BLRBi to H level when one of the output signals of gate circuits 42r and 44r is at H level.

  As shown in FIG. 10, the logical values of applied write data D and / D are inverted for bit line drivers DBLi and DBRi. Thereby, in bit line BLi, write current IBLwr can be passed between node N0 and node N2M in a direction corresponding to the logical value of write data D. In the configuration shown in FIG. 10, when write data D is at H level, bit line write current IBLwr flows from node N0 toward N2M. When write data D is at L level, write bit line current IBLwr flows from node N2M toward node N0.

  FIG. 11 shows operations of bit line drivers DBLi and DBRi shown in FIG. FIG. 11 shows an operation when write data D is at H level. The operation of the bit line driver shown in FIG. 10 will be described below with reference to FIG.

  In the standby state, both write enable signal WE and read enable signal RE are at L level, and write column selection signal Yi is also at L level. Therefore, bit line drive control signals BLLi and BLRi from gate circuits 40l and 40r are both at the H level, and MOS transistors PQL and PQR are off. On the other hand, the output signals of gate circuits 42l and 42r are at the H level, and accordingly the output signals of gate circuits 46l and 46r are at the H level. Therefore, in this state, bit line BLi is maintained at the ground voltage level by MOS transistors NQL and NQR.

  When the write cycle starts, first, the write enable signal WE is asserted from the command decoder 30 shown in FIG. 8 and becomes H level, and the write enable delay signal WED from the falling delay circuit 31 shown in FIG. Asserted. At this time, the write data D is also set to the H level according to the logical value. When write enable delay signal WED is asserted, the output signals of gate circuits 42l and 42r become L level, and the output signals of gate circuits 46l and 46r also become L level. Accordingly, MOS transistors NQL and NQR are turned off, and bit line BLi is isolated from the ground node and the peripheral power supply node. The write column selection signal Yi is still in a non-selected state.

  During this period, the precharge gate PGi shown in FIG. 8 precharges the bit line BLi to the cell power supply voltage VDDL (1.2 V) level of the intermediate voltage level in accordance with the precharge control signal UBi.

  When this bit line precharge period is completed, the write column selection signal Yi is asserted. In bit line driver DBLi, since write data D is at H level, bit line drive control signal BLLi from gate circuit 401 is driven to L level, and P channel MOS transistor PQL is turned on. The output signal of gate circuit 44l is at L level, and bit line drive control signal BLLBi from gate circuit 46l is at L level. Accordingly, MOS transistor NQL is in an off state.

  On the other hand, in bit line driver DBRi, bit line drive control signal BLLBi output from gate circuit 40r maintains the H level since complementary write data / D is at the L level. In response to assertion of write column selection signal Yi, gate circuit 44r sets its output signal to H level, and accordingly, bit line drive control signal BLRBi from gate circuit 46r is set to H level. In response, MOS transistor NQR is turned on, and node N2M is coupled to the ground node.

  Therefore, in this state, MOS transistors PQL and NQR are on, MOS transistors PQR and NQL are off, and bit line write current IBLwr flows from node N0 toward node N2M.

  When the write cycle is completed, first, the write enable WE is negated, and accordingly, the write column selection signal Yi is negated through the column selection signal CSLi from the column decoder 36 shown in FIG. When write column selection signal Yi is negated, bit line drive control signal BLLi from gate circuit 42l is driven to H level in bit line driver DBLi, and MOS transistor PQL is turned off. At this time, since the write enable delay signal WED is still at the H level, the output signal of the gate circuit 42l is at the L level. Therefore, even if the output signal of gate circuit 44l becomes L level, bit line drive control signal BLLBi maintains L level.

  In the bit line driver DBRi, when the write column selection signal Yi is negated, the output signal of the gate circuit 44r becomes L level, and accordingly, the bit line drive control signal BLRBi from the gate circuit 46r becomes L level. When bit line BLi is separated from the peripheral power supply node and the ground node, as shown in FIGS. 8 and 9, bit line BLi is precharged again to cell power supply voltage VDDL level by precharge gate PGi. .

  Thereafter, when write enable delay signal WED is negated, the output signals of gate circuits 42l and 42r become H level, and accordingly, bit line drive control signals BLLBi and BLRBi become H level. As a result, bit line BLi is again coupled to the ground node and precharged to the ground voltage level.

  The write column selection signal Yj for the non-selected column is at the L level during this write operation. Therefore, bit line drive control signals BLLj and BLRj maintain the H level. Bit line drive control signals BLLBj and BLRBj are driven to L level and H level according to write enable delay signal WED.

  When write data D is at L level, the operations of bit line drivers DBLi and DBRi described above are reversed, and write current IBLwr flows from node N2M toward node N0.

  In a read cycle in which data is read, read enable signal RE is asserted by command decoder 30 shown in FIG. Write column selection signals Yi and Yj are at L level when data is read. Therefore, in accordance with the assertion of read enable signal RE, the output signals of gate circuits 42l and 42r become L level, and the output signals of gate circuits 46l and 46r accordingly become L level. Therefore, MOS transistors NQL and NQR are set to an off state. In this state, the read column selection gate (not shown in FIG. 10) is turned on, and the read current (the upper limit value is limited by the output sense amplifier circuit included in the input / output circuit) for this bit line BLi. ) To set a predetermined voltage level (this read path is not shown).

  As described above, bit line drivers DBLi and DBRi precharge bit line BLi to the ground voltage level in the standby state, and cause the bit line current to flow in the direction corresponding to the logical value of the write data during the write operation. In the read cycle, the bit line driver output high impedance state is set.

  FIG. 12 shows an example of a configuration of a portion related to row selection of MRAM according to the first embodiment of the present invention. FIG. 12 representatively shows word line driver DWRi for word line WLi, source line driver DSRi for source line SLi, back gate driver DBGi for back gate line BGLi, and digit line driver DDLi for digit line DLi.

  Word line driver DWRi receives write data D and gate circuit 50 receiving delayed write enable signal WRX from delay circuit 32 shown in FIG. 8, and gate circuit 52 receiving row select signal Xi and delayed read enable signal REX. And a gate circuit 54 for receiving the output signals of these gate circuits 50 and 52. Delayed read enable signal REX is generated from delay circuit 55 that receives read enable signal RE. Delay circuit 55 is provided in common to each word line driver, and delays read enable signal RE for a predetermined time to generate delayed read enable signal REX. This delayed read enable signal REX is generated in order to set the bit line precharged to the ground voltage to the floating state at the start of the read cycle.

  Gate circuit 50 outputs a signal at H level when write data D and delayed write enable signal WRX are both at H level. The word line driver WLi shows a configuration of a portion provided for the array block 1L. Instead of write data D, complementary write data / D is applied to the word line driver provided for array block 1R.

  Gate circuit 52 outputs a signal at H level when both row selection signal Xi and delayed read enable signal REX are at H level. Gate circuit 54 outputs a signal at H level when the output signals of gate circuits 50 and 52 are both at L level.

  The word line driver DWRi further includes a P channel MOS transistor PQw for driving the word line WLi to the cell power supply voltage VDD level and an output signal of the gate circuit 54 at the H level when the output signal of the gate circuit 54 is at the L level. N channel MOS transistor NQw which is conductive at the time of driving word line WLi to the ground voltage level is included.

  The source line driver DSRi receives the write data D and the delayed write enable signal WRX, and P drives the source line SLi to the cell power supply voltage VDD level when the output signal of the gate circuit 56 is at the L level. Channel MOS transistor PQs and N channel MOS transistor NQs for discharging source line SLi to the ground voltage level when the output signal of gate circuit 56 is at the H level are included. Gate circuit 56 outputs an L level signal when both write data D and delayed write enable signal WRX are at an H level.

  Back gate line driver DBGi has a P channel MOS transistor PQb that couples back gate line BGLi to cell power supply node VDDL when an output signal of gate circuit 56 is at an L level, and an output signal of gate circuit 56 is at an H level. Includes an N channel MOS transistor NQb coupling back gate line BGLi to the ground node.

  Here, a configuration in which the gate circuit 56 is provided in common to the source line driver DSRi and the back gate line driver DBGi is shown as an example. However, the gate circuit 56 may be provided in each of the source line driver DSRi and the back gate line driver DBGi.

  When source line driver DSRi and back gate line driver DBGi are provided for array block 1R, complementary write data / D is applied instead of write data D.

  Digit line driver DDLi includes a gate circuit 58 that receives delayed write enable signal WRX and row selection signal Xi, and a P-channel MOS that couples digit line DLi to cell power supply node VDDL when the output signal of gate circuit 58 is at L level. Transistor PQd and an N channel MOS transistor NQd for coupling digit line DLi to the ground node when the output signal of gate circuit 58 is at the H level are included. The other end of digit line DLi is coupled to a ground node.

  Gate circuit 58 outputs a signal at L level when delayed write enable signal WRX and row selection signal Xi are both at H level. FIG. 13 is a timing chart showing the operation of the portion related to the row selection shown in FIG. The operation of the circuit shown in FIG. 12 will be described below with reference to FIG.

  In the standby state, delayed write enable signal WRX, row selection signal Xi, and read enable signal RE are all at the L level of the negated state. In this state, the output signal of gate circuit 54 of word line driver DWRi is at the H level, and word line WLi is maintained at the ground voltage level by MOS transistor NQw. Similarly, in source line driver DSRi, the output signal of gate circuit 56 is at the H level, and source line SLi is maintained at the ground voltage level by MOS transistor NQs. The back gate line BGLi is also maintained at the ground voltage level by the MOS transistor NQb. In digit line driver DDLi, the output signal of gate circuit 58 is at H level, and digit line DLi is similarly maintained at the ground voltage level.

  When the write cycle starts, the write enable signal WE is asserted (by the command decoder 30 in FIG. 8), and accordingly, the delayed write enable signal WRX from the delay circuit 32 shown in FIG. 8 is asserted. At this time, the write data D is in a definite state according to the write enable signal WE. When delayed write enable signal WRX and write data D both attain an H level, in word line driver DWRi, the output signal of gate circuit 50 attains an H level, and accordingly, the output signal of gate circuit 54 attains an L level. Accordingly, word line WLi is driven to cell power supply voltage VDDL level by MOS transistor PQw. Also in the source line SLi, the output signal of the gate circuit 56 of the source line driver DSRi becomes L level, and the source line SLi is driven to the cell power supply voltage VDDL level by the MOS transistor PQs. Similarly to the source line SLi, the voltage level of the back gate line BGLi is driven to the cell power supply voltage VDDL level.

  On the other hand, in digit line driver DDLi, when row selection signal Xi is asserted, the output signal of gate circuit 58 attains L level, and current is supplied from the cell power supply node via MOS transistor PQd.

  When the data writing is completed, the write enable signal WE is first negated, and accordingly, the delayed write enable signal WRX from the delay circuit 32 shown in FIG. 8 is negated. In the word line driver DWRi, since the output signal of the gate circuit 50 becomes L level, and the output signal of the gate circuit 52 is L level at this time, the output signal of the gate circuit 54 becomes H level, and the word line WLi is at the ground voltage level. Is discharged.

  In source line driver DSRi, in accordance with the negation of delayed write enable signal WRX, the output signal of gate circuit 56 attains an H level, and source line SLi is discharged to the ground voltage level. The back gate line BGLi is also discharged to the ground voltage level by the MOS transistor NQb.

  Also in digit line driver DDLi, the output signal of gate circuit 58 is at H level, MOS transistor NQd is turned on, and digit line DLi is maintained at the ground voltage level.

  When write data D is at L level, in word line driver DWRi, the output signal of gate circuit 54 is maintained at H level, and word line WLi is maintained at the ground voltage level. The source line SLi and the back gate line BGLi are also maintained at the ground voltage level because the output signal of the gate circuit 56 is at the H level.

  At the time of data reading, the read enable signal RE is first asserted. At this time, in accordance with the assertion of the delayed read enable signal REX from the delay circuit 55, the output signal of the gate circuit 52 at the word line driver DRWj (not shown) becomes the H level with respect to the selected row, and accordingly the gate circuit 54 The output signal becomes L level. As a result, the word line WLj in the selected row is driven to the cell power supply voltage VDDL level. For word line WLi, row selection signal Xi is in the non-selected state, and the output signal of gate circuit 54 is at the H level. Therefore, word line WLi is maintained at the ground voltage level.

  On the other hand, in source line driver DSRi and back gate line driver DBGi, regardless of row selection signal Xi, the output signal of gate circuit 56 is at H level, and source line SLi and back gate line BGLi maintain the ground voltage level. To do. Similarly, in digit line driver DDLi, the output signal of gate circuit 58 is at H level, and digit line DLi is maintained at the ground voltage level.

  When the data reading is completed, the read enable signal RE is negated, and then the delayed read enable signal REX is negated. Accordingly, row selection signal Xj of the selected row is negated, and word line WLj of the selected row is discharged to the ground voltage level by corresponding word line driver DWRj (not shown).

  As described above, write data is supplied as a control signal in array block units to the row selection system circuit excluding the digit line selection drive circuit. Therefore, word line WL, source line SL, and back gate line BGL are driven to the ground voltage level or cell power supply voltage level for each array block in accordance with the position of the array block or the logical value of the write data. be able to. Also, a digit line write current can be passed through the digit line of the selected row.

  FIG. 14 is a diagram schematically showing an example of the configuration of a portion that generates the row selection signal Xi shown in FIG. In FIG. 14, a row selection signal Xi is generated from a row decoder 60 that receives a row address signal ADX. The row decoder 60 is activated when the output signal of the gate circuit 62 that receives the delayed read enable signal REX and the delayed write enable signal WRX is asserted, and generates a row selection signal Xi by decoding the row address ADX from the outside. To do. Gate circuit 62 enables row decoder 60 when one of delayed read enable signal RED and delayed write enable signal WRX is asserted.

  Read column select signal CSLi is generated from gate circuit 64 receiving column select signal CSLi and delayed read enable signal REX. Gate circuit 64 drives read column selection signal CSLi to H level when both column selection signal CSLi and delayed read enable signal REX are at H level.

  FIG. 15 is a diagram schematically showing a planar layout of a voltage application unit to each region in the first embodiment of the present invention. In FIG. 15, a conductive layer 70 constituting the word line WL and a conductive layer 72 constituting the source line SL are provided in parallel. A channel region of the memory cell is disposed under the conductive layer 70 constituting the word line, and the channel region of the memory cell adjacent in the row direction is separated. As the conductive layer 70 constituting the word line WL, a two-layer structure of a lower polysilicon gate constituting the gate of the selection transistor of the memory cell and an upper low resistance metal wiring is usually used. Low resistance metal wiring is electrically connected to the virtual polysilicon gate at a predetermined interval.

  The conductive layer 72 constituting the source line SL may be constituted by a diffusion layer of the selection transistor of the memory cell, or a metal wiring electrically contacted with the diffusion layer of the selection transistor of the memory cell at a predetermined interval. May be. In any configuration, the diffusion layer coupled to the source line is provided so as to continuously extend in the row direction.

  Conductive layer 74 constituting digit line DL is disposed on conductive layer 72 constituting source line SL so as to continuously extend in the row direction. An MTJ element (or TMR element) is disposed below conductive layer 74 constituting digit line DL.

  At the terminal portions of conductive layers 70 and 72, memory cell MC for storing data and shape dummy cell FDMC for suppressing the shape distortion of memory cell MC are provided. The memory cell MC and the shape dummy cell FDMC have the same structure. The shape dummy cell FDMC is arranged at the end of the memory array and is different from the memory cell MC in that it receives shape distortion at the pattern end.

  In the memory cell MC, the underlying electrode 84 of the variable magnetoresistive element is formed so as to straddle the word line WL. The underlying electrode 84 is electrically connected to the MTJ element, and is also electrically connected to the underlying impurity region 80 a via the contact 82. Similarly, in the shape dummy cell FDMC, the underlying electrode (not explicitly shown) is electrically connected to the lower impurity region 80b through the contact 82. In this terminal portion, an active region (impurity region) 80c further extends in the row direction. In the terminal active region, the output of the back gate line driver DBG is electrically coupled. In memory cells aligned in the row direction, channel regions are separated from each other by an impurity region (not shown). However, since the substrate region under the channel isolation region functions as a back gate, a bias voltage can be supplied to each back gate region of the memory cells aligned in the row direction by the back gate line driver DBG.

  The back gate of the select transistor of the memory cell may be separated in array block units. It is not particularly required to be separated line by line. By arranging the back gate line driver corresponding to each row, the parasitic capacitance caused by the large junction capacitance can be charged / discharged at high speed even if the substrate region (back gate) is separated in array blocks. . In addition, by arranging a back gate line driver for each row, even if the substrate region is separated in array blocks, the voltage distribution in the substrate region is reduced and the back gate is accurately set to a desired voltage level for each row. Can be set.

  On the other hand, conductive layer 70 constituting word line WL is coupled to word line driver DWR through contact / via 92. In this case, the word line WL is often formed in a multi-layered shunt structure, and the word line driver DWR and the back gate line do not cause collision between the output wirings of the word line driver DWR and the back gate line driver DBG. Each DBG can be placed.

  Conductive layer 72 constituting source line SL is coupled to source line driver DSR by contact / via 94 at the end thereof. Conductive layer 74 constituting digit line DL is coupled to digit line driver DDL by contact 98 at the other end.

  The source line SL may be arranged corresponding to each memory cell row, or the memory cells in adjacent rows may be arranged so as to share the source line SL. In this case, two rows of source lines are driven by one source line driver DSR. As for the arrangement of the memory cells MC, as shown in Non-Patent Document 1, memory cells may be arranged every other column in the row direction (however, MTJ elements are arranged in each column). ) That is, the impurity region 80b is a memory cell in an adjacent row, and may be connected to the MTJ element of the memory cell in the adjacent row via the underlying electrode. Impurity regions 80a and 80b may be arranged so as to intersect the word line for each column.

  Note that the source line driver DSR and the back gate line driver DBG are not particularly required to be provided for each memory cell row. A source line driver and a back gate line driver having a large current driving capability may be provided for each of memory array blocks 1L and 1R. However, by disposing the source line driver DSR and the back gate line driver DBG for each row, the source line and the back gate line can be driven to a desired voltage level at high speed.

[Example of change]
FIG. 16 schematically shows a structure of a main part of a modification of the first embodiment of the present invention. In the array arrangement shown in FIG. 16, bit lines BL and source lines SL are arranged in parallel. FIG. 16 representatively shows memory cells arranged in 2 rows and 2 columns. Source lines SL2n and SL2n + 1 provided corresponding to bit lines BLL2n and BLL2n + 1 are representatively shown. Further, word lines WLM-1, WLM, back gate lines BGLM-1, BGLM, and digit lines DLM-1, DLM are representatively shown as row-related signal lines.

  Similar to the previous embodiment, memory cell MC includes a magnetoresistive element VR and a select transistor ST connected in series between a corresponding bit line and a source line. Word line WL, digit line DL, and back gate line BGL are arranged in a direction orthogonal to these bit lines and source lines.

  In the array arrangement shown in FIG. 16, source line SL2n is divided into two parts between bit line nodes NM-1 and NM. That is, source line SL2n is divided into source lines SSL2n and SLR2n, and source line SL2n + 1 is divided into source lines SLL2n + 1 and SLR2n + 1. A source line driver is provided between nodes NM-1 and NM corresponding to each of the divided source lines. That is, source line drivers LDS2n and LDS2n + 1 are provided for source lines SLL2n and SLL2n + 1, and source line drivers RDS2n and RDS2n + 1 are provided for source lines SLR2n and SLR2n + 1.

  For bit lines BLL2n, BLL2n + 1, word lines WLM-1, WLM and back gate lines BGLM-1 and BGLM, bit line drivers DBL2n, DBR2n, DBL2n + 1, DBR2n + 1, word line driver DRWM- are the same as in the previous embodiment. 1, DRWM, and back gate line drivers DBGM-1 and DBGM are provided. These drivers have the same configuration as described above.

  Digit line drivers DLLM-1 and DLLM are also provided for digit lines DLM-1 and DLM. Delayed write enable signal WRX and write data D are applied to source line drivers LDS2n and LDS2n + 1, and delayed write enable signal WRX and complementary write data / D are applied to source line drivers RDS2n and RDS2n + 1. It is done.

  Therefore, also in the arrangement shown in FIG. 16, the memory cell array is divided into array blocks 1L and 1R, and word lines, back gate lines, and sources are arranged in units of each array block in accordance with the logical value of write data D. The voltage level of the line can be set.

  In the arrangement shown in FIG. 16, the back gate line drivers may also be arranged in a distributed manner at the center of the memory cell array (between nodes NM-1 and NM), like the source line drivers.

  Also in the arrangement of the memory cells shown in FIG. 16, the source line SL may be shared by adjacent columns of memory cells. In this case, the number of source line drivers can be reduced.

  The operation at the time of data writing to the memory cell array shown in FIG. 16 is the same as the operation at the time of data writing of the MRAM described above, and the control configuration is also the same. Omitted.

  As described above, according to the first embodiment of the present invention, the memory array is divided, and the voltage levels of the word line, the source line, and the back gate line are set according to the distance from the high potential node of the bit line. The voltage difference between the voltage of the corresponding bit line and the voltage of each node of the selection transistor of the memory cell is set to a voltage level equal to or lower than the breakdown voltage (cell power supply voltage: intermediate voltage) of the selection transistor. Thus, a high voltage can be applied to one end of the bit line, and a large write current can be supplied without increasing the size of the bit line driver.

[Embodiment 2]
FIG. 17 schematically shows a structure of a main portion of the MRAM according to the second embodiment of the present invention. In FIG. 17 as well, bit lines BL2n and 2n + 1 are representatively shown as bit lines BL, as in the first embodiment.

  The MRAM shown in FIG. 17 is a toggle MRAM. When writing data, a bit line write current always flows in a constant direction regardless of the logical value of the write data. Therefore, in bit line drivers DBL2n and DBL2n + 1 of bit line drive circuit 7L, a P channel MOS transistor is provided, and a discharge N channel MOS transistor is not provided. On the other hand, in bit line drivers DBR2n and DBR2n + 1 of bit line drive circuit 7R, an N channel MOS transistor for discharging is provided, and a P channel MOS transistor for charging is not provided.

  It is assumed that a bit line write current flows from node N0 to N2M during writing. In this case, at the time of writing, a high voltage (2.4 V) is applied to the node N0 regardless of the logical value of the write data, the node N0 acts as the first end, and the node N2M is always Ground voltage 0V is applied, and node N2M acts as the second end of the bit line.

  The arrangement of memory cells, bit lines, source lines SL, back gate lines BGL, and arrangement of read column selection gates RG in this memory cell array is the same as that of the first embodiment (see FIG. 3), and the corresponding parts Are denoted by the same reference numerals, and detailed description thereof is omitted.

  In array block 1R, back gate lines BGLM-BGL2M are fixed to the ground voltage level, and source lines SLM-SL2M are also fixed to the ground voltage level. Word line WLM-WLM2M is also driven to 1.2V (cell power supply voltage level) when selected according to bit line driver DWRM-DWR2M, and is maintained at the ground voltage level when not selected. During data writing, word lines WLM-WLM2M are maintained at the ground voltage level in the non-selected state.

  In the write mode, it is determined whether the storage data of the selected memory cell matches the write data, and data is selectively written according to the determination result. That is, in the write mode, a process of reading data stored in the memory cell and then selectively writing data is executed. Therefore, the potential of the bit line differs between internal data reading and data writing. In order to cope with this change in the bit line potential, on the other hand, in the array block 1L, the high side power supply voltage VHW from the high side power supply switching circuit 100 is used as the high side power supply voltage for the word line drivers DWR0 to DWRM-1. And the voltage from the low-side power supply switching circuit 102 is supplied as the low-side power supply voltage VLW. High side power supply switching circuit 100 transmits a voltage of 2.4 V as high side power supply voltage VHW when write activation signals WRITE and ZWRITE for actually writing data are asserted. When write activation signals WRITE and ZWRITE are inactivated (during negation), high side power supply switching circuit 100 transmits cell power supply voltage (1.2 V) as high side power supply voltage VHW.

  The low-side power supply switching circuit transmits the cell power supply voltage (1.2 V) as the low-side power supply voltage VLW when the write activation signals WRITE and ZWRITE are asserted, and otherwise the ground voltage is supplied to the low-side power supply. It is transmitted as voltage VLW.

  Voltage VG from substrate power supply switching circuit 104 is applied to back gate lines BGL0-BGLM-1, and voltage VS from source line power supply switching circuit 106 is applied to source lines SL0-SLM-1. Substrate power supply switching circuit 104 transmits cell power supply voltage 1.2V as substrate bias voltage VG when write activation signals WRITE and ZWRITE are asserted, and transmits the ground voltage as substrate bias voltage VG. Similarly, source power supply switching circuit 106 transmits cell power supply voltage 1.2V as source line voltage VS when write activation signals WRITE and ZWRITE are asserted, and transmits the ground voltage as source line voltage VS.

  FIG. 18 is a flowchart showing an operation in the data write mode of the toggle MRAM shown in FIG. Hereinafter, the data write operation of the toggle MRAM shown in FIG. 17 will be briefly described with reference to FIG.

  First, it waits for an external command. When a command is given, it is determined whether data writing is designated by this command (step SP1). When data writing is designated by a command, write data is first latched (step SP2). Then, in accordance with an address signal applied in parallel with the write instruction from the outside, internal reading of data stored in the memory cell to be written is performed (step SP3).

  A determination is made as to whether the stored data read internally matches the logical value of the latched write data (step SP4). When the logical values of the stored data and the write data match, it is not necessary to perform writing. Therefore, in this case, the writing completion process is executed to complete the writing.

  On the other hand, if the stored data and the write data do not match, the data is written by switching each power source using the power source switching circuit as described in detail below. In this case, in the configuration shown in FIG. 17, the bit line write current IBLwr flows from the left bit line drive circuit 7L to the right bit line drive circuit 1R in the selected bit line BL. The data stored in the memory cell is inverted by the current flowing through the digit line DL and the bit line BL. Specifically, at the time of writing, a digit line current is first supplied, and then a bit line current is supplied. Thereafter, the supply of the digit line current is stopped and the bit line current is supplied. Thereafter, the bit line current is stopped.

  It is determined whether or not the series of writing sequences is completed (step SP6). When the series of writing sequences is completed, the writing is finished.

  As described above, in the toggle MRAM, first, when data is written, the stored data is read internally, and then the bit line is selectively selected according to the coincidence / mismatch of the logical value of the stored data and the write data. A write current is made to flow. In internal read and external read access, the word line voltage is changed between 1.2V and 0V. This is because the data in the memory cell is read by always passing a read current in one direction on internal data line LIO. At the time of writing, the voltage levels of the word lines, source lines, and back gate lines are updated in units of memory array blocks. In array block 1R, the voltages of the word line, back gate line, and source line are fixed. In the following, this write sequence will be described with respect to the relationship between the voltage of the bit line and the voltage of each word line, back gate line, and source line. The digit line current is only required to flow at a timing earlier than the bit line current and to stop the current supply.

  FIG. 19 is a timing chart showing an operation at the time of data writing of the toggle MRAM shown in FIG. Hereinafter, the data write operation of the toggle MRAM shown in FIG. 17 will be described more specifically with reference to FIG. FIG. 19 shows an example of an operation when a memory cell arranged corresponding to the intersection of bit line BL2n and word line WL0 is selected.

  The writing mode is set according to the application command at time t10. At time t10, first, in order to perform internal reading, read column selection signal CSLR2n is asserted, and read column selection gate RG2n becomes conductive. The bit line drivers DBR2n and DBR2n + 1 of the right bit line drive circuit 1R are set to the output high impedance state. In the left bit line drive circuit 1L, the bit line drivers DBL2n and DBL2N + 1 are in the output high impedance state, as in the standby state. The read column select gate is turned on, the read voltage is supplied to the selected bit line BL2n, and the voltage level rises. Unselected bit line BL2n + 1 is maintained at the ground voltage level.

  At this time, the word line WL0 corresponding to the addressed row is driven to the selected state, and its voltage level rises to about 1.2V. As a result, a current corresponding to the data stored in the memory cell flows through the bit line BL2n. This current is detected by a sense amplifier connected to internal data line LIO, and data is read internally. This internal read data is preferably latched.

  When the internal reading is completed at time t11, the internal reading cycle is terminated, and then a comparison / standby cycle for comparing the internal reading data and the writing data is started. In this cycle, bit line precharge control signals BLRB2n and BLRB2n + 1 are driven to the H level, the N-channel MOS transistors of bit line drivers DBR2n and DBR2n + 1 are turned on, and bit lines BL2n and BL2n + 1 are precharged to the ground voltage level. .

  If the stored data and the internal read data do not match as a result of the internal comparison, a write cycle for writing data to the selected memory cell is started. If the comparison result indicates a match, this write cycle is not executed, and bit lines BL2n and BL2n + 1 maintain the standby state and wait for the next access.

  At time t13, bit line precharge control signals BLRB2n and BLRB2n + 1 are negated, and the precharging of the bit lines BL2n and BL2n + 1 to the ground voltage level is completed. In parallel with this, precharge control signals UB2n and UB2n + 1 are asserted, and bit lines BL2n and BL2n + 1 are precharged to the cell power supply voltage (1.2V) level.

  At time t14, power supply switching circuits 100, 102, 104 and 106 switch the voltage levels of output voltages VHW, VLW, VG and VS in parallel with the bit line precharge. In this state, word line drivers DWR0 to DWRM-1 are in a non-selected state. Therefore, the voltage level of word lines WL0-WLM-1 rises to the cell power supply voltage (1.2V) level. Similarly, the voltage levels of back gate lines BGL0-BGLM-1 and source lines SL0-SLM-1 also rise to the cell power supply voltage (1.2V) level.

  At time t15, the bit line precharge control signal UB2n is negated, and the precharge of the bit line BL2n is completed. Bit line BL2n + 1 is continuously precharged to the cell power supply voltage level.

  Next, in the bit line driver DBL2n, the bit line drive control signal BLL2n is asserted, and the node N0 of the bit line BL2n is driven to a voltage level of 2.4V. As a result, write current IBLwr flows from node N0 to node N2M in bit line BL2n.

  When data writing to the memory cell is completed at time t16, bit line drive control signals BLL2n and BLR2n are negated, and supply of the write current to the bit line is stopped. In parallel with this, the precharge control signal UB2n is asserted, and the bit line BL2n is precharged to the cell power supply voltage (1.2V).

  After precharge of bit line BL2n is completed at time t17, power supply switching circuits 100, 102, 104 and 106 again switch the voltage level of the output power supply voltage, and word line WL, source line SL and back gate line BGL is driven to the ground voltage level. Control signals BLRB2n and BLRB2n + 1 for bit line drivers DBR2n and DBR2n + 1 are asserted, and bit lines BL2n and BL2n + 1 are precharged to the ground voltage level. The write mode is completed and the MRAM is in a standby state.

  Therefore, although power supply switching circuits 100, 102, 104, and 106 are used, the operation from time t13 to time t17 for writing data to this memory cell is the same as that of the write cycle in the first embodiment. Same as operation.

  By supplying voltages of 2.4 V and 1.2 V to the word line drivers DBR0 to DBRM-1 as power supply voltages VHW and BLW, respectively, the breakdown voltage of the constituent elements of the word line driver DBR0 is guaranteed.

  FIG. 20 schematically shows a structure of the control unit of the toggle MRAM according to the second embodiment of the present invention. 20, an array input / output circuit 110 for inputting / outputting data, a column decode circuit 140 for generating a column selection signal, and a row decoder 146 for generating a row selection signal are provided as array peripheral circuits. Although the row decoder 146 is provided corresponding to each row in the row decoding circuit, this row decoding circuit is not shown in FIG.

  Input / output circuit 110 is activated during data write mode and data latch 112 for latching write data and when data is read (including internal read), and detects and amplifies read data on internal data line LIO. Sense amplifier circuit 114 for generating internal read data RQ. An input buffer that receives external data is provided in front of the data latch 112, and an output buffer that generates external data is provided in the next stage of the sense amplifier circuit 114.

  The control circuit 120 includes a command decoder 122 that decodes an external command CMD. The command decoder 122 activates the read enable signal RE when the command CMD instructs data reading, and generates the write enable fast signal WEF when the command CMD instructs data writing.

  When one of read enable signal RE and write enable fast signal WEF is asserted, sense amplifier circuit 114 is activated. The data latch 112 latches the write data when the write enable fast signal WEF is asserted.

  Control circuit 120 further compares gate circuit 124 receiving read enable signal RE and write enable fast signal WEF, and latches data D of data latch 112 and internal read data RQ from sense amplifier circuit 114 when activated. And a write activation circuit 128 that selectively asserts the write enable signal WE in accordance with the comparison result of the comparison circuit 126.

  Gate circuit 124 asserts internal access operation activation signal ACT when one of read enable signal RE and write enable fast signal WEF is asserted. Column decoder 142 included in column decode circuit 140 decodes column address signal ADY according to the assertion of internal access operation activation signal ACT to generate column selection signal CSLi.

  Comparison circuit 126 is activated when write enable fast signal WEF is activated, and asserts mismatch instruction signal MISS when the logical values of latch data D and internal read data do not match.

  Write activation circuit 128 asserts write enable signal WE when mismatch instruction signal MISS from comparison circuit 126 is asserted. Write activation circuit 128 also maintains write activation signal WE in the negated state when mismatch instruction signal MISS from comparison circuit 126 is maintained in the negated state.

  Write enable signal WE from write activation circuit 128 is applied to delay circuit 132, falling delay circuit 131 and one-shot pulse generator 133. Falling delay circuit 131, delay circuit 132, and one-shot pulse generator 133 correspond to circuits 31, 33, and 32 in control circuit 11 described with reference to FIG. 8 in the first embodiment. The fall delay circuit 131 outputs a write enable delay signal WED, and the delay circuit 132 generates a write activation signal WRITE. A one-shot pulse signal WRP is generated from the one-shot pulse generator 133. Write activation signal WRITE from delay circuit 132 corresponds to delayed write enable signal WRX in the first embodiment, and adjusts the voltage levels of word lines, back gate lines and source lines in memory array 1L. Determine the period.

  Similarly to the first embodiment, gate circuit 37 is provided corresponding to each column, and generates write column selection signal Yi according to write enable delay signal WED, one-shot pulse signal WRP, and column selection signal CSLi.

  Similarly to the first embodiment, gate circuit 136 is provided corresponding to each column, and receives output signal ACTDD of column circuit 147 and column selection signal CSLi, and generates read column selection signal CSLRi. Gate circuit 147 receives read enable delay signal REX and write enable fast signal WEF, and asserts column access activation signal ACTDD when one of these input signals is asserted.

  Gate circuits 144 and 148 are provided for row selection control. Gate circuit 144 receives write enable signal WE and write activation signal WRITE, and asserts its output signal when these input signals are both asserted. Gate circuit 148 receives the output signal of gate circuit 144, read enable delay signal REX, and write enable fast signal WEF, and asserts internal access activation delay signal ACTD when at least one of these input signals is asserted. To do. The row decoder 146 is activated when the delay signal ACTD output from the gate circuit 148 is asserted, decodes the row address signal ADX, and generates a row selection signal Xi.

  FIG. 21 is a timing chart showing an operation at the time of data writing of the control circuit shown in FIG. The operation of the control circuit 120 shown in FIG. 20 will be briefly described below with reference to FIG.

  At time t20, data writing is instructed, and write enable fast signal WEF from command decoder 122 is asserted. In accordance with the assertion of write enable fast signal WEF, column decoder 142 and row decoder 146 are activated to perform a decoding operation and generate column selection signal CSLi and row selection signal Xi.

  In accordance with row selection signal Xi, the word line corresponding to the selected memory cell row is driven to the selected state. In accordance with column selection signal CSLi, bit line BLi of the selected column is coupled to internal data line LIO via corresponding read column selection gate RGi.

  Sense amplifier 114 is activated in accordance with activation of write enable fast signal WEF, and data in the selected memory cell is read in accordance with the current flowing through internal read data line LIO. Next, the comparison circuit 126 compares the data D latched in the data latch 112 with the internal read data RQ from the sense amplifier circuit 114, and asserts a mismatch instruction signal MISS if these logical values do not match. .

  When the mismatch instruction signal MISS is asserted, the write activation circuit 128 asserts the write enable signal WE. Accordingly, a cycle for actually writing data internally is executed from time t22.

  That is, the write enable delay signal WED from the falling delay circuit 131 is asserted, and the one-shot pulse signal WRP from the one-shot pulse generator 133 is asserted. At the time of writing, internal access operation activation signal ACT from gate circuit 124 is reasserted in accordance with assertion of write enable signal WE. In response, the column decoder 142 performs a decoding operation and asserts the column selection signal CSLi again. During this period, as in the first embodiment, precharging of the bit line to the cell power supply voltage level is performed. At this time, even if write enable signal WE is asserted, write activation signal WRITE is negated, the output signal of gate circuit 144 is in the root gate state, and row decoder 146 is in the inactive state.

  At time t23, write activation signal WRITE corresponding to the delayed write enable signal from delay circuit 132 is activated, and power supply switching is executed (not shown). By this power supply switching, the voltage levels of the word lines, source lines, and back gate lines of the array block 1L are changed. At this time, the output signal of the gate circuit 144 is asserted according to the assertion of the write activation signal WRITE, and the output signal ACTD of the gate circuit 148 is asserted accordingly. Again, the row decoder 146 is activated and asserts the row selection signal Xi. When the voltage adjustment of the word line, the source line, and the back gate line is completed, the digit line driver is activated in accordance with the row selection signal Xi to supply a write current to the digit line of the selected row.

  Next, when one-shot pulse signal WRP is negated, write column selection signal Yi is asserted at time t24. Thus, a write current flows through the bit line during a period determined by the write enable signal WE. At the time of writing, therefore, a current first flows in the digit line in accordance with the write activation signal WRITE, and then a current flows in the bit line in accordance with the negation of the one-shot pulse signal WRP. The timing of flowing the digit line current and the bit line current is adjusted to an appropriate timing and period according to the write activation signal WRITE and the write enable signal WE so as to surely cause the magnetization reversal in the memory cell.

  Data writing is completed at time t25, write enable signal WE is negated, column select signal CSLi is negated, and write column select signal Yi is negated accordingly. At this time, the output signal of the gate circuit 144 is negated, and the row selection signal Xi from the row decoder 146 is also negated. In this case, the digit line current has already been stopped. Thereafter, the write enable delay signal WED is negated at time t26.

  Therefore, when a write command is given in toggle MRAM, data is first internally read in accordance with the write enable fast signal, and data is written in accordance with the match / mismatch of the write data and the internal read data. it can.

  FIG. 22 specifically shows a configuration of the bit line driver of the toggle MRAM according to the second embodiment of the present invention. In FIG. 22, bit line driver DBLi on the left side includes an inverter 150 that receives write column selection signal Yi, and a P channel MOS transistor PQL that receives bit line voltage control signal BLLi output from inverter 150.

  The right bit line driver DBRi includes a gate circuit 152 that receives an access activation delay signal ACTDD and a write enable delay signal WED, a gate circuit 154 that receives an output signal of the gate circuit 152 and a write column selection signal Yi, and a gate circuit N channel MOS transistor NQR which is selectively turned on according to bit line voltage control signal BLRBi from 154 is included.

  When P channel MOS transistor PQL is conductive, it electrically couples a peripheral power supply node receiving peripheral power supply voltage VDDH (3.3 V) to the first end (node N0) of bit line BLi. MOS transistor NQR couples second node N2M at the second end of bit line BLi to the ground node when conducting.

  Gate circuit 152 outputs an H level signal when both activation delay signal ACTDD and write enable delay signal WED are in a negated state. Gate circuit 154 outputs an H level signal when one of the output signal of gate circuit 152 and write column selection signal Yi is active.

  Therefore, during write operation, when write column select signal Yi is asserted, MOS transistors PQL and NQR are both turned on, and a write current flows from node N0 toward N2M in bit line BLi.

  In the configuration shown in FIG. 22, the bit line current is shown to flow during the assertion period of write column selection signal Yi. However, as described above, the period and timing in which the bit line write current flows are appropriately determined according to the period in which the digit line current flows.

  At the time of data reading, write column selection signal Yi is negated and MOS transistor PQL is off. In both internal and external data reading, the write enable delay signal WED is at the negated L level. On the other hand, when reading this data (both internal and external), activation delay signal ACTDD is asserted and the output signal of gate circuit 152 attains an L level. Therefore, at the time of data reading to the inside or the outside, control signal BLRBi from gate circuit 154 is at L level, and MOS transistor NQR maintains the off state.

  The gate circuit 50 shown in FIG. 12 is not necessary for the word line driver WLBi. In the configuration shown in FIG. 12, internal access activation delay signal ACTDD may be applied instead of read enable signal RE. Write data D and write activation signal. When reading data (internal and external), the word line driver is enabled in accordance with delay signal ACTDD, and when row select signal Xi is asserted, corresponding word line WLi is selected. Driven to state. At the time of data writing, even if row selection signal Xi is asserted, internal access activation delay signal ACTDD is in a negated state, and the word line driver outputs a voltage in a non-selected state.

  For source line driver DSR, write data D and / D are fixed at H level and L level, respectively, in the configuration shown in FIG. A write activation signal WRITE is given as a control signal. Thereby, in the array block 1R, the source line potential can be changed in accordance with the write activation signal in the data write cycle. In array block 1L, the output signal of gate circuit 56 shown in FIG. 12 is fixed at H level, and accordingly, source line SL is fixed at L level (ground voltage level). The same applies to the back gate line BGL.

  For digit line driver DLLi, a signal obtained by ORing write activation signal WRITE and write enable first signal WEF in the configuration shown in FIG. 12 is supplied instead of control signal WRX. However, the timing of the row selection signal Xi is appropriately adjusted according to the timing of the bit line current.

  FIG. 23 is a diagram showing an example of the configuration of the power supply switching circuit shown in FIG. In FIG. 23, the step-down voltage VDDM (2.4 V) from the step-down circuit 150 is supplied to the high-side power supply switching circuit 100 as the first power supply voltage. A cell power supply voltage VDDL is supplied to the high-side power supply switching circuit 100 as the second power supply voltage.

  The high-side power supply switching circuit 100 converts the level of the inverted signal ZWRITE of the write activation signal WRITE given through the inverter 152, and the word line driver high in accordance with the output signal of the level conversion circuit 100a. A CMOS inverter 100b that generates the side power supply voltage VWH is included. The CMOS inverter 100b includes a P channel MOS transistor (P) and an N channel MOS transistor (N).

  Low-side power supply switching circuit 102, substrate power supply switching circuit 104, and source power supply switching circuit 106 are each composed of a CMOS inverter that receives complementary write activation signal ZWRITE, and cell power supply voltage VDDL as a high-side power supply voltage. And a ground voltage as a low-side power supply voltage.

  In the configuration of the power supply switching circuit shown in FIG. 23, write activation signal WRITE and complementary write activation signal ZWRITE change between cell power supply voltage VDDL and ground voltage. Level conversion circuit 150 converts complementary write activation signal ZWRITE into a signal that changes between step-down voltage VDDM and cell power supply voltage VDDL. No logical conversion is performed. Therefore, when the write activation signal WRITE is asserted, the high-side power supply voltage VWH becomes the step-down voltage VDDM (2.4 V). Similarly, the low-side power supply voltage VWL is at the cell power supply voltage VDDL level. Further, the back gate line voltage VG and the source line voltage VS are also at the cell power supply voltage VDDL level. The voltage level of the signal output from the word line driver is the low-side power supply voltage level.

  When write activation signal WRITE is negated, complementary write activation signal ZWRITE is at the H level. Therefore, the word line driver high-side power supply voltage VWH is set to the cell power supply voltage VDDL level, and the low-side power supply voltage VWL is maintained at the ground voltage level. Further, the back gate line voltage VG and the source line voltage VS are also maintained at the ground voltage level.

  When a source line driver and a back gate line driver are provided corresponding to each row and these are constituted by CMOS inverters, the power supply switching circuits 104 and 106 shown in FIG. 23 are respectively connected to the back gate line driver and the source. Used as a line driver.

  Thereby, in the toggle MRAM, when data is actually written to the memory cell, the word line voltage, the back gate voltage, and the source line voltage are switched in the array block 1L, and the applied voltage of the selection transistor of the memory cell is relaxed. Thus, a high voltage can be supplied to the bit line.

[Example of change]
FIG. 24 schematically shows a structure of a main portion of a modified example of the toggle MRAM according to the second embodiment of the present invention. In the toggle MRAM shown in FIG. 24, a step-down voltage VDDM (2.4 V) from step-down circuit 160 is supplied as a high-side power supply voltage to word line drivers DWR0 to DWRM-1 provided for array block 1L. The cell power supply voltage VDDL (1.2 V) is supplied as the low-side power supply voltage. The cell power supply voltage VDDL is supplied to the back gate lines BGL0 to BGLM-1, and the cell power supply voltage VDDL is also supplied to the source lines SL0 to SLM-1. The other configuration of the toggle MRAM shown in FIG. 20 is the same as the configuration of the toggle MRAM shown in FIG. 17, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 25 is a timing chart showing an operation in the data write mode of toggle MRM shown in FIG. The operation waveform diagram in the write mode shown in FIG. 25 is different from the operation timing diagram shown in FIG. 19 in the following points. That is, the word lines WL0 to WLM-1 provided in the array block 1L have an amplitude between the step-down voltage VDDM (2.4V) and the cell power supply voltage VDDL (1.2V). When data writing to the memory cell is performed, all word lines WL-WLM-1 are maintained at the cell power supply voltage VDDL level in the non-selected state. At the time of data reading (including both internal and external), the selected word line is driven to the step-down voltage VDDM (2.4V) level.

  The waveform and voltage level of the operation timing chart shown in FIG. 25 are the same as the waveform and voltage level of the operation timing chart shown in FIG.

  That is, in the toggle MRAM shown in FIG. 24, in the array block 1L, the back gate lines BGL0 to BGL-1 are fixedly set to the cell power supply voltage VDDL (1.2V) level, and the source lines SL0 to SLM- 1 is also fixedly set to the cell power supply voltage VDDL (1.2 V) level. The word lines WL0 to WLM-1 are driven to the 2.4V (high voltage VDDM) level when selected, and are maintained at the cell power supply voltage VDDL (1.2V) level when not selected.

  In the array block 1R, the amplitude of the word lines WLM-WL2M is between the cell power supply voltage VDDL and the ground voltage. Source line SL and back gate line BGL are fixedly maintained at the ground voltage level.

  Also in this configuration, at the time of data writing, the difference between the voltage of the bit line BL and the voltage of each node of the selection transistor of the memory cell is 1.2 V at the maximum. When the selection transistor of the memory cell is selected at the time of reading, the gate voltage is driven to the step-down voltage VDDM level of 2.4V. In this case, both the source line SL and the back gate line BGL are at the cell power supply voltage VDDL level of 1.2V. Accordingly, in the selection transistor, the gate-source voltage and the gate-back gate voltage are both 1.2 V, and the source and the back gate are at the same voltage level. This is the same condition as the voltage applied to the selection transistor of the memory cell of the array block 1R. Therefore, at the time of data reading, regardless of which memory cell is selected, a read current can be generated accurately in accordance with stored data.

  In array blocks 1L and 1R, since the bag gate voltage (substrate region voltage) is different, they are formed in separate wells, and these wells are electrically separated. In this case, the back gate region may be electrically isolated for each memory cell row.

  In the configuration of the toggle MRAM shown in FIG. 20, at the time of data writing, the word lines are not required to be driven to the selected state in array block 1L, and all need only be maintained in the non-selected state. Therefore, except for the voltage switching configuration, the conventional toggle MRAM data writing control configuration can be used.

  The configuration of the control circuit for controlling the operation of the toggle MRAM shown in FIG. 24 can also be the configuration of the control circuit shown in FIG. However, the word line drive control signals WLB0 to WLBM-1 for the word line drivers DWR0 to DWRM-1 for driving the array block word lines WL0 to WLM-1 are changed between the step-down voltage VDDM and the cell power supply voltage VDDL. Therefore, it is necessary to provide a circuit for performing level conversion for row selection signals X0-XM-1.

  In data read, in array block 1L, when a word line is selected, a current flows from the source line to the corresponding bit line, and in array block 1R, a read current flows from the bit line to the source line. Therefore, it is necessary to switch the logical value of the read data in accordance with the read path in accordance with the position of the selected array block. Therefore, the internal configuration of sense amplifier circuit 114 is different.

  FIG. 26 schematically shows an example of the configuration of sense amplifier circuit 114 in a modification of the second embodiment of the present invention. In FIG. 26, sense amplifier circuit 114 includes a constant current source 170 and a P channel MOS transistor 172 that selectively supplies a constant current from constant current source 170 to internal data line LIO in accordance with block selection signal BS. Block selection signal BS is set to H level when array block 1L is selected, and isolates constant current source 170 from internal data line LIO. On the other hand, when array block 1R is designated, block selection signal BS becomes L level, MOS transistor 172 is turned on, and a constant current from constant current source 170 is supplied to internal data line 170.

  Sense amplifier circuit 114 further selects one of current sense circuit 174 for detecting the current flowing through internal data line LIO and complementary output signals SAO and ZSAO of current sense circuit 174 in accordance with block select signal BS to internally read data. A selector 176 that generates Qout is included.

  As the current sense circuit 174, any configuration can be used as long as it detects the magnitude of the current applied to the input section and generates a complementary signal.

  Selector 176 selects complementary sense amplifier ZSAO when block selection signal BS designates array block 1L, and selects sense amplifier output signal SAO when block selection signal BS designates array block 1R.

  FIG. 27 is a diagram schematically showing a current to the current sense circuit 170 when the memory cell MC of the array block 1L is selected. When the memory cell of the array block 1L is selected, the gate of the selection transistor is 2.4V, the source line SL is 1.2V, and the back gate is 1.2V. The bit line is set to a read voltage level lower than the cell power supply voltage. In this state, memory cell current Im flows from internal source line SL maintained at 1.2 V to internal data line LIO via memory cell MC. In this case, the memory cell current Ih1 that flows when the memory cell MC is in the high resistance state or the memory cell current Il1 that is in the low resistance state of the memory cell MC is applied to the current sense circuit 170. When the selected memory cell MC is in a high resistance state, the value of the current Im supplied from the source line SL to the internal data line LIO via the memory cell MC is small. Therefore, the following relationship is established.

Ih1 <Il1
FIG. 28 schematically shows a path through which a read current flows when memory cell MC of array block 1R is selected. In this case, source line SL of memory cell MC is coupled to ground. To the gate of the select transistor. A cell power supply voltage of 1.2V is applied. The back gate is at ground voltage level. In this state, constant current Ic from constant current source 170 is supplied to internal data line LIO. Of this constant current Ic, memory cell current Im flows to memory cell MC, and residual current Ir is applied to current sense circuit 170. When the memory cell current Im flowing when the selected memory cell MC is in the high resistance state is Ih2, and the memory cell current Im when the memory cell MC is in the low resistance state is Il2, the following relationship is established.

Ir = Ic-Ih2> Ic-Il2
Therefore, the magnitude relationship between the currents detected by current sense circuit 170 is reversed between array blocks 1L and 1R.

  Since the reference current Iref is set to an intermediate value of each detection current, the following relational expression is obtained.

Iref = (Il1 + Ih1) / 2
= (Ic-Ih2 + Ic-Il2) / 2 (1)
Since the above-described reference current Iref is equal regardless of the position of the selected array block, the following equation is obtained from the above equation (1).

Ic = (Ih1 + Ih2 + Il1 + Il2) / 2
Therefore, by selecting one of output signals SAO and ZSAO of current sense circuit 170 in accordance with block selection signal BS, read data Qout corresponding to the storage data of the memory cell can always be generated accurately.

  As described above, according to the second embodiment of the present invention, in the toggle MRAM, the voltage levels of the word lines, the source lines, and the back gate lines of the array block provided close to the high potential bit line end are set to at least At the time of data writing, the voltage levels of the remaining blocks are set higher than those of the remaining blocks so as to guarantee the withstand voltage against the bit line voltage. Thus, when supplying the bit line write current, a high voltage can be applied to the first end of the bit line, and a sufficiently large bit line write current can flow. Further, when the voltage for each array block is fixedly set, the control configuration for voltage switching is simplified.

  In the second embodiment, as in the modification of the first embodiment, when the bit line BL and the source line SL are wired in parallel, the voltage level of the source line is set to the boundary between the array blocks 1L and 1R. Change in

  A driver may be arranged for each row for each of the source line SL and the back gate line BGL. The voltage level of the driver output signal is fixedly set according to the position of the array block.

[Embodiment 3]
FIG. 29 schematically shows a structure of a main portion of the MRAM according to the third embodiment of the present invention. In FIG. 29, the memory cell array 1 is divided into array blocks 1A-1N. A bit line BL is provided in common to these array blocks 1A-1N. Bit line drive circuits 7L and 7R are provided at both ends of the bit line BL. The configurations of these bit line drive circuits 7L and 7R are the same as those described with reference to FIGS. 3 and 10 in the first embodiment.

  Drive circuit groups 200A-200N are provided corresponding to array blocks 1A-1N, respectively. Each of these drive circuit groups 200A-200N includes a word line drive circuit, a source line drive circuit, and a back gate line drive circuit. Each of drive circuit groups 200A-200N adjusts the voltage levels of the corresponding word line, source line, and back gate line BL in accordance with delayed write enable signal WRX and write data D. The configurations of the word line drivers, source line drivers, and back gate drivers included in these drive circuit groups 200A-200N are the same as those shown in FIG. However, in drive circuit group 200B-200M, write data D is set to H level, and at the time of data writing, each high-side power supply voltage (cell power supply voltage) is supplied to the source line of corresponding array block 1B-1M, It is transmitted to the back gate line and the word line. Drive circuit groups 200A and 200N are respectively supplied to a corresponding array block, a word line, a source line, and a back gate line according to a logical value of write data D, and a high side power supply voltage (cell power supply voltage) and a low side power supply voltage Transmit one of (ground voltage).

  A multiplexer (MUX) 202A-202N and a step-down circuit (VDC) 204A-204N are provided corresponding to each of the drive circuit groups 200A-200N. Multiplexers 202A and 202N always select cell power supply voltage VDDL as the high-side power supply voltage and transmit the corresponding drive group to 200A and 200N. On the other hand, multiplexers 202B-202M select one of cell power supply voltage VDDL and the output voltage of corresponding step-down circuit 204B-204M in accordance with delayed write enable signal WRX and write data D, and drive circuit groups 200B-200M. Is supplied as a high-side power supply voltage.

  The multiplexers 202A and 202N always select the cell power supply voltage VDDL as the high-side power supply voltage. This is because drive circuit groups 200A and 200N set the word line, source line, and back gate voltage to the voltage level of ground voltage or cell power supply voltage VDDL (1.2 V) according to the logical value of write data D. Therefore, multiplexers 202A and 202N do not need to select the output voltage of the step-down circuit.

  The reference voltage from the reference voltage generation circuit 208 is transmitted to these step-down circuits 204B-204M via selectors (SEL) 206B-206M. These step-down circuits 204B-204M generate a voltage of a level corresponding to the reference voltage given through the selectors 206B-206M and transmit it to the corresponding multiplexers 202B-202M. The reference voltage generation circuit 208 transmits two reference voltages having different voltage levels to each of the selectors 206B to 206M. Depending on the logical value of the write data D, the selectors 206B-206M select one of the two supplied reference voltages. This is because it is necessary to switch the voltage levels of the word lines, source lines, and back gate lines in array block 1B-1M according to the direction in which the write current of the selected bit line flows.

  FIG. 29 also shows selectors 206A and 206N. However, selectors 206A and 206N are provided for array blocks 1A and 1N simply to maintain the regularity of the circuit layout pattern, and need not be provided.

  In the MRAM shown in FIG. 29, at the time of data writing, in array blocks 1A and 1N, in accordance with the logical value of the write data, the same manner as described in the first embodiment, word lines WL, The voltage levels of source line SL and back gate line BGL are switched. To the array block 1B-1M, the voltage from the step-down circuit 204B-204M is supplied as a high-side power supply voltage during data writing. Drive circuit groups 200B-200M have write data D set at an H level, and transmit a high-side power supply voltage to corresponding word lines, source lines, and back gate lines when data is written.

  FIG. 30 schematically shows voltages of selected bit lines BL and voltage levels of word lines WL, source lines SL and back gate lines BGL at the time of data writing in the MRAM shown in FIG. In FIG. 30, the horizontal axis indicates the voltage along the bit line nodes N0-N2M, and the vertical axis indicates the voltage. As shown in FIG. 30, at the time of data writing, according to the logical value of write data D, bit line BL has node N0 (or N2M) set to a high voltage level of 2.4V and node N2M (or N0). Is maintained at the ground voltage level. In this case, the output voltage of the step-down circuit 204B-204M is set to a voltage level set by the reference voltage, and the word line WL, the source line SL, and the back gate line BGL are set in the drive circuit group 200B-200M. The voltage level decreases sequentially.

  Therefore, even in this case, a large bit line write current can be supplied while guaranteeing the breakdown voltage of the transistor of the selected memory cell.

  In the configuration shown in FIG. 29, drive circuit groups 200B-200M transmit the high-side power supply voltage at the time of data writing. Therefore, in this case, the control signal applied to each driver is at L level, and the minimum value of the voltage level generated by the step-down circuit (VDC) is the absolute value of the threshold voltage of the P channel MOS transistor in this driver output stage. It is necessary to set a higher voltage level. When the reference voltage generation circuit 208 supplies the write current to the bit line BL by setting the step of the reference voltage to be generated to be equal to or higher than the absolute value of the threshold voltage of the P-channel MOS transistor in the driver output stage. The voltage levels of the word line WL, the source line SL, and the back gate line BGL can be surely set for each of the array blocks 1A-1N.

  In the case of the configuration shown in FIG. 29, it is necessary to set the voltage level of the back gate line for each of the array blocks 1A-1N. Therefore, the well regions of array blocks 1A-1N are separated from each other, or a back gate region (well region) is separated for each row.

[Example of change]
FIG. 31 schematically shows a structure of a main portion of an MRAM according to a modification of the third embodiment of the present invention. FIG. 31 schematically shows the configuration of the toggle MRAM array block 1K. The memory cell array 1 is divided into a plurality of array blocks (1A-1N) as in the configuration shown in FIG. A drive circuit group 210K is provided corresponding to array block 1K. The drive circuit group 210K includes a word line drive circuit, a source line drive circuit, and a back gate line drive circuit. Similar to the configuration of the second embodiment, the selection mode of each driver is set in accordance with write activation signal WRITE.

  For the drive circuit group 210K, a high-side power supply multiplexer (HMUX) 212 that transmits a high-side power supply voltage VH and a low-side power supply multiplexer (LMUX) 214 that transmits a low-side power supply voltage VL are provided. High side power supply multiplexer 212 selects one of the output voltage of high side step-down circuit 216 and cell power supply voltage VDDL in accordance with write activation signal WRITE. The low-side power supply multiplexer 214 selects one of the ground voltage and the output voltage of the low-side step-down circuit (LVDC) 214 according to the write activation signal WRITE. The high-side step-down circuit (HVDC) 216 generates a voltage between the maximum value 2.4V and the cell power supply voltage 1.2V. The low-side step-down circuit (LVDC) 218 generates a voltage between the cell power supply voltage (1.2 V) and the ground voltage level. The voltage level generated by these step-down circuits 216 and 218 is set according to the position of the array block 1K in the array.

  The difference between the voltage generated by the high-side high-voltage circuit (HVDC) 216 and the voltage generated by the low-side high-voltage circuit (LVDC) 218 is a voltage level of the cell power supply voltage 1.2V. By setting the voltage level generated by these step-down circuits 216 and 218 to a voltage level corresponding to the distance from the node (first end) N0 of the bit line, the bit line writing is performed for a plurality of array blocks. The word line, the source line, and the back gate line can be set to a voltage level corresponding to the voltage of the bit line at the time of supplying the built-in current.

  The configuration of drive circuit group 210K and multiplexers 212 and 214 is the same as the configuration of the drive circuit and power supply switching circuit described in the second embodiment.

  As shown in the modification of the second embodiment, in the case where the high side power supply voltage and the low side power supply voltage of the driver are fixed, the multiplexers 212 and 214 shown in FIG. 31 are not necessary, and the high side step-down circuit (HVDC) ) The output voltage of 216 and the output voltage of the low-side step-down circuit (LVDC) 218 are applied to the drive circuit group 210K as the high-side power supply voltage VH and the low-side power supply voltage VL, respectively.

  However, in this case, the direction of the current flowing through the bit line differs during data reading according to the relationship between the source line voltage and the bit line voltage. Therefore, in this case, at the time of data reading (in both internal and external reading), bit line BL is set to an intermediate voltage level, and the voltage level of the source line is set to the intermediate voltage level of this cell power supply voltage (bit line reading) The configuration of the sense amplifier is switched and the sense amplifier output signal is switched according to whether it is higher than the (precharge voltage) level. However, when supplying a read current to the source line and bit line, it is necessary to provide a constant current source for each source line and supply a constant current of the same magnitude as that when the current flows from the bit line to the source line. is there.

  As described above, according to the third embodiment of the present invention, the memory cells of the array block are applied to the back gate, the source and the gate of the selection transistor according to the distance from the node to which the high voltage of the bit line is applied. Therefore, it is possible to reliably ensure the withstand voltage of the memory cell and supply a large write current without increasing the size of the bit line driver.

  In the first to third embodiments, the voltage levels of the word lines, source lines, and back gate lines are adjusted. However, it is only necessary to adjust the voltage level for the weakest withstand voltage depending on the withstand voltage of the select transistor of the memory cell, that is, the gate insulating film withstand voltage and the junction withstand voltage. Therefore, it is not necessary to adjust the voltage levels of all the word lines, source lines, and back gate lines. The voltage level may be adjusted so that at least one withstand voltage of the word line, the source line, and the back gate line corresponding to the low withstand voltage portion is guaranteed.

  In general, when the present invention is applied to a thin-film magnetic semiconductor memory device (MRAM), an MRAM that can be reliably written without increasing the chip size can be realized. When this MRAM is formed on the same chip as other processors, a processing system with a small occupation area can be realized.

1 schematically shows a whole structure of an MRAM according to the first embodiment of the present invention. FIG. FIG. 2 is a diagram showing a configuration of a memory cell shown in FIG. 1. It is a figure which shows more specifically the structure of the principal part of MRAM according to Embodiment 1 of this invention. FIG. 4 is a timing chart showing an operation of the MRAM shown in FIG. 3. FIG. 4 is a diagram showing voltages of a bit line, a word line, a back gate line, and a source line at the time of data writing in the MRAM shown in FIG. 3. It is a figure which shows the applied voltage of the memory cell selection transistor at the time of the data writing in Embodiment 1 of this invention. It is a figure which shows the applied voltage of the memory cell selection transistor in Embodiment 1 of this invention. It is a figure which shows roughly the structure of the principal part of the control circuit of MRAM in Embodiment 1 of this invention. FIG. 9 is a timing chart showing an operation of the control circuit shown in FIG. 8. It is a figure which shows an example of a structure of the bit line driver of MRM according to Embodiment 1 of this invention. FIG. 11 is a timing chart showing an operation of the bit line driver shown in FIG. 10. It is a figure which shows an example of a structure of each driver | operator of the word line of MRM according to Embodiment 1 of this invention, a source line, a back gate line, and a gate line. FIG. 13 is a timing chart showing an operation of the driver shown in FIG. 12. It is a figure which shows an example of a structure of the row selection signal and read column selection signal generation part in Embodiment 1 of this invention. It is a figure which shows roughly the structure of the application part of each driver output voltage of MRAM in Embodiment 1 of this invention. It is a figure which shows roughly the structure of the example of a change of MRAM of Embodiment 1 of this invention. It is a figure which shows roughly the structure of the principal part of MRAM according to Embodiment 2 of this invention. FIG. 18 is a flowchart showing an operation at the time of data writing of the MRAM shown in FIG. 17. FIG. 17 is a timing diagram representing an operation at the time of data writing of the MRM according to the second embodiment of the present invention. It is a figure which shows schematically the structure of the control circuit of MRAM according to Embodiment 2 of this invention. FIG. 22 is a timing chart showing an operation of the control circuit shown in FIG. 21. FIG. 18 is a diagram specifically showing the configuration of the bit line driver shown in FIG. 17. FIG. 18 is a diagram illustrating an example of a configuration of a power supply switching circuit illustrated in FIG. 17. It is a figure which shows roughly the structure of the example of a change of MRAM according to Embodiment 2 of this invention. FIG. 25 is a timing chart showing an operation of the MRAM shown in FIG. 24. It is a figure which shows roughly the structure of the sense amplifier of MRAM of the modification of Embodiment 2 of this invention. FIG. 27 schematically shows a sensing operation of the sense amplifier circuit shown in FIG. 26. FIG. 27 schematically shows a sensing operation of the sense amplifier circuit shown in FIG. 26. It is a figure which shows roughly the structure of the principal part of MRAM according to Embodiment 3 of this invention. FIG. 30 schematically shows voltages applied to a bit line, a word line, a source line, and a back gate line when data is written in the MRAM shown in FIG. 29. It is a figure which shows schematically the structure of the principal part of the example of a change of MRAM of Embodiment 3 of this invention.

Explanation of symbols

  1 memory array, 1R, 1L, 1A-1N array block, 2 bit line selection drive circuit, 3 word line selection drive circuit, 4 source line selection drive circuit, 5 back gate selection drive circuit, 6 column decode circuit, 8 bit line Precharge circuit, 7L, 7R bit line drive circuit, 11 control circuit, MC memory cell, ST selection transistor, VR magnetoresistive element, WL, WL0-WL2M word line, BL, BL0-BL2M data line, SL, SL0- SL2M source line, BGL, BGL0-BGL2M back gate line, DWR0-DWR2M word line driver, DBG0-DBG2M back gate line driver, DSR0-DSR2M source line driver, DBL2n, DBL2n + 1, DBR2n, DBR2n + 1, DB Li, DBRi bit line driver, PG2n, PG2n + 1, PGi precharge gate, 100 high side power switching circuit, 102 low side power switching circuit, 104 substrate power switching circuit, 106 source power switching circuit, 112 data latch, 114 sense amplifier circuit , 150, 160 step-down circuit, 170 constant current source, 172 MIS transistor, 174 current sense circuit, 176 selector, 200A-200N drive circuit group, 202A-202N multiplexer (MUX), 204A-204N step-down circuit (VDC), 206A- 205N selector (SEL), 208 reference voltage generation circuit, 212 high side multiplexer (HMUX), 214 low side power supply multiplexer (LMUX), 216 high side step-down circuit (HVDC), 218 Side down circuit (LVDC).

Claims (9)

Plural elements arranged in a matrix, each including a magnetoresistive memory element, a first electrode coupled to the magnetoresistive memory element, a second electrode, a selection transistor having a gate electrode and a back gate. Memory cells,
Magnetoresistive storage element of memory cell of corresponding column arranged corresponding to each memory cell column, each having first and second ends, and between the first and second ends Multiple bit lines to which
Arranged corresponding to each memory cell row, each connected to the gate electrode of the select transistor of the memory cell in the corresponding row, and divided into a plurality of blocks along the column direction in which the bit line extends Multiple word lines,
A plurality of digit lines arranged corresponding to each of the memory cell rows, each applying a current-induced magnetic field to a magnetoresistive storage element of the corresponding memory cell when selected,
A plurality of source lines arranged along a first direction of one of the memory cell rows and columns, each connected to a second electrode of a select transistor of a corresponding memory cell;
A plurality of first lines are arranged corresponding to the first ends of the respective bit lines, and each supply a first voltage to the first ends of the corresponding bit lines when selected during data writing. Bit line drivers,
A second voltage lower than the first voltage is applied to the second end of the corresponding bit line when it is arranged corresponding to the second end of each bit line and selected during the data write. A plurality of second bit line drivers to be supplied; and at the time of data writing, a difference between a voltage of a corresponding bit line and at least one of a gate electrode, a second electrode, and a back gate of a selection transistor of the memory cell The at least one of the plurality of word lines, the plurality of source lines, and the back gates of the selection transistors of the plurality of memory cells so as to be maintained at a voltage level between the first voltage and the second voltage. A thin film magnetic semiconductor memory device comprising a voltage control circuit for setting a voltage corresponding to one voltage. The voltage control circuit includes:
A plurality of word line drivers arranged corresponding to the word lines, and arranged for a word line provided for a block closest to the first end of the bit line during the data writing; A word line driver that transmits a voltage between the first and second voltages to a corresponding word line, and a word line driver arranged for a word line of a block closest to the second end is The thin film magnetic semiconductor memory device according to claim 1, wherein the second voltage level voltage is transmitted. The first direction is a row direction in which the memory cell row extends;
The plurality of source lines are arranged corresponding to the memory cell rows, and each of the source lines is connected to a second electrode of a selection transistor of a memory cell in the corresponding row,
The voltage control circuit includes:
A plurality of source line drivers provided for the plurality of source lines, and a source arranged for a source line provided for a block near the first end of the bit line during the data writing; A line driver that transmits a voltage between the first and second voltages to a corresponding source line and is arranged with respect to a source line of a block closest to the second end; 3. The thin film magnetic semiconductor memory device according to claim 1, which transmits a voltage of two voltage levels. The voltage control circuit includes:
A plurality of back gate line drivers arranged corresponding to each memory cell row, each of which commonly sets a back gate voltage of a select transistor of a memory cell of the corresponding row; A back gate line driver disposed for a memory cell in a block near the first end of the first and second voltages, and transmits a voltage between the first and second voltages to the back gate of the corresponding memory cell, and 4. The thin-film magnetic semiconductor memory device according to claim 1, wherein a back gate line driver disposed for a memory cell in a block closest to the end of the thin film transmits the voltage of the second voltage level. 5. .   5. The thin film magnetic body according to claim 1, wherein positions of the first end portion and the second end portion of the bit line are exchanged in accordance with a logical value of write data during the data writing. Semiconductor memory device.   The voltage control circuit divides the first and second voltage differences according to the distance from the first end of the bit line, and supplies the voltage to at least one of the word line, back gate, and source line of each block. The thin film magnetic semiconductor memory device according to claim 1, wherein at least one voltage is applied.   5. The thin film magnetism according to claim 1, wherein positions of the first end portion and the second end portion of the bit line are fixed at the time of data writing regardless of a logical value of write data. 6. Semiconductor memory device. The voltage control circuit includes:
A word line driver that is provided for each of the word lines and supplies a non-selected voltage to the corresponding word line at the time of data writing;
At the time of data writing, the high-side and low-side operation power supply voltages output when the word line driver arranged for the block closest to the first end of the bit line is selected and not selected are respectively set to the first voltage. And a word line drive power supply switching circuit for setting the low-side power supply voltage of the word line driver of the block farthest from the first end to the second voltage level. 8. The thin film magnetic semiconductor memory device according to claim 7, wherein a low-side power supply voltage of a corresponding word line driver is transmitted to each word line as a voltage when not selected. The voltage control circuit includes:
A word line driver provided for each of the word lines and supplying a non-selection or selection voltage to the corresponding word line;
At the time of data writing, the high-side and low-side operation power supply voltages output when the word line driver arranged for the block closest to the first end of the bit line is selected and not selected are respectively set to the first voltage. And the low side power supply voltage of the word line driver of the block closest to the second end is set to the second voltage level, and the word line drivers of the remaining blocks And a word line drive power supply switching circuit for dividing and transmitting the intermediate voltage and the second voltage according to the distance from the first end as a high-side power supply voltage, At the time of loading, the word line driver of the block closest to the second end portion transmits the low-side power supply voltage to the corresponding word line, and the word line drivers of the remaining blocks are respectively connected to the corresponding word lines. Transmitting Lee-side power supply voltage, the thin-film magnetic semiconductor memory device according to claim 7 wherein.

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