JP5966402B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit that operates with a plurality of power supply voltages.

  2. Description of the Related Art In recent years, in semiconductor integrated circuits, the withstand voltage of elements has been reduced along with miniaturization of elements such as MOSFETs (Metal Oxide Field Effect Effect Transistors: transistors of metal-oxide film-semiconductor structure; simply referred to as transistors hereinafter). There is a need to lower the power supply voltage of semiconductor integrated circuits. For example, when the processing technology of the device is about 350 nm, the power supply voltage of the semiconductor integrated circuit is 3 V to 5 V. However, as the processing technology is miniaturized to 130 nm and 65 nm, the withstand voltage of the device decreases, and the semiconductor integrated circuit The power supply voltage is decreasing to 1.8V and 1.2V.

  However, in a system including an analog circuit that drives a liquid crystal, a sensor, or the like, a 3V power source or a 5V power source is necessary to operate the analog circuit. For this reason, when configuring an LSI chip including this type of analog circuit, the miniaturized internal circuit is operated with a low voltage power supply such as 1.2 V, and the analog circuit and the input / output interface circuit are driven with 3 V to 5 V. It is necessary to adopt a multi-power supply configuration such as a

  In addition, nonvolatile memories such as flash memory and EEPROM (Electrically Erasable and Programmable Read Only Memory) are used for many purposes because information does not disappear even when the power is turned off. However, this type of nonvolatile memory requires a high voltage for writing and erasing data. Therefore, this type of non-volatile memory also employs a multi-power supply configuration.

JP 2006-140211 A

  Conventionally, logic circuits that require high-speed operation and require finer technology due to the large number of elements are composed of low-voltage transistors with thin oxide films, and input / output interface circuits and high-voltage circuits have thick oxide films. The high voltage transistor was used.

  Thus, under the conventional technology, it was necessary to make a high voltage transistor in addition to the standard transistor corresponding to miniaturization. For this reason, it is necessary to manufacture a transistor by changing a plurality of types of oxide film thicknesses, and the number of processes is large and the process is expensive. In addition, since the manufacturing process is complicated, it is necessary to pay attention to the yield. In addition, since the process is expensive and the yield is low, there is a problem that the price of the product increases.

  In addition, when making a product composed of a single nonvolatile memory, there is only a problem that the price of the memory is increased. However, a so-called embedded (non-volatile memory) in which a nonvolatile memory and a logic circuit or an analog circuit are mixedly mounted on the same chip. In the case of Embedded products, a more important problem arises. In other words, in addition to the fine standard transistor that constitutes the memory, in order to construct a high breakdown voltage transistor with a thick oxide film, the thermal process of the process is changed, and the characteristics of the standard transistor that constitutes the memory also change. Occur. In particular, analog circuits such as memory sense amplifiers are sensitive to transistor characteristics, and each time the transistor characteristics change, tuning is required. For this reason, there is a problem that a large loss occurs in a semiconductor manufacturer having many analog IPs.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a semiconductor integrated circuit that can be realized by a standard CMOS process that can be miniaturized and that can operate at a high voltage. To do.

  According to the present invention, a nonvolatile memory cell array composed of a plurality of nonvolatile memory cells respectively connected to any one of a plurality of bit lines, and a data node and a plurality of bit lines are interposed, and at the time of writing or reading Column selection means for connecting a bit line connected to a nonvolatile memory cell to be accessed to the data node, a data control transistor having a drain connected to a power supply node and a source connected to a write voltage generation node, and writing A write circuit that controls a gate voltage of the data control transistor according to a signal; a data control switch that is a CMOS switch interposed between the write voltage generation node and the data node; and the data circuit according to a data signal And an input circuit for switching ON / OFF of the data control switch. When the data control transistor switches ON / OFF of the data control transistor by controlling the gate voltage to the data control transistor and turns on the data control transistor, the write operation is performed from the power supply node via the data control transistor. A semiconductor integrated circuit is provided, wherein a voltage applied to a voltage generation node is suppressed by a gate voltage with respect to the data control transistor. The data control transistor also has the function of the data control switch, and the input circuit also has the function of the write circuit, and the input circuit turns on / off the data control transistor according to the data signal. When the data control transistor is turned on, the voltage applied to the data node from the power supply node via the data control transistor may be suppressed by the gate voltage with respect to the data control transistor.

  According to the present invention, since the data control transistor serves as a means for relaxing the voltage, a semiconductor integrated circuit capable of high voltage operation can be realized by a standard CMOS process that can be miniaturized.

It is a figure which shows the oxide film thickness of the transistor in the MOS integrated circuit corresponding to various power supply voltages, and the limiting pressure | voltage resistance of the oxide film. It is sectional drawing which shows the structure of the CMOS circuit manufactured by the standard CMOS process. It is sectional drawing which shows the structural example of the high voltage | pressure-resistant CMOS circuit which expanded the LDD area | region of both the drain and the source, and improved the proof pressure. It is sectional drawing which shows the structural example of the high voltage | pressure-resistant CMOS circuit which expanded only the LDD area | region of the drain and improved the proof pressure. It is sectional drawing which shows the structure of a floating gate type non-volatile memory cell. It is a figure which shows operation | movement of the non-volatile memory cell. It is a circuit diagram which shows the structure of the non-volatile memory cell array comprised by the non-volatile memory cell. 1 is a circuit diagram showing a configuration of a circuit for column selection that is a part of a nonvolatile memory according to a first embodiment of the present invention; FIG. 3 is a cross-sectional view showing a state of the data control transistor 1 in the same embodiment. FIG. 2 is a circuit diagram showing a configuration example of a write circuit 10 in the same embodiment. FIG. 2 is a circuit diagram showing a configuration example of an input circuit 20 in the same embodiment. FIG. It is a circuit diagram which shows the structure of the circuit for column selection which is a part of the non-volatile memory which is 2nd Embodiment of this invention. 2 is a circuit diagram showing a configuration example of an input circuit 200 in the same embodiment. FIG. It is a circuit diagram which shows the structural example of the input circuit which is a part of non-volatile memory which is 3rd Embodiment of this invention. It is a circuit diagram which shows the operation state at the time of reading of the input circuit. FIG. 3 is a circuit diagram showing a configuration example of a regulator for generating a power supply voltage in the same embodiment. It is a circuit diagram which shows the structural example of the column decoder which is a part of non-volatile memory which is 4th Embodiment of this invention. It is a circuit diagram which shows the operation state at the time of writing of the same column decoder. It is a circuit diagram which shows the operation state at the time of the reading of the same column decoder. It is a circuit diagram which shows the structure of the circuit for column selection of the non-volatile memory which is a comparative example with respect to this invention. It is a wave form diagram which shows operation | movement of the comparative example. It is a wave form diagram which shows operation | movement of the non-volatile memory which is 1st Embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

<High breakdown voltage technology used in each embodiment>
Each embodiment of the present invention uses a high withstand voltage technique that is generally used in CMOS circuits. Therefore, prior to the description of the embodiments of the present invention, a technique for increasing the breakdown voltage of the CMOS circuit will be described.

  FIG. 1 shows the oxide film thickness of a transistor in a MOS integrated circuit corresponding to various power supply voltages and the limiting breakdown voltage (voltage that breaks down the gate oxide film in a certain time). Usually, in order to realize a MOS integrated circuit capable of guaranteeing operation for 10 years, the electric field applied to the oxide film is set to about 5 MeV (megaelectron volts), but the upper limit of the electric field that can be applied to the oxide film Is set to approximately 8 MeV.

  FIG. 2 is a cross-sectional view showing a configuration of a CMOS circuit manufactured by a standard CMOS process. This CMOS circuit employs an LDD (Lightly Doped Drain) structure in order to suppress the generation of hot electrons and improve the reliability of the transistor. This LDD structure is a structure in which a low-concentration impurity region is provided between a source, a drain and a channel so that a high electric field is not concentrated here. In order to form a transistor having an LDD structure, a side wall (generally an oxide film) is added to the side wall of the gate of the transistor, and n− or p− is set using the gate with the side wall added as a mask. Injected by implantation. In this case, the transistor can be manufactured by self-alignment, and the required area of the transistor is not increased. For example, when a CMOS circuit having a gate breakdown voltage of 5V is realized by the configuration shown in FIG. 2, the oxide film is set to a thickness of about 90 mm (angstrom), and the breakdown voltage (TDDB: Time Dependent Dielectric Breakdown) is set to about 6V. . In this case, the drain breakdown voltage (Breakdown) is about 7V.

FIG. 3 is a cross-sectional view showing a configuration example of an HVDMOS (High Level Voltage Drain Metal Oxide Semiconductor) transistor in which both the drain and source breakdown voltages of the CMOS circuit shown in FIG. 2 are improved. In this high voltage CMOS circuit, the LDD region (n ⁻ or p ⁻ region) in FIG. 2 is wide. By doing so, the drain breakdown voltage can be easily increased to 10 V or more. However, this configuration has the disadvantage that the gate and the diffusion region need to be sufficiently wide, and the layout area becomes large. As shown in FIG. 3, the structure of a P-channel transistor and an N-channel transistor in which both the drain and source LDD regions are expanded is called a double-sided high breakdown voltage structure.

  FIG. 4 is a cross-sectional view showing a configuration example of an HVDMOS transistor adopting a high breakdown voltage structure in which only the LDD region on the drain side of each channel transistor of the CMOS circuit shown in FIG. 2 is expanded. This configuration example has an advantage that the area increase is suppressed as compared with the configuration example of FIG. The structure of the P channel transistor and the N channel transistor shown in FIG. 4 is called a one-side high breakdown voltage structure. A technique for increasing the breakdown voltage of a circuit using this one-side high breakdown voltage transistor is disclosed in Patent Document 1, for example.

<Configuration of Nonvolatile Memory in Each Embodiment>
FIG. 5 is a cross-sectional view showing the configuration of an N-channel floating gate transistor used as a nonvolatile memory cell in each embodiment of the present invention. As shown in FIG. 5, the N-channel floating gate transistor has a floating gate FG arranged in an oxide film between a gate and a region between a source and a drain formed on a substrate (Pwell in the example shown in FIG. 5). It becomes the composition.

  FIG. 6 is a diagram showing an operation of the nonvolatile memory cell shown in FIG. At the time of writing (Program), for example, a voltage VD = 5V is applied to the drain of an N-channel floating gate transistor which is a nonvolatile memory cell to which data “1” is to be written via the bit line BIT, a voltage VS = 0V is applied to the source A voltage VG = 10 V is applied to the Pwell and 0 V is applied to the Pwell. As a result, electrons are injected into the floating gate FG, the threshold voltage of the N-channel floating gate transistor rises, and data “1” is written. Here, the N-channel floating gate transistor to which data “1” has not been written is in a state where electrons are not injected into the floating gate FG, the threshold voltage is low, and data “0” is stored. .

  At the time of erasing (Erase), the drain voltage VD, source voltage VS, and Pwell of the N-channel floating gate transistor are set to 10V, and the gate voltage VG is set to 0V or a negative voltage. As a result, electrons are extracted from the floating gate FG to Pwell and erased (that is, data “0” is stored).

  At the time of reading (Read), the drain voltage VD of the N-channel floating gate transistor is 0.6 V, the source voltages VS and Pwell are 0 V, the gate voltage VG is 3 V to 5 V, and the drain that flows through the bit line BIT at that time By determining the current, it is determined whether the N-channel floating gate transistor stores data “1” or “0”. Here, the drain voltage VD is set to a low voltage of about 0.6 V in order to prevent erroneous writing.

  FIG. 7 is a circuit diagram showing a configuration of a nonvolatile memory cell array used in each embodiment of the present invention. This nonvolatile memory cell array is formed by arranging the nonvolatile memory cells shown in FIG. 5 in a matrix. In the example shown in FIG. 7, the nonvolatile memory is associated with each intersection of the word line WLi (i = 0 to m) wired in the row direction and the bit line BITj (j = 0 to n) wired in the column direction. N-channel floating gate transistors, which are cells, are respectively disposed.

  Here, the gates of n + 1 N-channel floating gate transistors in the i-th row are connected to the i-th row word line WLi. The drains of m + 1 N-channel floating gate transistors in the j-th column are connected to the bit line BITj in the j-th column. In the illustrated example, the N-channel floating gate transistors in two adjacent rows (for example, the 0th row and the 1st row,..., The (m−1) th row and the mth row) have a common source, A source voltage VS is supplied to the common source via a common source line.

<First Embodiment>
FIG. 8 is a circuit diagram showing a configuration of a circuit for column selection which is a part of the nonvolatile memory according to the first embodiment of the present invention. In FIG. 8, bit lines BITj (j = 0 to n) are connected to the nonvolatile memory cell array shown in FIG. The nonvolatile memory includes a row decoder that selects one word line WLi indicated by a row address from m + 1 word lines WLi (i = 0 to m) in the nonvolatile memory cell array shown in FIG. However, the illustration is omitted.

  In FIG. 8, a write circuit 10 is a circuit that receives a write signal WE and outputs a write voltage WEN. The input circuit 20 is a circuit that receives the data signal Dinh (h = 0 to 15) and outputs selection voltages DINph and DINnh, respectively. Here, the selection voltages DINph and DINnh are complementary and symmetrical voltages, and when one is at a high level, the other is at a low level.

  As shown in FIG. 4, the data control transistor 1 is an N-channel transistor having a one-side high breakdown voltage structure in which only the drain LDD region is expanded. A high voltage VPP = 8 V output from a charge pump (not shown) is applied to the drain of the data control transistor 1, and a write voltage WEN is applied to the gate. The source of the data control transistor 1 is connected to a write voltage generation node NW that generates a write voltage VDP.

  The data control switch 2 is a CMOS switch composed of a P-channel transistor 2p and an N-channel transistor 2n, and is interposed between the write voltage generation node NW and the data node NA. Here, selection voltages DINph and DINnh are applied to the gates of P-channel transistor 2p and N-channel transistor 2n, respectively. When the data signal Dinh to be written is “0”, the input circuit 20 outputs selection voltages DINph and DINnh for turning off the data control switch 2 including the P-channel transistor 2p and the N-channel transistor 2n, and the data signal When Dinh is “1”, selection voltages DINph and DINnh for turning on the data control switch 2 are output.

  q + 1 first column decoders 30-x (x = 0 to q), k + 1 second column decoders 40-y (y = 0 to k), a first column switch unit 33, and a second column switch As a whole, the unit 34 selects one bit line BITj corresponding to the column indicated by the column address YADD from the n + 1 bit lines BITj (j = 0 to n), and selects a column connected to the data node NA. Means.

  More specifically, in this embodiment, there is a relationship of n + 1 = (k + 1) (q + 1) among the number n + 1 of bit lines, the number q + 1 of the first column decoders, and the number k + 1 of the second column decoders. Yes, n + 1 bit lines BITj (j = 0 to n) are divided into q + 1 groups each of k + 1 bit lines. Then, the second column decoder 40-y (y = 0 to k) and the second column switch unit 34, for each q + 1 groups x each consisting of k + 1 bit lines, for example, in the lower digit of the column address YADD. Based on this, one bit line in the group x is selected and connected to the intermediate node NBx.

  Specifically, P channel transistors 4p0y (y = 0 to k) and N are connected between the k + 1 bit lines BIT0 to BITk belonging to the first group x = 0 and the intermediate node NB0 corresponding to the group. Each of k + 1 column selection gates is inserted by a CMOS switch including channel transistors 4n0y (y = 0 to k). Further, between the k + 1 bit lines BITn-k to BITn belonging to the last group x = q and the intermediate node NBq corresponding to the group, a P channel transistor 4pqy (y = 0 to k) and an N channel are respectively provided. Each of k + 1 column selection gates by a CMOS switch including transistors 4nqy (y = 0 to k) is inserted. The same applies to other groups, and k + 1 column selection gates by CMOS switches are interposed between k + 1 bit lines belonging to the group and the intermediate node.

  On the other hand, two column selection lines COLBp0 and COLBn0 are connected to the second column decoder 40-0. Here, the column selection line COLBp0 is a column selection gate connected to the first bit line in each of the k + 1 groups (in the illustrated example, the bit line BIT0 in the first group, the bit line BITn-k in the last group). The column select line COLBn0 is connected to the gate of the N channel transistor 4nx0 (x = 0 to q) of the same column select gate. In addition, two column selection lines COLBp1 and COLBn1 are connected to the column decoder 40-1. Here, the column selection line COLBp1 is the column selection connected to the second bit line in each of the k + 1 groups (in the example shown, the bit line BIT1 in the first group, the bit line BITn−k + 1 in the last group). The gate is connected to the gate of the P-channel transistor 4px1 (x = 0 to q), and the column selection line COLBn1 is connected to the gate of the N-channel transistor 4nx1 (x = 0 to q) of the same column selection gate. The same applies to the other column decoders 40-2 to 40-k and the column selection lines connected to them.

  The second column decoder 40-y (y = 0 to k) is associated with each value y that can be taken by the lower digits of the column address YADD. When the lower digit of the column address YADD indicates 1, for example, the column decoder 40-1 outputs a column selection voltage for turning on the column selection gate of the second column switch unit 34 to the column selection lines COLBp1 and COLBn1. On the other hand, the column decoders other than the column decoder 40-1 each output a column selection voltage for turning off the column selection gate connected to each other via the column selection line. As a result, only the column selection gate connected to the second bit line in each of the k + 1 groups is turned ON, and the bit lines BIT1,..., BITn−k + 1 are connected to the intermediate nodes NB0 to NBq, respectively.

  Further, the first column decoder 30-x (x = 0 to q) and the first column switch unit 33 are connected to the q + 1 intermediate nodes NBx (x = 0 to q) based on, for example, the upper digit of the column address YADD. A circuit that selects one intermediate node NBx from among them and connects to the data node NA is configured.

  Specifically, in the first column switch unit 33, between each of the intermediate nodes NBx (x = 0 to q) and the data node NA, the P channel transistor 3px (x = 0 to q) and the N channel transistor 3nx. Q + 1 column selection gates are inserted by CMOS switches each including (x = 0 to q).

  On the other hand, two column selection lines COLAp0 and COLAn0 are connected to the column decoder 30-0. Here, the column selection line COLAp0 is connected to the gate of the P-channel transistor 3p0 of the column selection gate connected to the first intermediate node NB0, and the column selection line COLAn0 is connected to the gate of the N-channel transistor 3n0 of the same column selection gate. ing.

  Further, two column selection lines COLApq and COLAnq are connected to the last column decoder 30-q. Here, the column selection line COLApq is connected to the gate of the P-channel transistor 3pq of the column selection gate connected to the last intermediate node NBq, and the column selection line COLAnq is connected to the gate of the N-channel transistor 3nq of the same column selection gate. ing. The same applies to the other column decoders 30-x (x = 1 to q-1) and the column selection lines connected to them.

  The first column decoder 30-x (x = 0 to q) is associated with each value x that can be taken by the upper digits of the column address YADD. When the upper digit of the column address YADD indicates 0, for example, the first column decoder 30-0 outputs column selection voltages for turning on the column selection gates of the first column switch unit 33 to the column selection lines COLAp0 and COLAn0, respectively. On the other hand, the first column decoders other than the first column decoder 30-0 each output a column selection voltage for turning off the column selection gate connected to each other via the column selection line. As a result, only the column selection gate connected to the intermediate node NB0 is turned ON, and the intermediate node NB0 is connected to the data node NA.

  Next, the operation of this embodiment will be described. When the write signal WE is at a high level, the write circuit 10 outputs, as the write voltage WEN, a voltage 5V + Vthn≈7V obtained by adding the threshold voltage Vthn of the data control transistor 1 to the target write voltage 5V to the gate of the data control transistor 1 To do. Here, since the data control transistor 1 adopts a one-side high breakdown voltage structure in which the drain side (VPP) LDD is expanded, there is no problem in breakdown voltage.

  When 5V + Vthn (≈7V) is applied to the gate of the data control transistor 1, VSn = 5V + Vthn−Vthn = 5V is output to the source as shown in FIG. Here, in the data control transistor 1, since the source potential is 5V, the inversion layer has a potential of 5V or more, the depletion layer is expanded, and an electric field is hardly applied between the gate and the Pwell. Therefore, there is no problem with the withstand voltage between the gate and Pwell. Therefore, the data control transistor 1 can be configured by a low breakdown voltage gate MOS transistor.

  In this embodiment, the data control switch 2 is a CMOS switch, and all the switches of the first column switch unit 33 and the second column switch unit 34 are also CMOS switches. Therefore, when the data control switch 2 is turned on, the CMOS switch between the data node NA and the bit line BITj indicated by the column address is turned on, and the bit line BITj is selected, the voltage of the write voltage generation node NW 5V is supplied to the bit line BITj through each CMOS switch with almost no drop. At that time, the drain voltage and the source voltage of each CMOS switch between the data node NA and the bit line BITj indicated by the column address are 5 V, but the inversion layer formed in each transistor constituting these CMOS switches is 5 V. Therefore, there is no problem with the withstand voltage.

  As described above, according to the present embodiment, each CMOS switch interposed between the bit line BITj (j = 0 to n) and the write voltage generation node NW can be configured by only a transistor having a low breakdown voltage.

  FIG. 10 is a circuit diagram showing a specific configuration example of the write circuit 10 in FIG. 10, the charge pump 12 is a circuit that outputs a write voltage WEN to the gate of the data control transistor 1 in FIG.

  The gate and drain of the N channel transistor 11 are connected to the output terminal of the charge pump 12, and resistors R1 and R2 are connected in series between the source of the N channel transistor 11 and the low potential side power supply node VSS = 0V. It is connected. The N-channel transistor 11 functions as a voltage shift means for generating a voltage, which is reduced by a voltage corresponding to the threshold voltage Vthn of the data control transistor 1 from the voltage at the output terminal of the charge pump 12, at both ends of the series circuit composed of the resistors R1 and R2. .

  The comparator 13 compares the voltage at the node N11 between the resistors R1 and R2 with the reference voltage VREF = 1.5V, and outputs a low level when the voltage at the node N11 is higher than the reference voltage VREF, and outputs a high level when the voltage is low. . In this example, the resistance ratio of the resistors R1 and R2 is determined so that the voltage obtained by dividing 5V by the resistors R1 and R2 is 1.5V. The NAND gate 14 outputs a low level when both the write signal WE and the output signal of the comparator 13 are at a high level, and outputs a high level otherwise. The charge pump 12 is a circuit that increases the write voltage WEN by performing an operation of supplying charges to the generation node of the write voltage WEN while the output signal of the NAND gate 14 is at a low level.

  According to this configuration, when the write signal WE becomes a high level, the nonvolatile memory performs a write operation. At this time, if the voltage of the node N11 is lower than the reference voltage VREF = 1.5V and the output signal of the comparator 13 is at a high level, the output signal of the NAND gate 14 is at a low level, the charge pump 12 operates, and writing is performed. The voltage WEN increases. When the write voltage WEN becomes 5V + Vthn or more, the source voltage of the N-channel transistor 11 becomes 5V or more, and the voltage of the node N11 becomes the reference voltage VREF = 1.5V or more. As a result, the output signal of the comparator 13 becomes Low level, the output signal of the NAND gate 14 becomes High level, the charge pump 12 stops operating, and the write voltage WEN decreases. If the write voltage WEN is slightly lower than 5V + Vthn, the charge pump 12 starts again. Thus, the resistors R1 and R2, the comparator 13, and the NAND gate 14 operate as negative feedback control means for maintaining the write voltage WEN at 5V + Vthn.

  FIG. 11 is a circuit diagram showing a configuration example of the input circuit 20 shown in FIG. In FIG. 11, the input circuit 20 includes an NADN gate 29, a level shifter LS, and inverters 21 and 22.

  11 shows not only the input circuit 20 shown in FIG. 8, but also the first column decoder 30 and the second column decoder 40 shown in FIG. The first column decoder 30 and the second column decoder 40 have a configuration in which the NAND gate 29 in the input circuit 20 is replaced with an address match detection circuit YDET. The address match detection circuit YDET outputs a low level when the upper digit or lower digit of the column address is a value corresponding to the first column decoder 30 or the second column decoder 40, and outputs a high level otherwise. Circuit.

  In the input circuit 20 shown in FIG. 11, the NAND gate 29 is supplied with the high potential side power supply voltage 3V and the low potential power supply voltage 0V. The NAND gate 29 outputs a signal that is at a low level (0 V) when both the write signal WE and the data signal Dinh are at a high level, and at a high level (3 V) otherwise.

  In the level shifter LS, the inverters 23 and 24 are both CMOS inverters, and are supplied with the high potential side power supply voltage VD3 = 3V and the low potential side power supply voltage VSS = 0V. The inverter 23 logically inverts and outputs the output signal of the NAND gate 29, and the inverter 24 logically inverts and outputs the output signal of the inverter 23.

  P channel transistors 25 and 26 have their sources connected to a high potential side power supply node to which power supply voltage VD5 is applied. P channel transistors 25 and 26 have their respective drains connected to their gates.

The N-channel transistor 27 has a drain connected to a common connection node N22 of the drain of the P-channel transistor 25 and the gate of the P-channel transistor 26, a source connected to the low potential side power supply node VSS, and a gate connected to the output node of the inverter 23. It is connected. The N-channel transistor 28 has a drain connected to the common connection node N21 of the drain of the P-channel transistor 26 and the gate of the P-channel transistor 25, a source connected to the low potential side power supply node VSS, and a gate connected to the output of the inverter 24. Connected to the node.
The above is the configuration of the level shifter LS.

  The inverter 21 includes a P-channel transistor 21P and an N-channel transistor 21N that are inserted in series between the high-potential-side power supply VD5 and the low-potential-side power supply VSS. Here, each gate of the P-channel transistor 21P and the N-channel transistor 21N is connected to a node N21 in the level shifter LS. The inverter 21 logically inverts the signal at the node N21 and outputs it as the selection voltage DINhp.

The inverter 22 includes a P-channel transistor 22P and an N-channel transistor 22N that are inserted in series between the high-potential power supply VD5 and the low-potential power supply VSS. Here, each gate of the P-channel transistor 22P and the N-channel transistor 22N is connected to a node N22 in the level shifter LS. The inverter 22 logically inverts the signal at the node N22 and outputs it as the selection voltage DINhn.
The above is the configuration of the input circuit 20.

  In the nonvolatile memory according to the present embodiment, the high-potential-side power supply voltage VD5 is 3V during the read operation and 5V during the write operation.

During the write operation, the write signal WE becomes High level, and at the same time, the high potential side power supply voltage VD5 of the level shifter LS and the inverters 21 and 22 becomes 5V. At this time, the high potential side power supply voltage of the NAND gate 29 and the inverters 23 and 24 is VD3 = 3V.
When the data signal Dinh is “1” (High level), the output signal DIh of the NAND gate 29 is Low level, the node N21 of the level shifter LS is High level (≈5V), and the node N22 is Low level (≈0V). Become. For this reason, the inverter 21 outputs 0V as the selection voltage DINhp, and the inverter 22 outputs 5V as the selection voltage DINhn. As a result, the data control switch 2 composed of the transistors 2n and 2p in FIG. 8 is turned ON, and a 5V write voltage is supplied to the bit line BITj selected by the column address.

  When the data signal Dinh is “0”, the operation is reversed, the CMOS switch composed of the transistors 2n and 2p is turned off, and no write voltage is supplied to the bit line BITj indicated by the column address.

  At the time of reading, the write signal WE becomes Low level, and at the same time, the high potential side power supply voltage VD5 of the level shifter LS and the inverters 21 and 22 is switched to 3V. Since the write signal WE is at the low level, the selection voltage DINhp output from the inverter 21 is 3V, the selection voltage DINhn output from the inverter 22 is 0V, and the data control switch 2 is always OFF regardless of the data signal Dinh.

  When the circuit described above is used for the column decoder, the NAND gate 29 is replaced with the address match detection circuit YDET as described above. In this configuration, when the upper digit or the lower digit of the column address becomes a value corresponding to the column decoder, the output signal YDEC of the address match detection circuit YDET becomes the low level. As a result, the inverter 21 outputs, for example, a low level column selection voltage COLAp that turns on the P-channel transistor of the CMOS switch of the column switch unit 33, and the inverter 22 outputs the N-channel transistor of the CMOS switch of the column switch unit 33. A high level column selection voltage COLAn to be turned on is output.

Second Embodiment
FIG. 12 is a circuit diagram showing a configuration of a circuit for column selection which is a part of the nonvolatile memory according to the second embodiment of the present invention. In FIG. 12, the input circuit 200 has both functions of the input circuit 20 and the write circuit 10 in FIG. The input circuit 200 generates a write voltage DINh at the gate of the data control transistor 1 based on the write signal WE and the data signal Dinh. In FIG. 12, the data control transistor 1 also has the functions of the data control transistor 1 and the data control switch 2 in FIG. Since other configurations are the same as those in FIG. 8, the same reference numerals are used.

  Next, the operation of this embodiment will be described. The input circuit 200 sets the write voltage DINh to 5V + Vthn when the write signal WE is in a write state in which the level is high and the data signal Dinh is in the high level. As a result, as in the first embodiment (FIG. 8), the data control transistor 1 is turned on, and the write voltage 5V is generated at the data node NA. Here, the first column decoders 30-0 to 30-q turn on one CMOS switch in the first column switch unit 33, and one of the second column decoders 40-0 to 40-k is the second column switch unit. The q + 1 CMOS switches in 34 are turned ON, and the bit line BITj of the column indicated by the column address YADD is connected to the data node NA. As a result, 5V is output to the bit line BITj of the column indicated by the column address YADD.

  On the other hand, when the data signal Dinh is at the low level, the write voltage DINh is 0 V, so that the data node NA is in a floating state. Therefore, no voltage is applied to the bit line BITj indicated by the column address YADD, and no data is written to the nonvolatile memory cell.

  FIG. 13 is a circuit diagram showing a specific configuration example of the input circuit 200 in the present embodiment. The input circuit 200 is different from the input circuit 20 shown in FIG. 10 in that an AND gate 15 and an N-channel transistor 16 are added.

  The AND gate 15 sets the signal WEN to the high level when both the write signal WE and the data signal Dinh are at the high level, and sets the signal WEN to the low level otherwise. The NAND gate 14 outputs a low level when both the signal WEN and the output signal of the comparator 13 are at a high level, and outputs a high level otherwise. The N-channel transistor 16 is interposed between a node from which the charge pump 12 outputs the write voltage DINh and the low potential side power source VSS. An inverted signal WENB of the signal WEN is input to the gate of the N channel transistor 16.

  In the input circuit 200, when writing, when the write signal WE becomes High level and the data signal Dinh becomes High level, the signal WEN becomes High level and the signal WENB becomes Low level. In this state, when the voltage of the node N11 is lower than the reference voltage VREF = 1.5V and the output signal of the NAND gate 14 becomes low level, the charge pump 12 operates to increase the write voltage DINh. On the other hand, when the voltage of the node N11 is higher than the reference voltage VREF = 1.5V and the output signal of the NAND gate 14 becomes High level, the charge pump 12 is stopped and the write voltage DINh is lowered. By such an operation, the write voltage DINh is maintained at 5V + Vthn.

  On the other hand, when the data signal Dinh is at the low level, the signal WEN is at the low level and the signal WENB is at the high level. For this reason, the output signal of the NAND gate 14 becomes a high level and the operation of the charge pump 1 is stopped, and at the same time, the N-channel transistor 16 is turned on. As a result, the write voltage DINh becomes 0V. Thus, ON / OFF of the data control transistor 1 in FIG. 12 is controlled based on the data signal Dinh.

  In this embodiment, since the charge pump 12 is directly controlled by the data signal Dinh, it takes time for the waveform of the write voltage DINh to stabilize. In addition, it is necessary to provide the charge pump 12 for the number of bits of data to be simultaneously written, which increases the layout area. However, this embodiment has an advantage that the input circuit and the write circuit in the first embodiment are simplified and the configuration of the nonvolatile memory is simple.

<Third Embodiment>
In this embodiment, the input circuit 200 (FIG. 12) in the second embodiment is replaced with the input circuit shown in FIG. In FIG. 14, high potential power supply voltage VD3 and low potential power supply voltage VS (0 V) are applied to NAND gate 210 and inverter 209 in level shifter 220. The NAND gate 210 outputs a low level when both the write signal WE and the data signal Dinh are at a high level, and outputs a high level in other cases.

  In level shifter 220, P-channel transistors 201 and 202 have their sources connected to a high potential side power supply node to which power supply voltage VPP is applied. P channel transistors 201 and 202 have their respective drains connected to their gates.

  Each of the P-channel transistors 203 and 204 is a one-side high breakdown voltage transistor in which only the drain LDD region is expanded. The source of the P-channel transistor 203 is connected to the common connection node N 1 between the drain of the P-channel transistor 201 and the gate of the P-channel transistor 202. Further, the source of the P channel transistor 204 is connected to the common connection node N <b> 2 between the drain of the P channel transistor 202 and the gate of the P channel transistor 201. A bias voltage VBIAS2 is applied to the gates of P-channel transistors 203 and 204.

  The NAND gate 210 in the previous stage of the N-channel transistors 205 and 206, the inverter 209, and the level shifter 220 has one drain of the P-channel transistor 203 or 204 and a low potential side power supply node (VS = 0V) according to the output signal of the NAND gate 210. ) Is configured to form a current path. Further details are as follows.

  Each of N-channel transistors 205 and 206 is a one-side high breakdown voltage transistor in which only the drain LDD region is expanded, and each drain is connected to each drain of P-channel transistors 203 and 204, respectively. The source of the N channel transistor 205 is connected to the output node N3 of the NAND gate 210, and the source of the N channel transistor 206 is connected to the output node N4 of the inverter 209. A bias voltage VBIAS3 is applied to each gate of N channel transistors 205 and 206. N-channel transistors 205 and 206 to which the bias voltage VBIAS3 is applied at the gate serve to regulate the voltages at nodes N3 and N4 to which the sources are connected so as not to exceed power supply voltage VD3 = 3V.

  P channel transistor 207 has its source and drain connected to the source and drain of P channel transistor 201, respectively. P channel transistor 208 has its source and drain connected to the source and drain of P channel transistor 202, respectively. Bias voltage VBIAS1 is applied to each gate of P channel transistors 207 and 208. The bias voltage VBIAS1 is a voltage shifted from the voltage VPP by the threshold voltage Vthp of the P-channel transistors 207 and 208 to the low potential side power supply voltage VSS = 0V side.

  A slight drain current flows through P channel transistors 207 and 208 to which the bias voltage VBIAS1 is applied at the gate. In the circuit shown in FIG. 14, when leak current flows through P channel transistors 203 and 204, the voltages at nodes N1 and N2 drop. P-channel transistors 207 and 208 serve to compensate for voltage drops at nodes N1 and N2 due to leakage current by replenishing nodes N1 and N2 with a small drain current flowing therethrough.

The buffer 230 includes a P-channel transistor 231 and an N-channel transistor 232. Each of these transistors 231 and 232 is a one-side high breakdown voltage transistor in which only the drain LDD region is expanded. The P channel transistor 231 has a source connected to the high potential side power supply VPP and a gate connected to the node N1 in the level shifter 220. The N-channel transistor 232 has a source connected to the low potential power source VSS and a gate connected to the output node N3 of the NAND gate 210. The drains of the transistors 231 and 232 are commonly connected, and the write voltage DINh is output from the common connection node to the gate of the data control transistor 1 in FIG.
The above is the configuration of the input circuit according to the present embodiment.

  Next, the operation of this embodiment will be described. During the write operation, as shown in FIG. 14, the level shifter 220 and the buffer 230 are supplied with 5V + Vthn≈7V, which is the power supply voltage VPP obtained by adding the threshold voltage Vthn of the data control transistor 1 (see FIG. 12) to 5V. It is done. Bias voltage VBIAS1 for level shifter 220 is set to a voltage VPP−Vthp = 5 V obtained by subtracting threshold voltage Vthp of P-channel transistors 207 and 208 from power supply voltage VPP. The bias voltage VBIAS2 is 3V-Vthp obtained by subtracting the threshold voltage Vthp of the P-channel transistors 203 and 204 from 3V. The bias voltage VBIAS3 is 3V.

  In this case, when the voltage at the node N1 is to be lower than 3V, the P-channel transistor 203 is turned OFF because the gate-source voltage is lower than the threshold voltage Vthp. Further, the P-channel transistor 204 is turned OFF because the gate-source voltage becomes lower than the threshold voltage Vthp when the voltage at the node N2 becomes lower than 3V. Thus, P channel transistors 203 and 204 to which bias voltage VBIAS2 is applied to the gate serve to lower the lower limit voltage of nodes N1 and N2 to 3V.

  When the data signal Dinh becomes “1” (3V), the node N3 becomes 0V and the node N4 becomes 3V. Accordingly, the gate voltage VGn = 0V is supplied to the N-channel transistor 232 of the buffer 230. Since the node N3 is 0V and the node N4 is 3V, the N-channel transistor 205 is turned on, the N-channel transistor 206 is turned off, the P-channel transistor 203 is turned on, and the P-channel transistor 204 is turned off. Therefore, the node N1 is 3V, and the node N2 is VPP (5V + Vthn≈7V). Therefore, the gate voltage VGp = 3V is supplied to the P-channel transistor 231 of the buffer 230. As a result, in the buffer 230, the P-channel transistor 231 is turned ON, the N-channel transistor 232 is turned OFF, and the write voltage DINh becomes VPP (5V + Vthn≈7V).

  When the data signal Dinh becomes “0” (0V), the node N3 becomes 3V and the node N4 becomes 0V. Therefore, the gate voltage VGn = 3V is supplied to the N-channel transistor 232 of the buffer 230. Since the node N3 is 3V and the node N4 is 0V, the N-channel transistor 205 is OFF, the N-channel transistor 206 is ON, the P-channel transistor 203 is OFF, and the P-channel transistor 204 is ON. Therefore, the node N1 is 7V, the node N2 is 3V, and the gate voltage VGp = VPP (5V + Vthn≈7V) is supplied to the P-channel transistor 231 of the buffer 230. As a result, in the buffer 230, the P-channel transistor 231 is turned OFF, the N-channel transistor 232 is turned ON, and the write voltage DINh becomes 0V.

  Thus, according to the present embodiment, the gate-substrate voltage VGB applied to all the transistors can be set to 5 V or less, and 0 V and 5 V + Vthn (≈7 V) can be output as the write voltage DINh.

  In the present embodiment, transistors 207 and 208 functioning as constant current sources are provided in order to prevent the voltages at the nodes N1 and N2 from being lowered due to the leakage current. However, another circuit may be used as the constant current source, and a simple resistor may be used instead of the transistors 207 and 208 as long as the control of the leakage current does not become a problem.

  Next, with reference to FIG. 15, the operation at the time of reading in this embodiment will be described. FIG. 15 shows voltages at various parts during the read operation. As shown in FIG. 15, during the read operation, the power supply voltage VPP for the level shifter 220 and the buffer 230 is 3V, and the bias voltage VBIAS2 is 0V or -Vthp. During the read operation, since the write signal WE is at a low level, the node N3 is 3V and the node N4 is 0V. Therefore, the gate voltage VGn = 3V is supplied to the N-channel transistor 232 of the buffer 230. Since the node N3 is 3V and the node N4 is 0V, the N-channel transistor 205 is OFF, the N-channel transistor 206 is ON, the P-channel transistor 203 is OFF, and the P-channel transistor 204 is ON. Accordingly, the node N1 is 3V, the node N2 is 0V, and the gate voltage VGp = 3V is supplied to the P-channel transistor 231 of the buffer 230. As a result, in the buffer 230, the P-channel transistor 231 is turned OFF, the N-channel transistor 232 is turned ON, and the write voltage DINh becomes 0V.

  FIG. 16 is a circuit diagram showing a configuration of regulator circuit 250 for stably supplying power supply voltage VPP = 5 V + Vthn to level shifter 220 and buffer 230 shown in FIG. In FIG. 16, the charge pump 251 outputs a voltage of 8V. The output voltage of the charge pump 251 is supplied as a power supply voltage to the comparator 252 and also supplied to the sources of the P-channel transistors 253 and 255. The N-channel transistor 254 is a one-side high voltage structure transistor in which only the drain LDD layer is expanded. The drain and gate of the N channel transistor 254 are connected to the drain of the P channel transistor 253. Resistors R3 and R4 are interposed in series between the source of the N-channel transistor 254 and the low-potential side power supply VSS. In this example, the resistance ratio of the resistors R3 and R4 is determined so that the voltage obtained by dividing 5V by the resistors R3 and R4 becomes the reference voltage VREF = 1.5V. Comparator 252 compares the voltage at node N12 between resistors R3 and R4 with reference voltage VREF = 1.5 V, and controls the gate voltage for P-channel transistors 253 and 255 based on the comparison result. Here, the drain voltage of the P-channel transistor 255 is supplied to the level shifter 220 and the buffer 230 shown in FIG. 14 as the power supply voltage VPP.

  In such a configuration, when the source voltage of the N-channel transistor 254 is higher than 5V and the voltage of the node N12 is higher than the reference voltage VREF, the comparator 252 increases the gate voltage with respect to the P-channel transistors 253 and 255, and the P-channel transistor Increase the ON resistance of 253 and 255. On the other hand, when the source voltage of N-channel transistor 254 is lower than 5 V and the voltage at node N12 is lower than reference voltage VREF, comparator 252 lowers the gate voltage for P-channel transistors 253 and 255, and P-channel transistors 253 and 255 Reduce ON resistance. By this negative feedback control, the source voltage of the N-channel transistor 254 becomes 5V, and the drain and gate voltages of the N-channel transistor 254 are voltages obtained by adding the threshold voltage Vthn of the N-channel transistor 254 to this 5V. 5V + Vthn. Since a common gate voltage is applied to P channel transistors 253 and 255, power supply voltage VPP = 5V + Vthn is supplied from the drain of P channel transistor 255 to level shifter 220 and buffer 230 shown in FIG.

<Fourth embodiment>
In the flash memory shown in FIG. 5 and FIG. 6, it is necessary to set the drain voltage VD, the source voltage VS, and the Pwell voltage to 10 V at the time of erasing. At this time, all the column decoders are not selected. However, since the column switch section is composed of CMOS switches, it is necessary to devise settings in order to turn off these CMOS switches.

  FIG. 17 is a circuit diagram showing a configuration example of the column decoder 40 corresponding to erasure. FIG. 17 illustrates one CMOS switch among the CMOS switches constituting the second column switch unit 34 in FIG. This CMOS switch is composed of a P-channel transistor 4p and an N-channel transistor 4n. The Nwell in which the P-channel transistor 4p is formed is supplied with the high potential side power supply voltage VCOL, and the Pwell in which the N channel transistor 4n is formed is supplied with the low potential side power supply voltage VSS. The column decoder shown in FIG. 17 performs ON / OFF control of this CMOS switch.

  In the column decoder, the high potential side power supply voltage VD3 and the low potential side power supply voltage VSS are applied to the address match detection circuit 52, the inverter 53, and the inverter 51 in the level shifter 400. The level shifter 400 and the inverters 54 and 57 are supplied with the high potential side power supply voltage VCOL and the low potential side power supply voltage VSS.

  The inverter 53 logically inverts the erase signal EE and outputs it. The address match detection circuit 52 receives a lower digit of the column address and an inverted signal EEB of the erase signal EE. At the time of erasure (EEB = “0”), the address match detection circuit 52 outputs a high level (= VD3) regardless of the column address. Further, when it is not during erasure (EEB = “1”) and the lower digit of the column address indicates a value associated with the column decoder, the address match detection circuit 52 sets the Low level (= VSS). Output.

  In level shifter 400, P-channel transistors 41 and 42 have their sources connected to the high potential side power supply node to which power supply voltage VCOL is applied. P channel transistors 41 and 42 have their respective drains connected to their gates.

  Each of the P-channel transistors 43 and 44 is a one-side high breakdown voltage transistor in which only the drain LDD region is expanded. The source of the P-channel transistor 43 is connected to the common connection node N 1 between the drain of the P-channel transistor 41 and the gate of the P-channel transistor 42. The source of the P channel transistor 44 is connected to the common connection node N 2 of the drain of the P channel transistor 42 and the gate of the P channel transistor 41. A bias voltage VBIAS2 is applied to each gate of the P-channel transistors 43 and 44.

  The source of the P channel transistor 43 is connected to the drain of the N channel transistor 49, and the drain of the P channel transistor 43 is connected to the source of the N channel transistor 49. Further, the drain of the N channel transistor 50 is connected to the source of the P channel transistor 44, and the source of the N channel transistor 50 is connected to the drain of the P channel transistor 44. Each of these N-channel transistors 49 and 50 is a one-side high breakdown voltage transistor in which only the drain LDD region is expanded. Each gate of N channel transistors 49 and 50 is connected to output node N 5 of inverter 53.

  The address match detection circuit 52 at the preceding stage of the N channel transistors 45 and 46, the inverter 51 and the level shifter 400 is connected to one drain of the P channel transistor 43 or 44 and the low potential side power supply node in accordance with the output signal of the address match detection circuit 52. Switch means for forming a current path with (VSS = 0V) is configured. Further details are as follows.

  Each of N-channel transistors 45 and 46 is a one-side high breakdown voltage transistor in which only the LDD region of the drain extends, and each drain is connected to each drain of P-channel transistors 43 and 44, respectively. The source of the N channel transistor 45 is connected to the output node N 3 of the address match detection circuit 52, and the source of the N channel transistor 46 is connected to the output node N 4 of the inverter 51. Power supply voltage VD3 is applied to the gates of N channel transistors 45 and 46. N channel transistors 45 and 46 to which the power supply voltage VD3 is applied to the gate serve to regulate the voltages of nodes N3 and N4 to which the respective sources are connected so as not to exceed power supply voltage VD3.

  P channel transistor 47 has its source and drain connected to the source and drain of P channel transistor 41, respectively. The P channel transistor 48 has its source and drain connected to the source and drain of the P channel transistor 42, respectively. A bias voltage VBIAS1 is applied to each gate of the P-channel transistors 47 and 48. This bias voltage VBIAS1 is a voltage shifted from the voltage VCOL by the threshold voltage Vthp of the P-channel transistors 47 and 48 to the low potential side power supply voltage VSS = 0V side.

  P channel transistors 47 and 48 to which the bias voltage VBIAS1 is applied to the gate, like the P channel transistors 207 and 208 of the third embodiment, supplement the nodes N1 and N2 with a small drain current flowing therethrough, respectively. It plays a role of compensating voltage drops at the nodes N1 and N2 due to the leakage current.

  The inverter 54 includes a P channel transistor 55 and an N channel transistor 56. Each of these transistors 55 and 56 is a one-side high breakdown voltage transistor in which only the drain LDD region is expanded. The P channel transistor 55 has a source connected to the high potential side power supply VCOL and a gate connected to the node N 2 in the level shifter 400. The N-channel transistor 56 has a source connected to the low potential side power supply VSS and a gate connected to the node N4 in the level shifter 400. Transistors 55 and 56 have drains connected in common, and the common connection node outputs a column selection voltage to the gate of P channel transistor 4p via column selection line COLBp.

  On the other hand, the inverter 57 is composed of a P-channel transistor 58 and an N-channel transistor 59. Each of these transistors 58 and 59 is a one-side high voltage structure transistor in which only the drain LDD region is expanded. The P channel transistor 58 has a source connected to the high potential side power supply VCOL and a gate connected to the node N 1 in the level shifter 400. The N-channel transistor 59 has a source connected to the low-potential-side power supply VSS and a gate connected to the node N3 in the level shifter 400. Transistors 58 and 59 have drains connected in common, and the common connection node outputs a column selection voltage to the gate of N channel transistor 4n via column selection line COLBn.

  Next, the operation at the time of erasing according to the present embodiment will be described. At the time of erasing (Erase), the power supply voltage VCOL for the level shifter 400 and the inverters 54 and 57 is set to 10 V, which is the erasing voltage (P well voltage). Since the erase signal EE is at a high level, the node N5 is at a low level (= VSS = 0V), and the N-channel transistors 49 and 50 are turned off.

  Further, since the input signal EEB (inverted signal of the erasure signal EE) to the address match detection circuit 52 is at a low level, the output node N3 of the address match detection circuit 52 is at a high level (= VD3) regardless of the column address YADD. = 3V). As a result, the N channel transistor 45 and the P channel transistor 43 are turned OFF, and the drain node N6 of the N channel transistor 45 and the output node N1 of the level shifter 400 become 10V.

  On the other hand, since the output node N4 of the inverter 51 is at the low level (= VSS = 0V), the N-channel transistor 46 is turned on, and the node N7 at the drain of the N-channel transistor 46 is at the low level (= 0V). However, since the bias voltage VBIAS2 is 5V-Vthp, the level of the output node N2 of the level shifter 400 becomes the lower limit value 5V determined by the bias voltage VBIAS2.

  Since the gate voltage of the P-channel transistor 55 is 5V and the gate voltage of the N-channel transistor 56 is 0V, the inverter 54 outputs 10V to the column selection line COLBp. Further, since the gate voltage of the P-channel transistor 58 is 10V and the gate voltage of the N-channel transistor 59 is 3V (VD3), the inverter 57 outputs 0V to the column selection line COLBn. As a result, all the P channel transistors 4p connected to the column selection line COLBp and all the N channel transistors 4n connected to the column selection line COLBn are turned off.

  The above is the operation at the time of erasing. According to the present embodiment, even when the bit line BITj becomes 10V at the time of erasing, the electric fields between the gates of the transistors 55, 56, 58, 59, 4p, and 4n and the well can all be reduced to the breakdown voltage or less. The nonvolatile memory can be operated at a high voltage without using a gate high breakdown voltage transistor having a thick oxide film.

  Note that all Nwells of the P-channel transistors 41, 42, 47, 48, 43, and 44 may be connected to the power source of the highest voltage VCOL or may be connected to its own source. If it is connected to its own source, there is a merit that it is not affected by the back bias, but it is necessary to provide Nwell of each transistor independently, and the required area becomes large.

  FIG. 18 shows the operating voltage of each part at the time of writing (Program) of the circuit shown in FIG. In FIG. 18, the power supply voltage VCOL is set to 5 V at the time of writing. Since erase signal EE goes low, node N5 becomes 3V, N-channel transistors 49 and 50 are turned ON, and nodes N1 and N6 and nodes N2 and N7 are short-circuited.

  Further, since the signal EEB is at the high level, when the column address YADD indicates a value associated with the column decoder, the output node N3 of the address match detection circuit 52 is 0V, the output node N4 of the inverter 51 is 3V, The output node N1 of the level shifter 400 is 0V, and the output node N2 is 5V. Therefore, the inverter 54 outputs 0V to the column selection line COLBp, and the inverter 57 outputs 5V to the column selection line COLBn. As a result, all the P channel transistors 4p connected to the column selection line COLBp and all the N channel transistors 4n connected to the column selection line COLBn are turned on. At this time, if the data node NA is set to the write voltage 5V, 5V is output to the selected bit line BITj.

  On the other hand, when the column address YADD does not indicate a value associated with the column decoder, the output node N3 of the address match detection circuit 52 is 3V, the output node N4 of the inverter 51 is 0V, and the output node N1 of the level shifter 400 is 5V. , The output node N2 becomes 0V. Therefore, the inverter 54 outputs 5V to the column selection line COLBp, and the inverter 57 outputs 0V to the column selection line COLBn. As a result, all the P channel transistors 4p connected to the column selection line COLBp and all the N channel transistors 4n connected to the column selection line COLBn are turned off.

  FIG. 19 shows the operating voltage of each part at the time of reading (Read) of the circuit shown in FIG. As shown in FIG. 19, at the time of reading, the power supply voltage VCOL is 3V, and all the power supply voltages are 3V. The operation when the column decoder is selected and the operation when it is not selected are the same as those in FIG. At the time of reading, a voltage of 0.6 V is applied to the bit line BITj.

<Effect of each embodiment>
Next, effects of the embodiments of the present invention will be described while comparing with the comparative example shown in FIG. For example, as shown in FIG. 20, if the power supply voltage VPP for writing is set to 5 V and applied to the data node NA via a CMOS switch composed of a P-channel transistor 1p and an N-channel transistor 1n, in principle, All transistors can be replaced by low field transistors. However, in order to generate the power supply voltage VPP = 5V in the chip in this case, it is necessary to configure the power supply by the charge pump and the regulator, and there arises a problem of the response speed with respect to the instantaneous current.

  FIG. 21 shows an example of an undesired operation waveform when the circuit of FIG. 20 is used. In this example, when the data signal DINnh becomes a high level at the time of writing, the column decoder corresponding to the column address is turned on by the column decoder corresponding to the column address, and the bit line corresponding to the selected column address is set. A write voltage (5 V) is applied to BITj. FIG. 21A shows signal waveforms of the data signal DINnh and the column selection line COLA. In this example, the column selection lines COLA0 and COLA1 are selected in order. FIG. 21B shows voltage waveforms of the power supply voltage VPP and the data node NA. When the column selection gate on the path from the data node NA to the bit line BITj indicated by the column address is turned on and a voltage is applied to the bit line BITj and a current flows through the memory cell, the response of the regulator that generates the power supply voltage VPP Since the speed is low, as shown in FIG. 21B, the power supply voltage VPP is once dropped to a voltage of 5 V or less, and then gradually recovered. In some cases, when the column selection gate is turned OFF, a high voltage may be generated in the power supply voltage VPP for a moment due to the characteristics of the regulator. Therefore, as shown in FIG. 21 (c), the voltage waveform of the bit line BITj becomes considerably duller than the original ideal waveform, which causes a problem that the write characteristics are deteriorated.

  On the other hand, for example, the operation waveform when the circuit of the first embodiment (FIG. 8) is adopted is as shown in FIG. According to the first embodiment, when the column selection gate on the path from the data node NA to the bit line BITj indicated by the column address is turned on, a current flows rapidly as in FIG. As shown, the power supply voltage VPP (8 V) once causes a voltage drop. However, since the drop of the power supply voltage VPP is a voltage drop within a range higher than 5V set by the writing circuit, the voltage of the data node NA is not affected, and the data node NA always maintains 5V. Therefore, as shown in FIG. 22C, the original ideal voltage waveform is generated in the bit lines BIT0 and BIT1.

  As mentioned above, although the effect compared with the comparative example was demonstrated to 1st Embodiment as an example, the same effect is acquired also in 2nd-4th embodiment.

<Other embodiments>
In addition to the first to fourth embodiments described above, embodiments of the present invention are conceivable. For example, in each of the above-described embodiments, the one-side high withstand voltage structure transistor is used at the location where the voltage is concentrated. However, both-side high withstand voltage structure transistors may be used.

DESCRIPTION OF SYMBOLS 10 ... Write circuit 20,200 ... Input circuit, 30-x (x = 0-q), 40-y (y = 0-k) ... Column decoder, 33, 34 ... Column switch part, NW ... Write voltage generation node, NA... Data node, 2p, 3px (x = 0 to q), 4pyx (y = 0 to k, x = 0 to q)... P channel transistor, 2n, 3nx (x = 0 ... q), 4nyx (y = 0-k, x = 0-q), 11 ... N-channel transistor, 1 ... data control transistor, 2 ... data control switch, 12 ... charge pump, R1, R2 , R3, R4... Resistor, 13... Comparator, 14... NAND gate, 21, 22, 230, 54, 58... Buffer, LS, 220, 400 ... Level shifter, YDET, 52. .

Claims (2)

A nonvolatile memory cell array composed of a plurality of nonvolatile memory cells each connected to any one of a plurality of bit lines;
Column selecting means that is inserted between the data node and the plurality of bit lines, and connects the bit line connected to the nonvolatile memory cell to be accessed at the time of writing or reading, to the data node;
A data control transistor having a drain connected to the power supply node and a source connected to the write voltage generation node;
A write circuit for controlling a gate voltage of the data control transistor in response to a write signal;
A data control switch which is a CMOS switch interposed between the write voltage generation node and the data node;
An input circuit for switching ON / OFF of the data control switch according to a data signal,
When the write circuit switches ON / OFF of the data control transistor by controlling a gate voltage with respect to the data control transistor, and turns on the data control transistor, the power supply node passes through the data control transistor. A semiconductor integrated circuit, wherein a voltage applied to a write voltage generation node is suppressed by a gate voltage with respect to the data control transistor. The column selection means has a plurality of CMOS switches respectively inserted as column selection gates on a path from the plurality of bit lines to the data node, and from the bit line of the column indicated by a column address to the data node 2. The semiconductor integrated circuit according to claim 1, wherein a column selection gate on the route to be reached is selected and turned on .

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