JP2000076881A - Non-volatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device, by which a circuit area can be reduced, and at the same time working speed can be increased. SOLUTION: Memory cells MC, in which information is stored, are connected to decoders for read and decoders for write/erase through word lines WL. A plurality of the decoders for read are divided into a plurality of erasing blocks so that information stored in the memory cells is erased collectively. Voltage changeover circuits CH1 and CH2 changing over voltage input to terminals VP and terminals VN connected to inverters in the decoders for read to voltage selected from a plurality of voltage are joined with each erase block B1 and B2 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of electrically erasing stored information collectively, and more particularly to a nonvolatile semiconductor memory device capable of reducing a circuit area.

[0002]

2. Description of the Related Art A nonvolatile semiconductor memory device capable of collectively erasing stored information, that is, a flash memory in which a negative voltage is applied to a control electrode of a memory cell at the time of writing or erasing is known. (JP-A-6-168597). In this flash memory, since it is necessary to handle a voltage higher than the potential V _CC supplied by the voltage supply unit and a negative voltage at the time of writing and erasing, the level conversion circuit is connected to the row decoder,
The input voltage is converted into a predetermined voltage by this level conversion circuit and input to the row decoder.

Generally, in a flash memory,
The read time of one address is several tens nsec to several hundred ns.
ec, the writing time and the erasing time are each several μsec or more. Therefore, as a flash memory, it is necessary that the row decoder operate at high speed at the time of reading.

[0004]

However, the switching time of the level conversion circuit described in Japanese Patent Application Laid-Open No. 6-168597 is several nsec, and compared with several hundred psec which is the switching time of a logic gate such as an inverter. Since the operation is slow, it is difficult to use the above-described conventional row decoder when a high-speed operation of, for example, several tens of MHz is required.

[0005] A non-volatile semiconductor device with a higher writing speed has also been proposed (JP-A-6-309883).
No.). Further, for a flash memory in which a negative voltage is applied to a control electrode during an erasing operation, a row decoder for the flash memory capable of improving the reliability of the erasing operation has been proposed (Japanese Patent Laid-Open No. 5-205490).

However, using any of these nonvolatile semiconductor memory devices has the problems that the read time cannot be reduced and the circuit area may be large.

The present invention has been made in view of the above problems, and has as its object to provide a nonvolatile semiconductor memory device that can reduce the circuit area and improve the operation speed. .

[0008]

A nonvolatile semiconductor memory device according to the present invention comprises a plurality of memory cells for storing information, a word line connected to each memory cell, and an inverter connected to each word line. A pre-inverter connected to the inverter for determining selection and non-selection of the word line; and a write connected to the word line for writing information to the memory cell and erasing information from the memory cell. And an erasing decoder, and one or a plurality of voltage switching circuits provided for each of the one or more inverters and capable of switching an input voltage of an inverter belonging to each group to a voltage selected from a plurality of voltages. It is characterized by.

[0009] The timing of switching the input voltage to the inverter of the voltage switching circuit may be a time of performing an erasing operation, performing a writing operation, or performing a reading operation.

Preferably, the write / erase decoder has a level conversion circuit for converting an input voltage to a predetermined voltage. Further, the inverter and the pre-inverter may constitute a read decoder for reading information stored in the memory cell.

Further, the pre-inverter may have a NAND gate to which a row address signal is inputted,
At this time, the pre-inverter can determine selection or non-selection of the word line based on the row address signal.

In the present invention, one or a plurality of voltage switching circuits are provided for each of the one or a plurality of inverters, and the voltage switching circuit converts the input voltage to each of the one or a plurality of inverters into a plurality of the voltage. Therefore, even if the inverters belonging to one group cause punch-through due to the input voltage, the inverters belonging to another group are not affected. Accordingly, the withstand voltage of the transistor constituting the inverter and the pre-inverter connected thereto can be set low, so that the channel width and the channel length can be reduced, and the circuit area can be reduced.

In the present invention, if the write / erase decoder has a level conversion circuit for converting the input voltage to a predetermined voltage, the input / output voltage is reduced during the write / erase operation. Since a higher voltage or a negative voltage is required, a desired voltage can be obtained through this level conversion circuit. Further, at the time of a read operation, it is not necessary to use a level conversion circuit having a long switching time, so that the operation speed can be improved.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention, and FIG.
FIG. 2 is an enlarged circuit diagram showing a storage circuit of the nonvolatile semiconductor memory device shown in FIG. As shown in FIG. 2, a memory cell MC for storing information is connected to a word line WL, one end of the memory cell MC is connected to a bit line BL, and the other end is connected to a source line SL. ing.

The read decoder RD is connected to the word line WL
Is connected to a write / erase decoder WD having a level conversion circuit (not shown). In the read decoder RD, a row address signal is externally input to the NAND gate NAND1. Also,
The NAND gate NAND1 is connected to the gates of the P-channel MOS transistor P3 and the N-channel MOS transistor N4, and is also connected in series via the N-channel MOS transistor N1 to the P-channel MOS transistor P6 and the N-channel MOS transistor N4. It is connected to the gate of the type MOS transistor N7.

Further, a P-channel type MOS transistor P
A P-channel MOS transistor P2 and an N-channel MOS transistor N5 are connected in series to the 3 and N-channel MOS transistors N4, respectively. In this embodiment, the NAND circuits NAND1, N1,
The channel type MOS transistors N1, N4 and N5 and the P channel type MOS transistors P2 and P3 constitute a pre-inverter PINV, and include a P channel type MOS transistor P6 and an N channel type MOS transistor.
An inverter (word line driving stage) INV is configured by the transistor N7. That is, the word line WL is connected between the P-channel MOS transistor P6 and the N-channel MOS transistor N7 that constitute the inverter INV.

Further, the gates of the N-channel MOS transistor N1, the P-channel MOS transistor P2 and the P-channel MOS transistor P5 are connected to terminals A, B and C, respectively, and are connected to the outside of the read decoder RD. , Signals are input via terminals A, B and C. One end of the P-channel MOS transistor P6 is connected to the terminal VP, and one end of the N-channel MOS transistor N7 is connected to the terminal VN.

The nonvolatile semiconductor device according to the present embodiment has a plurality of storage circuits shown in FIG. 2, and the plurality of storage circuits are used to collectively erase information stored in memory cells. As shown in FIG. 1, for example, two erase blocks B1 and B2 each have two word lines WL1 and WL2 and word lines WL3 and WL4. And each word line WL
1, WL2, WL3 and WL4 are connected to memory cells MC1, MC2, MC3 and MC4, respectively.
One end of all the memory cells MC1, MC2, MC3 and MC4 is connected to one bit line BL.

The terminals A, B, and C of each memory circuit are all connected, and signals input from the terminals A, B, and C are collectively input to all the read decoders RD1 to RD4. Is controlled to be. Each of the erase blocks B1 and B2 has a voltage switching circuit C for switching voltages input to the terminals VP and VN.
H1 and CH2 are connected, and the same voltage can be input to all inverters in a predetermined block. Note that the voltage switching circuits CH1 and CH2 are connected to the terminal V, respectively.
A first switching unit (V _cc / open) for switching the voltage input to P between the potential V _cc and open (open), and a terminal V
A second switching unit (GND / open) that switches the voltage input to N between the potential V _SS (ground potential GND) and the open state is provided.

The read decoder RD shown in FIG.
NAND gates NAND11, NAN in 1 to RD4
D12, NAND13 and NAND14, N-channel MOS transistors N11, N12, N13 and N1
4, P-channel MOS transistors P21, P22,
P23 and P24, P-channel type MOS transistor P
31, P32, P33 and P34, N-channel type MOS
Transistors N41, N42, N43 and N44, N-channel MOS transistors N51, N52, N53 and N54, P-channel MOS transistors P61 and P
62, P63 and P64, N-channel MOS transistors N71, N72, N73 and N74, and
The erasing decoders WD1, WD2, WD3, and WD4 are
Each of the N-channel MOS transistor N1, the P-channel MOS transistor P2, the P-channel MOS transistor P3 in the read decoder WD shown in FIG.
N channel type MOS transistor N4, N channel type M
It corresponds to the OS transistor N5, the P-channel MOS transistor P6, the N-channel MOS transistor N7, and the write / erase decoder WD.

The operation of the nonvolatile semiconductor memory device thus configured will be described below with reference to FIG.
Table 1 below shows an example of a word line voltage for each operation in the nonvolatile semiconductor memory device according to the embodiment of the present invention.

[0022]

[Table 1]

As shown in Table 1 and FIG. 2, in the read operation, the terminal A shown in FIG. 2 has the potential V _CC , the terminal B has the potential V _CC , the terminal C has the potential V _SS , and the terminal C has the potential V _SS . Is a potential V _CC , and a potential V _SS is inputted to a terminal VN. When the word line WL is selected, the NAND gate NAND
1 are all at high level (potential V _CC ), the node 11 between the NAND gate NAND1 and the N-channel MOS transistor N1 is at low level (potential V _SS ), and the N-channel MOS transistor N1 1 between P-channel MOS transistor P3 and N-channel MOS transistor N4
2 also becomes low level (potential V _SS ).

Accordingly, the output of the inverter (word line driving stage) INV constituted by the P-channel MOS transistor P6 and the N-channel MOS transistor N7 has the potential V _CC, and this potential V _CC is the voltage of the word line WL. Becomes At this time, the gate voltage of the P-channel MOS transistor P2 is V _CC and the gate voltage of the N-channel MOS transistor N5 is V _SS , so that both the P-channel MOS transistor P2 and the N-channel MOS transistor N5 are in the off state. And the word line WL
And the node 12 are electrically separated.

On the other hand, when the word line is not selected, NA
Since at least one of the row address signals input to the ND gate NAND1 becomes low level (potential V _SS ) and the node 11 becomes high level (potential V _CC ), the potential of the node 12 becomes V _CC -V _tn 1 ( Vtn1 becomes the threshold value of the N-channel MOS transistor N1). Note that P
Channel type MOS transistor P6 and N-channel type M
Inverter IN constituted by OS transistor N7
Since V is set so that this value is sensed as a high level, the voltage of the word line WL becomes V _SS . Also in this case, as in the case of selecting the word line WL, both the P-channel MOS transistor P2 and the N-channel MOS transistor N5 are off, and the word line W
L and the node 12 are electrically separated.

In a write operation, -9 V is applied to terminal A,
The potential V _SS is inputted to the terminal B, the potential V _CC is inputted to the terminal C,
The terminal VP is open and the terminal VN is open. When the word line WL is selected, −9 V is output from the write / erase decoder, and this potential −9 V becomes the voltage of the word line WL. At this time, the NAND gate NAND
Since all the row address signals input to 1 are at the high level (potential V _CC ), the node 11 is at the low level (potential V _SS ). Therefore, the N-channel MOS transistor N5 having a gate voltage of V _CC and a source voltage of -9 V is turned on, and the source voltage of the N-channel MOS transistor N4 is set to -9 V, so that the N-channel MOS transistor N4 is turned on.
Since the OS transistor N4 is also turned on, the node 12
Is -9 V which is the same potential as the word line WL. This allows
The P-channel MOS transistor P6 and the N-channel MOS transistor N7 are both in the off state,
The N-channel MOS transistor N1 is also off.

On the other hand, when the word line WL is not selected,
V _SS is output from the write / erase decoder, and this potential V _SS becomes the voltage of the word line WL. At this time, the NAND
Since at least one of the row address signals input to the gate NAND1 is at the low level (potential V _SS ), the node 11 is at the high level (potential V _CC ). Accordingly, the N-channel MOS transistor N5 having a gate voltage of V _CC and a source voltage of V _SS is turned on, the source voltage of the N-channel MOS transistor N4 becomes V _SS, and the N-channel MOS transistor N4
Is also turned on, so that the node 12 has the same potential V _{SS as the} word line WL. Thus, the P-channel MOS transistor P6 and the N-channel MOS transistor N7
Are both turned off, and the N-channel MOS transistor N1 is also turned off.

[0028] In the erase operation, the terminal A is at a potential V _SS, terminal B is input potential V _SS, the potential V _CC to the terminal C, the terminal VP open, the terminal VN is set to open. When the word line WL is selected, 12 V is output from the write / erase decoder, and this potential 12 V becomes the voltage of the word line WL. At this time, the NAND gate N
Since all row address signals input to AND1 are at high level (potential V _CC ), node 11 is at low level (potential V _SS ). Therefore, a P-channel MOS transistor P2 having a gate voltage of V _SS and a source voltage of 12V
Is turned on, the source voltage of the P-channel MOS transistor P3 becomes 12 V, and the P-channel MOS transistor P3 is also turned on.
2 has the same potential as the word line WL, that is, 12V. As a result, the P-channel MOS transistor P6 is turned off, and the N-channel MOS transistor N7 has the potential input to the terminal VN connected to the source of 12V- _Vtn7.
At the time when (V _tn7 is the threshold value of the N-channel MOS transistor N7), the transistor is turned off. The N-channel MOS transistor N1 is off.

On the other hand, when the word line WL is not selected,
V _SS is output from the write / erase decoder, and this potential V _SS becomes the voltage of the word line WL. At this time, the NAND
Since at least one of the row address signals input to the gate NAND1 is at the low level (potential V _SS ), the node 11 is at the high level (potential V _CC ). Accordingly, the N-channel MOS transistor N5 having a gate voltage of V _CC and a source voltage of V _SS is turned on, the source voltage of the N-channel MOS transistor N4 becomes V _SS, and the N-channel MOS transistor N4
Is also turned on, so that the node 12 has the same potential V _{SS as the} word line WL. As a result, the P-channel MOS transistor P6 is turned off when the source voltage becomes | V _tp 6 | (V _tp 6 is the threshold value of the P-channel MOS transistor P6), and the N-channel MOS transistor N7 is also turned off. It turns off. The N-channel MOS transistor N1 is off.

In the nonvolatile semiconductor memory device in which the memory circuits operating as described above are connected in the state shown in FIG. 1, for example, when the erase block B1 is selected during the erase operation and the erase block B2 is not selected, the erase operation is performed. word lines WL1 and WL2 in the block B1 is 12V, and the word line WL3 and WL4 in the erase block B2 becomes V _ss. At this time, a P-channel MOS transistor P61 constituting an inverter of the read decoders RD1 to RD4
And N-channel MOS transistor N71, P-channel MOS transistor P62 and N-channel MOS
Since the transistor N72, the P-channel MOS transistor P63 and the N-channel MOS transistor N73, and the P-channel MOS transistor P64 and the N-channel MOS transistor N74 are all turned off, the selected word lines WL1 and WL2 are ,
The unselected word lines WL3 and WL4 do not electrically interfere with each other. Therefore, only a memory in a predetermined erase block can be erased collectively by a simple erase operation.

In this embodiment, each of the erase blocks includes voltage switching circuits CH1 and CH2 for switching the voltages input to the terminals VP and VN to the selected voltage. Therefore, it is not necessary to consider the withstand voltage of the MOS transistors constituting the inverter in the erase block B1 with respect to the voltages of the word lines WL1 and WL2 in the erase block B1 selected during the erase operation. . However, during the write operation, selection / non-selection is switched for each word line, so that the voltage of the selected word line is -9V. Therefore, the transistors constituting all the inverters may be configured to have a withstand voltage with respect to a voltage of -9V.

Further, in this embodiment, the write / erase decoder has a level conversion circuit, and the read operation can be executed without passing through the level conversion circuit having a long switching time. The operation speed can be improved as compared with the nonvolatile semiconductor memory device.

In addition to the non-volatile semiconductor memory device shown in FIG. 1, a non-volatile semiconductor memory device capable of controlling voltages applied to all terminals VP and VN collectively can be considered. FIG. 3 is a circuit diagram showing a nonvolatile semiconductor memory device having a voltage switching circuit connected to all inverters. The difference between the circuit shown in FIG. 3 and the present embodiment shown in FIG. 1 is that the terminals VP and VN in the erase block B1 are different.
And the terminals VP and VN in the erase block B2 are connected to each other, and all the inverters are collectively controlled. Therefore, in the circuit shown in FIG. The same components as those described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

Even in a nonvolatile semiconductor memory device configured as shown in FIG. 3, similar to the present embodiment shown in FIG.
The operation speed can be improved, and the selected word lines WL1 and WL2 and the unselected word lines WL3
And WL4 do not electrically interfere with each other, so that the erasing operation is easy.

[0035] However, in the nonvolatile semiconductor memory device shown in FIG. 3, the NAND circuit 11 to 14 potential V _CC
Although the above high voltage is not applied, since a high voltage or a negative voltage higher than the potential V _CC is applied to the drain electrodes of all other MOS transistors in the read decoder,
If the MOS transistor used has low withstand voltage, punch-through may occur. Therefore, it is necessary to increase the channel length of all the MOS transistors in order to increase the punch-through breakdown voltage of the transistors.

As described above, at the time of the erase operation, the voltage of the word line WL in the selected erase block is 12 V, so that the MOS transistors used must have a punch-through breakdown voltage of 12 V or more. In particular, a MOS transistor (a transistor corresponding to the P-channel MOS transistor P6 and the N-channel MOS transistor N7 shown in FIG. 2) which needs to drive a large load parasitic on the word line WL at high speed has a large driving capability. Therefore, it is necessary to further increase the channel width,
The circuit area increases.

On the other hand, the present embodiment has a voltage switching circuit for switching the voltage input to the terminals VP and VN to a selected one for each erase block.
Since the voltage applied to the inverter is independent for each erase block, even if a transistor forming the inverter in the selected erase block causes punch-through, it does not affect other erase blocks and malfunctions. Does not occur. Therefore, even for an inverter that requires the largest driving capability to perform a high-speed read operation,
During a write operation in which the word line voltage is lower than during an erase operation,
Since it is only necessary to have the required punch-through breakdown voltage, the channel width and the channel length can be set small, and the circuit area can be reduced.

[0038]

As described in detail above, according to the present invention,
One or a plurality of voltage switching circuits are provided for each of the one or a plurality of inverters, and the voltage switching circuit can switch an input voltage to each of the one or a plurality of inverters to a voltage selected from a plurality of voltages. Therefore, even if the inverters belonging to one group cause a punch-through due to the input voltage, they do not affect the inverters belonging to the other group, and the withstand voltage of the transistors constituting the inverters and the pre-inverters connected thereto is not affected. Can be set low, and the circuit area can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is an enlarged circuit diagram showing a storage circuit of the nonvolatile semiconductor memory device shown in FIG. 1;

FIG. 3 is a circuit diagram showing a nonvolatile semiconductor memory device having a voltage switching circuit connected to all inverters.

[Explanation of symbols]

A, B, C, VP, VN; terminals B1, B2; erase block BL; bit lines CH, CH1, CH2; voltage switching circuit MC, MC1, MC2, MC3, MC4; memory cells RD, RD1, RD2, RD3. RD4; read decoder SL; source line WD, WD1, WD2, WD3, WD4; write / erase decoder WL, WL1, WL2, WL3, WL4; word line

Claims (8)

[Claims] A plurality of memory cells for storing information;
A word line connected to each memory cell, an inverter connected to each word line, a pre-inverter connected to the inverter to determine selection and non-selection of the word line, and the memory cell connected to the word line And a write / erase decoder for writing information to the memory cell and erasing information from the memory cells, and an input voltage of an inverter provided for each of one or a plurality of inverters and belonging to the group, from a plurality of voltages. A nonvolatile semiconductor memory device comprising one or more voltage switching circuits capable of switching to a selected one. 2. The timing of switching the input voltage to the inverter of the voltage switching circuit when performing an erasing operation, performing a writing operation, or performing a reading operation. 3. The non-volatile semiconductor device according to claim 1. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said write / erase decoder has a level conversion circuit for converting an input voltage to a predetermined voltage. 4. The read-out decoder according to claim 1, wherein the inverter and the pre-inverter form a read decoder for reading information stored in the memory cell.
7. The non-volatile semiconductor storage device according to claim 1. 5. The nonvolatile semiconductor memory device according to claim 1, wherein said pre-inverter has a NAND gate to which a row address signal is input. 6. The nonvolatile semiconductor memory device according to claim 5, wherein said pre-inverter determines selection or non-selection of said word line based on said row address signal. 7. The inverter according to claim 1, wherein the inverter has a P-channel MOS transistor and an N-channel MOS transistor connected to the P-channel MOS transistor. Nonvolatile semiconductor memory device. 8. The voltage switching circuit includes a first switching unit that switches a voltage input to the P-channel MOS transistor and a second switching unit that switches a voltage input to the N-channel MOS transistor. The nonvolatile semiconductor memory device according to claim 7, wherein: