JP5487616B2 - I / O cell output circuit - Google Patents

Description

  The present invention relates to an output circuit of an I / O cell.

  In recent years, semiconductor memory devices have been increased in operating speed, increased storage capacity, and circuit elements. In such an I / O cell of a semiconductor memory device, variations in characteristics due to miniaturization are likely to occur.

  FIG. 13 shows an example of an I / O cell. A pull-up side output transistor T1 composed of a resistor R1 and a P-channel MOS transistor is connected between the pad 1 and the high potential side power supply VDE. Between the pad 1 and the ground GND, resistors R2 and N A pull-down output transistor T2 composed of a channel MOS transistor is connected. The input circuit 2 is connected to the pad 1 via a resistor R3.

  In such an I / O cell, in the output mode, one of the output transistors T1 and T2 is turned on, and an output signal of H level or L level is output from the pad 1. At this time, the resistors R1 and R2 act as damping resistors to reduce noise included in the output signal.

  In the input mode, an input signal input to the pad 1 is supplied to the internal circuit via the input circuit 2. At this time, for example, one of the output transistors T1 and T2 is turned on, or both are turned on, and the resistors R1 and R2 function as termination resistors for supplying a required potential to the pad 1.

In recent miniaturized semiconductor memory devices, the difference in wiring length between the pad 1 and the output transistors T1 and T2 greatly affects the output characteristics as the I / O cell is miniaturized as described above. It is like that.
JP 2004-327602 A Japanese Patent Laid-Open No. 11-177022 JP 2004-146485 A

  In a miniaturized I / O cell, if there is a difference in wiring length between the pad 1 and the output transistors T1 and T2, a difference in wiring resistance or parasitic capacitance occurs. The difference in wiring resistance or parasitic capacitance causes variations in the rising and falling speeds of the output signal, which causes the output characteristics to deteriorate.

  Patent Document 1 discloses a layout of an output buffer circuit (see FIG. 17). In this output buffer circuit, resistors are laid out between the pad and the P-channel MOS transistor and the N-channel MOS transistor.

Therefore, a difference occurs in the wiring length between the pad and each output transistor, so that the above problem cannot be solved.
Patent Document 2 discloses an output buffer circuit in which resistors are laid out between a P-channel MOS transistor and an N-channel MOS transistor that constitute an output transistor. However, a pad is laid out between the P-channel MOS transistor and the N-channel MOS transistor, and the interval between the P-channel MOS transistor and the N-channel MOS transistor is increased, so that the layout area is increased.

  Patent Document 3 discloses a semiconductor device in which an output buffer circuit and a termination resistor circuit are connected in parallel to a pad. However, in this semiconductor device, since the output buffer circuit and the termination resistor circuit are laid out independently, the layout area increases. In the termination resistor circuit, resistors are laid out between the pad and the P-channel MOS transistor and the N-channel MOS transistor, respectively, but in order to make the wiring length from the pad to the P-channel MOS transistor and the N-channel MOS transistor equal. The configuration of is not disclosed.

  An object of the present invention is to improve output characteristics and area efficiency of an output buffer circuit having a resistor that functions as a termination resistor or a damping resistor.

The object is to have a pull-up side transistor and a pull-down side transistor, and the output nodes of the pull-up side transistor and the pull-down side transistor are connected to pads via resistors and wires, respectively, and the respective resistors are formed. A plurality of regions are laid out on opposite sides of the region, the pull-up transistor is laid out in one of the regions, and the pull-down transistor is laid out in the other region. The pad is laid out outside the region, and is achieved by an output circuit of an I / O cell in which wirings between the output nodes of the pull-up side transistor and the pull-down side transistor and the resistors are of equal length .

  In the output circuit of the disclosed I / O cell, output characteristics and area efficiency of an output buffer circuit including a resistor that functions as a termination resistor or a damping resistor can be improved.

(First embodiment)
FIG. 1 shows an output buffer circuit embodying the present invention. The output transistor T11 on the pull-up side is composed of a P-channel MOS transistor, the source of the output transistor T11 is connected to the power supply VDE, and the drain (output node) is the pad 11 via the wiring L1, the resistor R11, and the wirings L2, L3. Connected to.

  The pull-down output transistor T12 is composed of an N-channel MOS transistor, the source of the output transistor T12 is connected to the ground GND, and the drain (output node) is connected to the pad 11 via the wiring L5, the resistor R12, and the wirings L4 and L3. Connected to. The output transistors T11 and T12 are actually configured by connecting a number of transistors in parallel. The on / off operations of the output transistors T11 and T12 are controlled by the drive signals dv1 and dv2 input to the gates thereof.

  FIG. 2 shows an element layout of the output buffer circuit. The output transistors T11 and T12 are constituted by a large number of transistors in which a large number of gate electrodes 14 are arranged in parallel on the diffusion regions 12 and 13, respectively.

  The pad 11 is laid out adjacent to the diffusion region 12, and the resistors R11 and R12 are laid out alternately at positions corresponding to the output transistors T11 and T12 formed in the diffusion regions 12 and 13, respectively.

  More specifically, the resistors R11 and R12 are laid out in a rectangular shape with the direction perpendicular to the longitudinal direction of the diffusion regions 12 and 13 as the longitudinal direction between the output transistors T11 and T12, and the resistors R11 and R12 are alternately laid out. The 3 and 4, the resistors R11 and R12 are formed of a polysilicon layer laid out on the substrate 15.

  The pad 11 is connected to one end of the resistor R11 through the wirings L3 and L2. As shown in FIG. 4, the wiring L3 is formed of a fourth layer wiring, and the wiring L2 is formed of a third layer wiring.

  When the substrate 15 to the fourth layer wiring are connected by the contacts 16a to 16c, the pad 11 is connected to the wiring L3 via the contacts 16a to 16c that connect the second and third wiring layers to each wiring layer. Connected to. The wiring L3 and the wiring L2 are connected through a contact 16c, and the wiring L2 and the resistor R11 are connected through a contact 16b, a second layer wiring, and a contact 16a.

  The other end of the resistor R11 is connected to the drain of the output transistor T11 via a wiring L1. The wiring L1 is formed of a third layer wiring as shown in FIG. 4, and both ends thereof are connected to the resistor R11 and the output transistor T11 via the second layer wiring and contacts 16b and 16a.

The pad 11 is connected to one end of the resistor R12 through the wirings L3 and L4. As shown in FIG. 3, the wiring L4 is formed of a third layer wiring.
The wiring L3 and the wiring L4 are connected through the contact 16c, and the wiring L4 and the resistor R12 are connected through the contact 16b, the second layer wiring, and the contact 16a.

  The other end of the resistor R12 is connected to the drain of the output transistor T12 via a wiring L5. The wiring L5 is formed of a third layer wiring as shown in FIG. 3, and both ends thereof are connected to the resistor R12 and the output transistor T12 via the second layer wiring and contacts 16b and 16a.

  As shown in FIGS. 2 to 4, among the wirings L1 to L5, the wirings L1 and L5 are formed to have the same length, and the wirings L2 and L4 are also formed to have the same length. The total wiring length from the pad 11 to the output transistor T11 is L3 + L2 + L1, and the total wiring length from the pad 11 to the output transistor T12 is L3 + L4 + L5.

Accordingly, the wiring length from the pad 11 to the output transistor T11 is equal to the wiring length from the pad 11 to the output transistor T12.
In the output buffer circuit as described above, the output transistors T11 and T12 are alternately turned on by the drive signals dv1 and dv2 in the output mode. When the output transistor T11 is turned on, an H level output signal is output from the output pad 11, and when the output transistor T12 is turned on, an L level output signal is output from the output pad 11. At this time, the resistors R11 and R12 operate as damping resistors that reduce noise in the output signal.

  In the input mode, one or both of the output transistors T11 and T12 are turned on. Then, the resistors R11 and R12 operate as termination resistors that hold the pad 11 at any one of the high potential side power supply VDE level, the ground GND level, or the intermediate level between the high potential side power supply VDE and the ground GND. A large number of such output buffer circuits are provided according to the number of input / output bits.

  FIG. 5 shows the rising waveform and falling waveform of the output signal of the output buffer circuit as described above. The rising waveforms p1 to p3 and the falling waveforms n1 to n3 shown in the figure show the case where the wiring length from the pad 11 to the output transistor T11 and the wiring length from the pad 11 to the output transistor T12 are made equal.

  The cross point between the rising waveform and the falling waveform of the output buffer circuit is preferably near an intermediate level between the high potential power source VDE and the ground GND. When the high potential power source VDE is 1.5 V, the cross point is The standard defines VDE / 2 ± 0.15V.

  The rising waveforms p1 to p3 and the falling waveforms n1 to n3 are dependent on the process of the output signal when the wiring length from the pad 11 to the output transistor T11 is equal to the wiring length from the pad 11 to the output transistor T12. Changes in operating speed due to temperature dependence are shown.

  If the wiring length is equal, when the rising waveform changes from p1 to p3, the falling waveform also changes from n1 to n3. Therefore, the cross points c1 to c3 of the rising waveform and the falling waveform are VDE / 2. It converges within ± 0.15V.

  On the other hand, when the resistors R11 and R12 are not laid out between the output transistors and there is a large difference in the wiring length from the pad to each output transistor, for example, the rising waveform is p4 with respect to the falling waveform n1. This is because the difference in the wiring length affects the variation of the wiring parasitic resistance due to the process dependence and temperature dependence, so that the rising speed is lowered and the slope of the rising waveform p4 is gentle.

  As a result, the cross point cx between the falling waveform n1 and the rising waveform p4 deviates from VDE / 2 ± 0.15V by 0.03V. In this embodiment, by making the wiring length from the pad 11 to the output transistor T11 equal to the wiring length from the pad 11 to the output transistor T12, the falling waveforms with respect to the rising waveforms p1 to p3 are set to n1 to n3. Such a problem is solved.

In the output buffer circuit as described above, the following operational effects can be obtained.
(1) The resistors R11 and R12 can act as damping resistors in the output mode, and the resistors R11 and R12 can act as termination resistors in the input mode.
(2) The resistors R11 and R12 can be laid out between the output transistor T11 on the pull-up side and the output transistor T12 on the pull-down side so that the wiring length between the pad 11 and the output transistors T11 and T12 can be made equal. .
(3) Since the wiring length between the pad 11 and the output transistors T11 and T12 can be made equal, it is possible to suppress voltage fluctuations at the cross point of the output signal due to process dependence and temperature dependence.
(4) The resistors R11 and R12 are laid out between the output transistors T11 and T12, and the pad 11 is located outside the diffusion regions 12 and 13, that is, between the pad 11 and the resistors R11 and R12. Since the layout is performed at the sandwiched position, the layout area of the output buffer circuit can be reduced.
(5) Since the resistors R11 and R12 are alternately laid out in the parallel direction of the output transistors T11 and T12 to form one column, the interval between the output transistors T11 and T12 can be reduced to reduce the layout area. .
(Second embodiment)
FIG. 6 shows another layout example of the output buffer circuit shown in FIG. In this embodiment, between the output transistors T11 and T12, the resistors R11 and R12 are respectively laid out in two columns, and the resistors R11 and R12 and the pad 11 and the output transistors T11 and T12 are respectively connected to the wirings L1, L3, and L4. , L5 are connected to form the output buffer circuit shown in FIG. Other configurations are the same as those in the first embodiment.

In such a configuration, the wiring length between the pad 11 and the resistors R11 and R12 is not equal, but the wiring length difference between the pad 11 and each of the output transistors T11 and T12 is slight.
Therefore, the same effects as (1) to (4) obtained in the first embodiment can be obtained. Further, since the resistors R11 and R12 are laid out in two rows, it is possible to easily form a resistor having a large current capacity as compared with the resistors R11 and R12 of the first embodiment. Further, since the resistors R11 and R12 are laid out in two rows, the layout length of the resistors R11 and R12 in the juxtaposed direction can be reduced as compared with the first embodiment.
(Third embodiment)
7 and 8 show a third embodiment. This embodiment shows an output buffer circuit in which the drains of the output transistors T11 and T12 are connected to the pad 11 via a resistor R13. In this output buffer circuit, the output transistors T11 and T12 are alternately turned on to output an output signal of H level or L level from the pad 11. The resistor R13 acts as a damping resistor.

  FIG. 8 shows an element layout of the output buffer circuit shown in FIG. A plurality of polysilicon resistance elements are formed between a diffusion region 16 in which a plurality of P-channel MOS transistors are juxtaposed as the output transistor T11 and a diffusion region 17 in which a plurality of N-channel MOS transistors are juxtaposed as the output transistor T12. A resistor R13 is laid out.

  The pad 11 is laid out on the side of the diffusion region 16 as in the first embodiment, and is connected to one end of each resistor R13 via the wiring L6. The other end of each resistance element is connected to the output transistor T11 via the wiring L7, and is connected to the output transistor T12 via the wiring L8. The wiring lengths of the wirings L7 and L8 are substantially equal.

With such a configuration, since the resistor R13 is laid out between the output transistors T11 and T12, the area efficiency can be improved. Further, by making the wiring length from the pad 11 to the output transistors T11 and T12 substantially equal, it is possible to suppress voltage fluctuation at the cross point of the output signal due to process dependence and temperature dependence.
(Fourth embodiment)
9 and 10 show a fourth embodiment. In this embodiment, the pull-up output transistor T11 is connected to the pad 11 via a resistor R13, and the pull-down output transistor is not provided.

  This output buffer circuit outputs an output signal of H level from the pad 11 when the output transistor T11 is turned on in the output mode. Further, when the output transistor T11 is turned off, the potential of the pad 11 becomes indefinite.

In the input mode, the output transistor T11 is turned on, and the resistor R13 operates as a termination resistor.
FIG. 10 shows an element layout of the output buffer circuit shown in FIG. The output transistor T11 is configured by laying a number of P-channel MOS transistors in two diffusion regions 18 and 19 arranged in parallel.

A resistor R13 composed of a plurality of polysilicon resistance elements is laid out between the diffusion regions 18 and 19.
The pad 11 is laid out on the side of the diffusion region 18 as in the first embodiment, and is connected to one end of each resistor R13 via the wiring L6. The other end of each resistance element is connected to the output transistor T11 in the diffusion region 17 through the wiring L7, and is connected to the output transistor T11 in the diffusion region 18 through the wiring L8. The wiring lengths of the wirings L7 and L8 are substantially equal.

With such a configuration, since the resistor R13 is laid out between the diffusion regions 18 and 19 forming the output transistor T11, the area efficiency can be improved. In addition, while the output transistor T11 is composed of a large number of P-channel MOS transistors formed in two diffusion regions, the wiring length between each transistor and the resistor R13 can be made substantially uniform. Therefore, the wiring length from the pad 11 to the many transistors constituting the output transistor T11 is made substantially equal, and the variation in the output characteristics of each transistor due to process dependence and temperature dependence is made uniform, thereby improving the output characteristics of the output transistor T11. be able to.
(Fifth embodiment)
11 and 12 show a fifth embodiment. In this embodiment, the pull-down output transistor T12 is connected to the pad 11 via a resistor R13, and the pull-up output transistor is not provided.

  This output buffer circuit outputs an L level output signal from the pad 11 when the output transistor T12 is turned on in the output mode. Further, when the output transistor T12 is turned off, the potential of the pad 11 becomes indefinite.

In the input mode, the output transistor T12 is turned on and the resistor R13 operates as a termination resistor.
FIG. 12 shows an element layout of the output buffer circuit shown in FIG. The output transistor T12 is configured by laying out a large number of N-channel MOS transistors in two diffusion regions 20 and 21 arranged in parallel.

A resistor R13 composed of a plurality of polysilicon resistor elements is laid out between the diffusion regions 20 and 21.
The pad 11 is laid out on the side of the diffusion region 20 as in the fourth embodiment, and is connected to one end of each resistor R13 via the wiring L6. The other end of each resistor R13 is connected to the output transistor T12 in the diffusion region 20 through the wiring L7, and is connected to the output transistor T12 in the diffusion region 21 through the wiring L8. The wiring lengths of the wirings L7 and L8 are substantially equal.

  With such a configuration, since the resistor R13 is laid out between the diffusion regions 20 and 21 forming the output transistor T12, the area efficiency can be improved. In addition, while the output transistor T12 is composed of a large number of N-channel MOS transistors formed in two diffusion regions, the wiring length between each transistor and the resistor R13 can be made substantially uniform. Therefore, the wiring length from the pad 11 to the many transistors constituting the output transistor T12 is made substantially equal, and the output characteristics of the output transistor T12 are improved by aligning variations in the output characteristics of each transistor due to process dependence and temperature dependence. be able to.

The embodiment described above can also be carried out in the following manner.
The pad 11 may be laid out on any diffusion region side of the pull-up side output transistor and the pull-down side output transistor.

The various aspects of the present invention are summarized as additional notes below.
(Appendix 1)
In an output circuit in which an output node of an output transistor is connected to a pad via a wiring and a resistor,
An output circuit of an I / O cell, wherein a plurality of regions forming the output transistor are laid out on both sides of the resistor so as to face each other, and the pad is laid out outside the region.
(Appendix 2)
The output transistor is constituted by a pull-up side transistor and a pull-down side transistor, and output nodes of the pull-up side transistor and the pull-down side transistor are connected to the pad via a resistor and a wiring, respectively, and the one of the plurality of regions The pull-up side transistor is laid out, the pull-down side transistor is laid out in the other region, and the wiring between the output node of the pull-up side transistor and the pull-down side transistor and each resistor is made equal in length. The output circuit of the I / O cell according to appendix 1.
(Appendix 3)
The I / according to claim 2, wherein the resistor connected between the pull-up side transistor and the pad and the resistor connected between the pull-down side transistor and the pad are laid out in a line. O cell output circuit.
(Appendix 4)
The resistor connected between the pull-up side transistor and the pad and the resistor connected between the pull-down side transistor and the pad are laid out in a line, respectively. I / O cell output circuit.
(Appendix 5)
The output transistor is composed of a pull-up side transistor and a pull-down side transistor, and an output node of the pull-up side transistor and the pull-down side transistor is connected to the pad via a common resistor and wiring, and is connected to one of the plurality of regions. The pull-up side transistor is laid out, the pull-down side transistor is laid out in the other region, and the wiring between the output node of the pull-up side transistor and the pull-down side transistor and each resistor is made equal. The output circuit of the I / O cell according to Supplementary Note 1, wherein
(Appendix 6)
The output transistor is constituted by a pull-up side transistor, an output node of the pull-up side transistor is connected to the pad via a resistor and a wiring, the pull-up side transistor is laid out in the plurality of regions, 2. The output circuit of an I / O cell according to claim 1, wherein wiring between an output node of the pull-up side transistor in the region and the resistor is made equal in length.
(Appendix 7)
The output transistor is configured by a pull-down transistor, an output node of the pull-down transistor is connected to the pad via a resistor and a wiring, the pull-down transistor is laid out in the plurality of regions, 2. The output circuit of an I / O cell according to appendix 1, wherein wiring between an output node of a pull-down transistor and the resistor has an equal length.
(Appendix 8)
8. The I / O cell output circuit according to any one of appendices 1 to 7, wherein the resistor is formed of polysilicon.

It is a circuit diagram showing an output buffer circuit of a first embodiment. It is an element layout diagram showing an output buffer circuit of the first embodiment. It is a chip sectional view showing the output buffer circuit of a first embodiment. It is a chip sectional view showing the output buffer circuit of a first embodiment. It is an output characteristic figure of an output buffer circuit. FIG. 6 is an element layout diagram showing an output buffer circuit of a second embodiment. It is a circuit diagram which shows 3rd embodiment. It is an element layout figure showing a third embodiment. It is a circuit diagram which shows 4th embodiment. It is an element layout figure showing a 4th embodiment. It is a circuit diagram which shows 5th embodiment. It is an element layout figure showing a 5th embodiment. It is a circuit diagram which shows an I / O cell.

Explanation of symbols

11 Pad 12, 13, 16, 17, 18, 19, 20, 21 Diffusion region T11, T12 Output transistor R11, R12, R13 Resistance

Claims (4)

A pull-up side transistor;
A pull-down transistor,
The output nodes of the pull-up side transistor and the pull-down side transistor are connected to pads through resistors and wirings, respectively, and are laid out so that a plurality of regions face each other on both sides of the regions where the resistors are formed, The pull-up side transistor is laid out in one of a plurality of regions, the pull-down side transistor is laid out in the other region, the pad is laid out outside the plurality of regions, and the pull-up side transistor and the pull-down side are laid out An output circuit of an I / O cell, characterized in that wiring between an output node of a transistor and each of the resistors is of equal length.   A resistor connected between the pull-up side transistor and the pad and a resistor connected between the pull-down side transistor and the pad are laid out in a line in the region where the resistors are formed. The output circuit of the I / O cell according to claim 1.   A resistor connected between the pull-up side transistor and the pad and a resistor connected between the pull-down side transistor and the pad are laid out in a line in the region where each resistor is formed. 2. The output circuit of an I / O cell according to claim 1, wherein A pull-up side transistor;
A pull-down transistor,
The output node of the pull-up side transistor and the pull-down side transistor is connected to the pad via a common resistor and wiring, and is laid out so that a plurality of regions are opposed to each other on both sides of the region where the resistor is formed, The pull-up side transistor is laid out in one of the plurality of regions, and the pull-down side transistor is laid out in the other region, and the wiring between the output node of the pull-up side transistor and the pull-down side transistor and the respective resistors Is an equal length, an output circuit of an I / O cell.

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