KR101231242B1 - Sram cell for preventing capacitive coupling noise between neighbor bitline - Google Patents

Abstract

The present invention is to provide an SRAM cell suitable for preventing the sensing margin reduction due to the capacitive coupling noise between adjacent bit lines, the SRAM cell of the present invention is the first and second load transistor, the first and second drive transistor and In an SRAM cell having first and second exciter transistors, a first region to which a VSS line is connected and a second region and a third region to be connected to both sides of the first region to form the first and second exciter transistors. Shape) an active region, a first access gate line across the top of the second region, a second access gate line across the top of the third region, a bit line connected to an end of the second region, and Any neighboring bit line connected to an end of the third area and arranged side by side with the bit line at a predetermined interval, and disposed between the bit line and the neighboring bit line, and one of the first area. And an access gate line connection wiring connecting the first access gate line and the second access gate line to each other, wherein the present invention includes a VSS between neighboring bit lines BL and / BL. By arranging the lines, the capacitive coupling noise between the two bit lines is blocked during the sensing operation to increase the noise margin, thereby improving the reliability and yield of the SRAM cell.

SRAM, SRAM, VCC, Bitline, Coupling Noise

Description

SRAM cell prevents capacitive coupling noise between neighboring bit lines {SRAM CELL FOR PREVENTING CAPACITIVE COUPLING NOISE BETWEEN NEIGHBOR BITLINE}

1 is a circuit diagram of an SRAM cell according to the prior art,

2a to 2c is a layout process of the SRAM cell according to the prior art,

3A to 3C are layout process diagrams of an SRAM cell according to an embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

21: first active area 22: second active area

23a: first common gate line 23b: second common gate line

23c: first access gate line 23d: second access gate line

28a: bit line 28b: sub bit line

28c: VSS line 30: Access gate line connection wiring

The present invention relates to an SRAM cell, and more particularly, to an SRAM cell having an excellent noise margin.

In general, SRAM (Static Rndom Access Memory) does not need refresh operation, and it is easy to adjust the operation timing, so that the access time and cycle time can be the same as the microcomputer, and high speed operation such as bipolar RAM can be realized. It is.

It is also widely used in buffer memory of large calculators, main memory of supercomputers, and control memory.

Such an SRAM is based on a flip-flop type, and is classified into an E / D type SRAM, a CMOS type SRAM, and a high resistance load type SRAM according to the load element. Dual CMOS type SRAM uses PMOS as a load device, which has the lowest power consumption and is advantageous in terms of operation timing setting.

Therefore, recently, in order to improve the characteristics of the SRAM cell, the SRAM cell of the full CMOS type is mainly adopted.

Hereinafter, the SRAM of the related art will be described with reference to the accompanying drawings.

1 is a circuit diagram illustrating a conventional SRAM cell.

Referring to FIG. 1, an SRAM cell consists of two access transistors TA1 and TA2 and a pair of CMOS inverters (an inverter of TL1 and TD1 and an inverter of TL2 and TD2).

In FIG. 1, the gates of the first and second transistors TA1 and TA2 are connected to the word line WL, and the sources thereof are respectively connected to the bit line BL and the sub bit line / BL. Connect.

In a pair of CMOS inverters, a first CMOS inverter includes a first load transistor TL1 and a first drive transistor TD1, and an input terminal is connected to an output terminal of the second CMOS inverter and a drain of the second exciter transistor TA2. The output terminal is connected to the drain of the first access transistor TA1 and the input of the second CMOS inverter. The second CMOS inverter includes a second load transistor TL2 and a second drive transistor TD2. The input terminal is connected to the output terminal of the first CMOS inverter and the drain of the first access transistor TA1, and the output terminal is connected to the second access transistor. It is connected to the drain of the transistor TA2 and the input terminal of the first CMOS inverter. In addition, drains of the first and second load transistors TD1 and TD2 are connected to the first power supply Vcc, and sources of the first and second drive transistors TD1 and TD2 are connected to the second power supply Vss. do.

2A to 2C are layout process diagrams of an SRAM cell according to the prior art.

As shown in FIG. 2A, a first active region 11 in which the first and second load transistors are to be formed, and a second active region 12 in which the first and second drive transistors and the first and second exciter transistors are to be formed are formed. do.

Subsequently, the first common gate line 13a, the second load transistor, and the second drive of the first load transistor and the first drive transistor that cross the upper portion of the first active region 11 and the second active region 12 simultaneously. The second common gate line 13b of the transistor is formed. In addition, a word line 13c is formed at the same time across the upper portion of the second active region 12 where the first and second exciter transistors are to be formed. Here, the word line 13c serves as the gate line of the first and second exciter transistors, and when the signal is applied to the word line 13c, the first and second exciter transistors are simultaneously driven.

Subsequently, predetermined active region contacts 14a, 14b, 14c, 14d, 14e, 14f, 14g, and 14h are formed in each active region, and the first and second common gate lines 13a and 13b are formed in the center portion. First and second gate line contacts 15a and 15b are formed. The active region contacts 14a, 14b, 14c, 14d, 14e, 14f, 14g, and 14h and the first and second gate line contacts 15a and 15b are metal contacts M1C.

As shown in FIG. 2B, the first output node local wiring 16a and the second common gate line 13 which simultaneously connect the first common gate line 13a, one side of the second load transistor and one side of the second drive transistor 13b), a second output node local wiring 16b for simultaneously connecting one side of the first load transistor and one side of the first drive transistor is formed; The VSS line 16c is connected to the common source of the first and second drive transistors through the active region contact 14h and connected to the common drain of the first and second load transistors through the active region contact 14a. The VCC line 16d is formed. Then, local wirings 16e and 16f are formed to be connected to one side of the first and second exciter transistors, respectively.

The first and second output node local wirings 16a and 16b, the VSS line 16c, the VCC line 16d, and the local wirings 16e and 16f are connected to the metal contact M1C. )to be. On the other hand, vias 17a, 17b, and 17c are formed on the VSS line and the local wiring.

As shown in FIG. 2C, the bit lines 18a and the sub bit lines / BL and 18b connected to the local wirings 16e and 16f through the vias 17b and 17c are formed.

However, since the voltages of the adjacent bit lines 18a and 18b operating in the sensing operation are changed in opposite directions, the above-described prior art is caused by the capacitive coupling noise 19 and the sensing margin is increased. There is a decreasing problem.

In addition, the conventional technology has a disadvantage in that the length of the vertical direction is longer than that of the horizontal direction and embedded in the DDI chip that is longer in the horizontal direction, thereby increasing the total area of the chip by lengthening the length of the vertical DDI chip.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and an object thereof is to provide an SRAM cell suitable for preventing a sensing margin reduction caused by capacitive coupling noise between adjacent bit lines.

In order to achieve the above object, the SRAM cell of the present invention is a SRAM cell including first and second load transistors, first and second drive transistors, and first and second exciter transistors, the first region to which the VSS line is connected and the first region. An active region having a second region and a third region connected to both sides of the first region to form the first and second excursion transistors, a first access gate line crossing the upper portion of the second region, and an upper portion of the third region A second access gate line intersecting the second bit line; a bit line connected to an end of the second region; an arbitrary bit line connected to an end of the third region and arranged in parallel with the bit line at a predetermined distance; A VSS line connected to one side of the first region and an access gate line connecting wiring connecting the first access gate line and the second access gate line to each other and disposed between the adjacent bit lines and a neighboring bit line. The bit line, the neighboring bit line and the VSS line is characterized in that the same metal wiring level, and the access gate line connection wiring is higher than the bit line, neighboring bit line and VSS line metal wiring And a first common gate line which serves as a gate line of the first load transistor and a first drive transistor in common, and a second common which serves as a gate line of the second load transistor and the second drive transistor in common. A first output node local wiring for simultaneously connecting a gate line, the first common gate line, one side of the second load transistor, and one side of the second drive transistor, the second common gate line, one side of the first load transistor, and the first A second output node local wiring for simultaneously connecting one side of the drive transistor, and the empty of the first and second load transistor And a VCC line connected to the portion, wherein the first and second output node local wiring lines and the VCC line are at the same metal wiring level, and the first and second output node local wiring lines and the VCC line are lower than the VSS line. The second and third regions of the active region extend in the horizontal direction at both ends of the first active region and are bent in a transverse shape, and the first and second access gate lines are horizontal. It is characterized in that it is disposed above the portion extending in the direction.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

In an embodiment to be described below, noise between two bit lines is blocked by inserting a common source line (ie, VSS line) of a drive transistor between two bit lines, that is, a bit line and a sub bit line. The source of the drive transistor always maintains a 0V voltage, which blocks noise caused by capacitive coupling between the bit lines.

In addition, in the SRAM cell layout, the length of the transverse direction is longer than that of the longitudinal direction, thereby reducing the chip area.

3A to 3C are layout process diagrams illustrating a method of manufacturing an SRAM cell according to an exemplary embodiment of the present invention. Hereinafter, the first and second load transistors are PMOS, the first and second drive transistors and the first and second exciter transistors are NMOS, and a well region and a source / drain region for each transistor are not shown.

As shown in FIG. 3A, a first active region 21 in which the first and second load transistors are formed, and a second active region 22 in which the first and second drive transistors and the first and second exciter transistors are formed are formed. do. Here, the first active region 21 has the same shape as the first active region 11 of the prior art, and the second active region 22 is horizontally different from the second active region of the prior art placed in the vertical direction. It has a more expanded form. That is, the second active region 22 is disposed in the horizontal direction from both ends of the second-first active region 22a and the second-first active region 22a in the horizontal direction in which the first and second drive transistors are to be formed. From the extended first portion 201 and the first portion 201 to the second active region 22b having a cross-shaped ("a") shape consisting of an extended second portion 202 extending from the first portion 201. It is composed. Here, the second-second active regions 22b are regions in which the first and second exciter transistors are to be formed. As will be described later, the gate lines of the first and second exciter transistors are formed on the first portions 201 of the second-second active regions 22b.

As described above, the second active region 22b having the shape of an access gate line is formed in the second active region 22 and the second active region 22b having the shape of a tracer. ), So that the length in the horizontal direction is longer than in the vertical direction.

Subsequently, the first common gate line 23a of the first load transistor and the first drive transistor that cross the upper portion of the second-first active region 22a of the first active region 21 and the second active region 22 at the same time. ) And a second common gate line 23b of the second load transistor and the second drive transistor. In addition, the first and second of the first and second exciter transistors crossing the upper portion of the first portion 201 of the second and second active regions 22b in which the first and second exciter transistors are to be formed. The exit gate lines 23c and 23d are formed. Here, the first and second access gate lines 23c and 23d are gate lines of the first and second exciter transistors, and when the signal is applied, the first and second access transistors are simultaneously driven. In addition, the first and second access gate lines 23c and 23d are formed separately from each other unlike the prior art.

Subsequently, predetermined active region contacts 24a, 24b, 24c, 24d, 24e, 24f, 24g, and 24h are formed in each active region, and the first and second common gate lines 23a and 23b are formed in the center portion. First and second gate line contacts 25a and 25b are formed, and third and fourth gate line contacts 25c and 25d are formed on word lines 23d and 23c. The active region contacts 24a, 24b, 24c, 24d, 24e, 24f, 24g and 24h and the first, second, third and fourth gateline contacts 25a, 25b, 25c and 23d are metal contacts M1C. .

As shown in FIG. 3B, the first output node local wiring 26a and the second common gate line 23 simultaneously connecting the first common gate line 23a, one side of the second load transistor, and one side of the second drive transistor. 23b), a second output node local wiring 26b for simultaneously connecting one side of the first load transistor and one side of the first drive transistor is formed. The VSS local wiring 26c connected to the common source of the first and second drive transistors is formed through the active region contact 24h, and the common drain of the first and second load transistors is formed through the active region contact 24a. The VCC line 26d to be connected is formed. The bit line local wiring 26e and the sub bit line local wiring 26f respectively connected to one side of the first and second exciter transistors are formed. In addition, primary access gate line local wirings 26g and 26h are formed on the first and second access gate lines 23c and 23d through the third and fourth gate line contacts 25c and 25d.

The first and second output node local wirings 26a and 26b, VSS local wiring 26c, VCC line 26d, bit line local wiring 26e, sub bit line local wiring 26f, and primary access gate. The line local wirings 26g and 26h are first metal wirings M1 connected to the metal contacts M1C. On the other hand, the first vias 27a, 27b, 27c, 27d on the VSS local wiring 26c, the bit line local wiring 26e, the sub bit line local wiring 27f, and the primary access gate lines 26g and 26h. , 27e) is formed.

As shown in FIG. 2C, a second metal wiring M2 connected to the first metal wiring M1 is formed through the first vias 27a, 27b, 27c, 27d and 27e.

For example, the second metal wiring M2 is connected to the bit line local wiring 26e and the sub bit line local wiring 26f through the first vias 27b and 27c, respectively. / BL, 28b).

A VSS line 28c is formed between the bit line 28a and the sub bit line 28b to be connected to the VSS local wiring 26c through the first via 27a. As such, when the VSS line 28c which is the power line is formed in the second metal wiring process, the complexity of the lower first metal wiring M1 may be reduced. That is, in the prior art, since the VSS line is formed in the first metal wiring M1 process and formed together with the output node local wiring, the wiring is very complicated. By forming the wiring arrangement, the wiring arrangement is simplified. That is, the bit line 28a, the sub bit line 28b and the VSS line 28c are at the same metal wiring level.

In the second metal wiring (M2) process as described above, the second access gate line local wirings 28d and 28e connected to the first access gate line local wirings 26g and 26h through the first vias 27d and 27e. Form.

After the second vias 29a and 29b are formed on the secondary access gate local wirings 28d and 28e, the third metal wiring M3 connected to the second vias 29a and 29b is formed. do. In this case, the third metal wiring M3 is an access gate line connection wiring 30 for simultaneously connecting the second access gate local wirings 28d and 28e through the second vias 29a and 29b. The access gate line connection wiring 30 is at a higher metal wiring level than the bit line 28a, the sub bit line 28b, and the VSS line 28c.

As a result, the first and second access gate lines 23c and 23d of the first and second exciter transistors are connected to each other by the access gate line connection wiring 30 by the third metal wiring process. Preferably, the third and fourth gate line contacts 25c and 25d which are metal contacts, the primary access gate line local wirings 26g and 26h, and the first vias 27d and 27e and the secondary access gate line local wiring ( 28d and 28e and second vias 29a and 29b.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the VSS line is disposed between neighboring bit lines BL and / BL to block the capacitive coupling noise between the two bit lines during the sensing operation, thereby increasing the noise margin, thereby improving reliability of the SRAM cell. The effect is that the yield can be improved.

Claims (6)

In the SRAM cell having the first and second load transistors, the first and second drive transistors and the first and second exciter transistors, An active region having a first region to which a VSS line is connected and a second region and a third region to be connected to both sides of the first region to form the first and second exciter transistors; A first access gate line crossing the upper portion of the second region; A second access gate line crossing the upper portion of the third region; A bit line connected to an end of the second region; An arbitrary bit line connected to an end of the third area and disposed to be parallel to the bit line at a predetermined distance; A VSS line disposed between the bit line and a neighbor bit line and connected to one side of the first region; And And an access gate line connection wiring connecting the first access gate line and the second access gate line to each other. And the bit line, the neighbor bit line, and the VSS line have the same metallization level. delete The method of claim 1, And the access gate line connection wiring is at a metal level higher than that of the bit line, the neighboring bit line, and the VSS line. The method of claim 1, A first common gate line which simultaneously functions as a gate line of the first load transistor and the first drive transistor; A second common gate line which simultaneously functions as a gate line of the second load transistor and the second drive transistor; A first output node local wiring for simultaneously connecting the first common gate line, one side of the second load transistor, and one side of the second drive transistor; A second output node local wiring for simultaneously connecting the second common gate line, one side of the first load transistor, and one side of the first drive transistor; And Further comprising a VCC line connected to the common portion of the first and second load transistor, And the first and second output node local wiring lines and the VCC line have the same metal wiring level, and the first and second output node local wiring lines and the VCC line are lower metal wiring levels than the VSS line. 5. The method of claim 4, The first and second access gate lines and the access gate line connection wiring may include A gate line contact on the first and second access gate lines, a first access gate line local wiring on the gate line contact, a first via on the first access gate local wiring, and a second access on the first via Connected via a second via on the gate line local wiring and the second access gate line local wiring, And the primary access gate line local wiring is at the same metal wiring level as the first and second output node local wiring lines, and the secondary access gate line local wiring is at the same metal wiring level as the VSS line. The method according to any one of claims 1 and 3 to 5, The second region and the third region of the active region extend in the horizontal direction at both ends of the first active region and are bent in a transverse shape, and the first and second access gate lines extend in the horizontal direction. Sram cell, characterized in that disposed in.

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