JP2001101871A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which the reset time of a word line can be shortened and the access speed can be increased. SOLUTION: In the semiconductor memory provided with a reset transistor resetting a word line, the memory is characterized in that the reset transistor is arranged between the far end and the center of the word line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having a transistor for resetting a word line.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional circuit diagram. As shown in FIG. 2, this diagram is a circuit diagram for selecting and non-selecting a word line. In this conventional example, the circuit is constituted by a two-input NOR. That is, as shown in FIG. 2, 2N1 represents a two-input NOR for selecting or deselecting the word line W1,
2N2 is a 2-input N for selecting or non-selecting the word line W2.
Represents OR. One of the two inputs of the two-input NOR is shown in FIG.
As shown in FIG.
1 and D2, and the other input is a one-shot signal XE generated from the address transition detection circuit.
Address transition detection circuit (Address Transition Detection
Circuit; hereinafter, referred to as "ATD circuit". ) Is a one-shot pulse signal generated by an address transition
It is called "OS". ) To control the internal operation. This ATD circuit is used for an internal synchronous semiconductor device. Also, as shown in FIG. 2, R1 and R2 represent the wiring resistances of word lines W1 and W2, respectively, and C11 and C12 and C21 and C22 represent the word lines W1 and W22, respectively.
2 represents a parasitic wiring capacitance.

In such a conventional circuit, usually,
In order to realize high-speed access, a method of reducing word resistance by running a polysilicon line and an aluminum line in parallel on a word line and making appropriate contact with a part thereof is adopted. In products that do not require very high-speed access, the word line resistance is high because the polysilicon and aluminum cannot be run in parallel due to the memory cell layout pattern and the word line is composed of polysilicon alone. As a result, the reset time becomes longer. At this time, if the method of crossing the word lines at a sufficiently low voltage level is adopted, it is necessary to further increase the OS width, in other words, the width of XE.

In such a method, it is necessary to further adjust the OS width in accordance with the wiring resistance and capacitance of the word line. When the product of the wiring resistance of the word line and the wiring capacitance is large, the reset time of the word line is long, so that the OS width is widened. When the product of the wiring resistance of the word line and the wiring capacitance is small, Since the reset time of the word line is short, the OS width is narrowed.

For example, in an SRAM configured to drive 256 cells per word line, the design rule is 0.3 to
In the case of a product conforming to the 0.4 μm process rule, r1 consisting of a word line consisting only of polysilicon is about several tens of KΩ, and c1 is a value on the order of several pF (subpicofarad) as a normal value. ing. Here, assuming that r1 is 50 KΩ and c1 is 0.3 pF, the reset time T
Becomes 15 nSec (nanosecond). Therefore, O of XE
The S width needs to be 15 nSec or more.

[0006] In the future, the power supply voltage value of general-purpose memories used in mobile phones and the like is expected to be lower than the current value, and the access time standard is expected to be faster. I have. However, when the power supply voltage value is reduced, the capacity of the transistor is reduced, and accordingly, the access time is further reduced accordingly. As described above, if the OS width is made sufficiently wide, it is considered that the access time becomes longer, and even if the product has a sufficient access time, the access time margin will be lost in the future.

For example, in the case of a memory product using an SRAM having a capacity of 2M used for a cellular phone or the like, an access time of 70 nSec is currently required at a power supply voltage of 2.7 V. When spending more than 15nSec on word reset time only with such products,
Satisfying access becomes difficult. For this reason, there is a demand that the reset time of a word line composed of only polysilicon must be shortened.

FIG. 4 shows an example in which the word line reset time is shortened to meet such a demand. In this example,
The drain is the word line, the source is the GND,
An Nch transistor whose gate is connected to XE is formed at the far end of the word line. In this example, the word potential is discharged from “high” to “low” by the 2-input NOR and the N-channel transistor and reset, and the 2-input NOR is reset from the near end of the word to the N-channel. Are reset from the far end of the word.

In the conventional example shown in FIG. 2, the word reset time is 15 nSec (nanosecond), while in the conventional example shown in FIG. 4, 1 / sec of the example shown in FIG. 4, which is 3.75 nSec.

FIG. 5 shows another conventional example in which an N-channel (Nch) reset transistor is arranged at the center of a word. In the conventional example shown in FIG. 5, the reset time is inferior to the case where the word is arranged at the far end of the word.
That is, in the other conventional example shown in FIG. 5, the two-input NOR resets from the near end of the word line, and the reset transistor resets from the center of the word line. As described above, also in the conventional example shown in FIG. 5, since resetting is performed in both the near end side and the far end side, it takes extra time to reset the word line to the far end.

There are also known circuit means for shortening the time for setting a word. FIG. 6 shows such a circuit, but the shortened circuit of FIG. 6 is designated as P1 in FIG. The input side is a word line, and the output side is an inverter IN1 input to the gate of P1 of the Pch transistor. Then, as shown in FIG.
1 are connected to VCC, and the drains are connected to word lines, respectively. In this circuit, the output of the two-input NOR transitions from low to high, and the word gradually transitions from low to high from the near end of the word line connected to the two-input NOR. Also, the voltage level of the word line connected to this circuit gradually increases, and when the voltage exceeds the threshold voltage of the inverter, the inverter output changes from high to low,
The P-channel (Pch) transistor is turned on, thereby increasing the speed at which the word line rises to a high level. Since this circuit is desirably located at the center of the word line, the reset circuit is also arranged together with the circuit, and the increase in the chip size due to the arrangement at different locations is prevented. Thus, the center of the word line is N
There is also known a configuration in which a reset transistor for ch is arranged.

[0012]

As described above, when the wiring resistance of the word line is increased or the wiring capacitance is increased, the first problem is that the reset time of the word line from high to low becomes longer. Is mentioned. In particular, in the case of a word line composed only of polysilicon, this tendency is further increased. In order to solve such a problem, as shown in FIG. 4, it is conceivable to shorten the reset time by arranging a transistor for assisting the word reset at the far end of the word line.

However, it is expected that the operating power supply voltage of memory products such as SRAMs used in portable devices and the like in the future will be further reduced, and at the same time, the access standard will tend to be maintained. Therefore, it is necessary to further speed up the reset time of the word line.

An object of the present invention is to shorten the reset time of a word line and speed up access.

[0015]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device having a reset transistor for resetting a word line.
The arrangement position of the reset transistor is arranged between the center and the far end of the word line.

According to a second aspect of the present invention, in the first aspect, the reset transistor has a drain connected to a word line, a source connected to GND, and a gate connected to a signal controlled by an address transition detection circuit. The reset transistor is constituted by an N-channel transistor.

According to a third aspect of the present invention, there is provided the semiconductor integrated circuit device according to the first or second aspect, wherein the reset transistor is provided at a position shifted by about 29% from a far end.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit device including a reset transistor for resetting a word line, wherein the semiconductor integrated circuit device selects / deselects a word line. A wiring portion of the word line, a first wiring length from the near end of the two input means, a second wiring from the near end to the reset transistor, and a second wiring length from the reset transistor to the far end Wiring length.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit device according to the fourth aspect, a ratio of the first wiring length to the second wiring length is about 1.4: 1. It is characterized by having been set as follows.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit device according to any one of the first to fifth aspects, the word line is provided corresponding to a 0.3 or 0.4 μm rule. And

[0021]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention. In the present invention, the decoder is a two-input NOR
It is composed of 2N1 is a two-input NOR that selects or deselects W7, and 2N2 is a two-input NOR that selects or deselects W8. One of the two inputs is a decode signal from an address, and the other input is an address transition detection circuit (Address Transition Detec).
Option circuit; hereinafter, referred to as "ATD circuit". ) Generated from a one-shot signal XE (hereinafter referred to as “OS”).
It is. R71, R72, R73 and R81, R8
2, R83 represent resistors wired to word lines W7 and W8, respectively, and C71 to C76 and C81 to C86
Represents wiring capacitances parasitic on the word lines W7 and W8, respectively. N1 is a word line W7, and N2 is an N channel (Nch) for resetting the word line W8.
It is a transistor. The ATD circuit controls internal operation based on a one-shot pulse signal generated by a transition of an address. This ATD circuit is used for an internal synchronous semiconductor device.

Next, the operation of the circuit of the semiconductor integrated circuit device according to the present invention will be described with reference to FIG. FIG. 3 shows a timing chart for performing an operation of selecting and non-selecting a word line. As shown in FIG. 3, when the address changes at the timing T1, the XE generates an OS in response to the transition, as shown in FIG. In the previous cycle, D1 is LO, the word of W1 is high, and in response to the rising edge of the activated XE, all the two-input NORs are deselected, so that W1 is reset from high to low.

The decode signals D1 and D2 change in response to the address signal while XE is high (upwardly convex) in response to the rising signal of XE, and then in response to the falling of XE in response to the falling of XE. You will select from low to high. W1
Care must be taken that the voltage level crosses at a sufficiently low level at the transition point between and. If the voltage level crosses at a high level, two words are momentarily selected, thereby causing a malfunction. The time for resetting W1 from high to low in FIG. 3 depends on the product of the resistance and capacitance of the word line, and also depends on the size of the gate width W of the two-input NOR. If the ON resistance of the Nch transistor constituting the two-input NOR is made sufficiently smaller than the wiring resistance of the line, the time generally depends on the product of the resistance of the word line and the capacitance. Normally, in order to realize high-speed access, word lines are run in parallel with polysilicon wiring and aluminum wiring, and a part of them is brought into contact with each other as appropriate, adopting a method of reducing word resistance. I have.

Products that do not require very high-speed access have a structure in which polysilicon and aluminum cannot be run in parallel due to the layout pattern of the memory cells. Since the word line is composed of the word lines alone, the resistance of the word line increases, and as a result, the reset time is long. For example, in this case, if the method of crossing the word lines at a sufficiently low voltage level is adopted, it is necessary to make the OS width, that is, the width of XE sufficiently wide. In such a method, it is necessary to adjust the OS width in accordance with the wiring resistance and the capacitance of the word line. As described above, when the product of the wiring resistance and the wiring capacitance of the word line is large, It takes a long time to reset the line,
When the OS width is large and the product of the wiring resistance and the wiring capacitance of the word line is small, the reset time of the word line is short.
Reduce the S width.

The reset time T of the word line W1 is as follows: r1 is the resistance value of the wiring resistance R1 of the word line W1, and c1 is the sum of the capacitance values of the wiring capacitances C11 and C12 of the word line W1.
It can be expressed by the following equation (1). T = c1 × r1 (1) For example, in an SRAM configured to drive 256 cells per word line, the design rule is 0.3 to 0.4.
In the case of a product conforming to the μm process rule, r1 consisting of a word line consisting only of polysilicon is about several tens of KΩ,
c1 is usually of the order of a sufficient number pF (subpicofarad). Assuming that r1 is 50 KΩ and c1 is 0.3 pF, the reset time T can be simply expressed by the following equation (2). Therefore, the reset time T is obtained by substituting the aforementioned r1 and c1 and T = (1 (2) × c1 × (１ ／) r1 = (１ ／) c1 × r1 (2) 15 nS (nanosecond), and the T needs to be 15 nS or more.

In the semiconductor memory circuit device according to the present invention, since the position of the reset transistor is different,
Reset time is shortened. That is, as shown in FIG.
The wiring portion of the word line is defined as the wiring length L from the near end side of the decoder, the wiring portion on the far end side from N1 is defined as the wiring length M, and similarly, the wiring portion is divided from N1 to the near end side as the wiring portion of the wiring length M. L
The two-input NOR resets the wiring length portion, and the reset time is calculated assuming that the wiring portion having two wiring lengths M is reset by N1. The earliest reset time in such a reset time is when the reset time of the L wiring portion is equal to the reset time of the two M wiring portions.

The reset time of the L wiring portion is TL, and the reset time of the M wiring portion is TM. Since the wiring resistance and the wiring capacitance are proportional to the wiring length, TL and TM become equal. The arrangement position of N1 is obtained by the following equations (3) to (5). TL = TM (3) L × L = 2M × M (4) Therefore, L ² = 2M ² , and L = (2) ^1/2 M ≒ 1.41M (5). Thus, the ratio of L: M is approximately 1.41:
However, in the present invention, the ratio of L: M may be about 1: 1 to 2: 1.

Therefore, as a whole, 1 / (L + M + M) =
1 / 3.41 = 0.293, which indicates that it is better to provide an Nch transistor for reset at a wiring position near 29% from the far end. Comparing the reset time at the position calculated by the above equation with the conventional example, the wiring resistance of the word line W7 is the sum of R71, R72, and R73, 50 kΩ as in the conventional case, and the word line W7. Is the sum of C71 to C76. Here, assuming that the wiring capacitance of the word line 7 is 0.3 pF as in the related art,
In the present invention, the wiring length covered by the two-input NOR is (2) ^1/2 × (1 / (1 + 1 + 1.41)) ≒ 1.41.
/3.41 is 41.3% of the word line. Therefore, the reset time is obtained by the following equation.

T3 ≒ (41.3 / 100) × 50 kΩ × (41.3 / 100) × 0.3 pF (6) By executing the above equation (6), the reset time T
3 is about 2.56 nSec.

Therefore, in the case of resetting only with the two-input NOR, it took 15 nSec conventionally, but in the semiconductor memory circuit device according to the present invention, the reset time becomes 2.56 nSec as described above. The reset time is also improved by about ((15−2.56) / 15) × 100 ≒ 83%. Also, two inputs N
A comparison between the case where the reset is performed at the OR and the far end of the word line and the semiconductor memory circuit device according to the present invention shows that the case where the reset is performed at the two-input NOR and the far end of the word line is 3.75 nSe.
Since the reset time is c, in the present invention, ((3.7)
5−2.56) /3.75) × 100 ≒ 32% and 32
% Reset time has also been improved.

Actually, it is difficult to accurately arrange the Nch reset transistor at a position 29% from the far end of the word line. This is because a cell forms an area for each address or I / O unit, and the minimum unit is an array for every 4 digits, 8 digits, etc., and the layout of circuits around the cell is made regularly. This is because it is very difficult to break the minimum array configuration. By arranging the reset transistor at a position slightly deviated from 4 digits or 8 digits instead of arranging the reset transistor accurately from the far end of the word line as described above, the effects described above can be achieved by the present invention. can get. In addition, the present invention can provide an effect that the reset time is shorter even when the word is greatly deviated from the 29% position, as compared with the case where the word is placed at the far end or the center of the word.

[0032]

According to the present invention, the N-channel reset transistor is arranged at a position about 29% from the far end of the word, so that the conventional word line reset is performed by the two-input NOR of the decoder in the first conventional example. In the second conventional example, in the method of resetting by the two-input NOR and the Nch reset transistor at the far end of the word, the reset time of the word line is 83% as compared with the reset time of the first conventional example. It is possible to reduce the reset time by 32% as compared with the reset time of the second conventional example.

Even if the arrangement position is shifted from the far end of the word by 29%, if the arrangement can be made at the far end from the center of the word, the effect that the reset time can be shortened as compared with the conventional example can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a circuit diagram showing a first conventional example.

FIG. 3 is a diagram showing a timing chart in a conventional circuit.

FIG. 4 is a circuit diagram showing a second conventional example.

FIG. 5 is a circuit diagram showing a third conventional example.

FIG. 6 shows a circuit diagram for accelerating a word set.

[Explanation of symbols]

 XE ATD controlled signal D1, D2 Address decode signal W1 to W8 Word line R1 to R2 Wiring resistance R51 to R52 Wiring resistance R61 to R62 Wiring resistance R71 to R73 Wiring resistance R81 to R83 Wiring resistance C11 to C12 Wiring capacitance C21 To C22 Wiring capacitance C51 to C54 Wiring capacitance C61 to C64 Wiring capacitance C71 to C76 Wiring capacitance C81 to C86 Wiring capacitance 2N1, 2N2 2-input NOR N1, N2 N-channel transistor P1 P-channel transistor IN1 Inverter

Claims (6)

[Claims] 1. A semiconductor integrated circuit device having a reset transistor for resetting a word line, wherein the reset transistor is disposed between a center and a far end of the word line. . 2. The reset transistor according to claim 1, wherein a drain is connected to a word line, a source is connected to GND, and a gate is connected to a signal controlled by an address transition detection circuit. The reset transistor is an N-channel transistor. 2. The semiconductor integrated circuit device according to claim 1, wherein 3. The semiconductor integrated circuit device according to claim 1, wherein the reset transistor is provided at a position shifted from the far end by about 29%. 4. A semiconductor integrated circuit device having a reset transistor for resetting a word line, wherein the semiconductor integrated circuit device has two input means for selecting / non-selecting a word line, A semiconductor integrated circuit device having a first wiring length from the near end of the two-input means, and a second wiring length from the near end to the reset transistor and from the reset transistor to the far end. 5. The semiconductor integrated circuit according to claim 4, wherein a ratio between the first wiring length and the second wiring length is set to be approximately 1.4: 1. apparatus. 6. The word line has a size of 0.3 or 0.4 μm.
2. A method according to claim 1, wherein said information is provided in accordance with a rule.
6. The semiconductor integrated device according to any one of items 5 to 5.