JP2010109232A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve data holding characteristics without increasing the size of a latch part of a latch type memory cell. <P>SOLUTION: Conductive lines (26a and 26b) in the same wiring layer as intrinsic wiring of a flash memory cell transistor are disposed so as to extend in a direction crossing gate electrode wiring (21a and 21c) constituting a storage node of the latch type memory cell. Capacitances are formed at intersections between the gate electrode wiring and the conductive lines, and the conductive lines are maintained at a fixed potential. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a data holding portion. More particularly, the present invention relates to a structure for improving data retention characteristics of a memory cell of a static random access memory (SRAM).

  In a static random access memory (SRAM), a memory cell is composed of a data latch (flip-flop) and a pair of access transistors. The data latch is usually composed of an inverter latch, and complementary data is held in an internal storage node. Since complementary data is held by the inverter latch, unlike a DRAM (dynamic random access memory), a refresh operation for rewriting data is not required in the SRAM. In addition, since the SRAM operates statically, a precharge cycle for precharging the signal line is unnecessary, and the access time is shorter than that of the DRAM. SRAM having such features is widely used for applications requiring high-speed processing such as cache memory.

  In recent years, in a system LSI (large-scale integrated circuit), a logic circuit such as a processor and a plurality of types of memories are integrated on a single semiconductor chip to realize a single processing system. In such an SOC (system-on-chip) that constitutes a system on one semiconductor chip, each device has a low power supply voltage and a low power supply voltage from the viewpoint of reducing power consumption and chip size (system size). A small occupation area is required.

  On the other hand, as the process becomes finer, the capacity of the internal storage node of the memory cell decreases in the SRAM. In this case, there is a problem that resistance to soft errors in which data in the storage node is inverted due to alpha rays or the like is lowered, and stability of data retention is impaired.

  An example of a configuration for improving the soft error tolerance is disclosed in, for example, Japanese Patent Application Laid-Open No. 2008-135461. In the configuration disclosed in Patent Document 1, a flash memory cell is formed of a stacked gate transistor having a floating gate and a control gate. A capacitive element is connected to the storage node of the SRAM cell using a process of manufacturing a floating gate and a control gate of the flash memory cell. Specifically, as an example, the gate electrodes of the load transistor and the drive transistor of the SRAM cell are formed of wirings in the same wiring layer as the floating gate, and the wirings of the same wiring layer as the control gate are connected to the gate electrodes of the load transistor and driver transistor. They are arranged and used as capacitor electrodes. This capacitor electrode is connected to the storage node of the cell.

In the SRAM cell, a capacity is additionally connected to the internal storage node to compensate for capacity reduction due to miniaturization of the storage node and to improve data retention characteristics.
JP 2008-135461 A

  In the configuration disclosed in Patent Document 1 described above, a flash memory and an SRAM are integrated together with a processor on the same semiconductor substrate (chip). A capacitance is formed using the manufacturing process of the floating gate and control gate of the memory cell of the flash memory, and this capacitance is connected to the storage node. By using the gate manufacturing process of the flash memory cell, the addition of a manufacturing process due to capacitance formation is avoided.

  However, in the SRAM cell structure of Patent Document 1, a capacitor electrode is arranged opposite to the gate electrode of the driver transistor and / or load transistor, and this capacitor electrode is connected to an internal cell storage node. Therefore, it is necessary to provide a capacity for each memory cell, pattern a capacity electrode for each memory cell, and pattern a wiring for connecting the capacity electrode to an internal storage node. Therefore, from the viewpoint of reducing the layout area of the SRAM cell and simplifying the manufacturing process, it can be said that there is still room for improvement in the structure of the SRAM cell of Patent Document 1.

  In semiconductor integrated circuit devices, a latch circuit is often used. For example, in a logic circuit or the like, a latch circuit is used to increase the processing speed by transferring data in synchronization with a clock signal. In addition, a latch circuit is used in a register circuit or the like to temporarily hold data. Even in such a latch circuit, there is a problem that the data retention characteristic is deteriorated with the miniaturization.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that can increase the capacity of a data holding node of a data holding unit without increasing the number of manufacturing steps.

  Another object of the present invention is to provide a semiconductor integrated circuit device capable of increasing the capacity of a data storage node of an SRAM cell without increasing the cell occupation area and the manufacturing process.

  In the semiconductor integrated circuit device according to the present invention, the conductive line of the same wiring layer as the wiring of the unique wiring layer of the flash memory cell formed on the same semiconductor chip is opposed to the gate electrode of the data holding transistor of the memory cell. To place.

  In one embodiment, a semiconductor integrated circuit device according to the present invention is common to memory cells arranged in alignment with a direction intersecting with an extending direction of a gate electrode of a cell transistor coupled to a storage node of the memory cell. The conductive line is disposed so as to face the gate electrode.

  In another embodiment, in a device having a non-volatile memory and a data holding portion, the same wiring as a specific wiring of the non-volatile memory cell is formed so as to cross a transistor having a gate electrode coupled to a data holding node. Arrange the wiring of the wiring layer.

  Utilizing the manufacturing process of the flash memory cell, a conductive line extending continuously is formed using a wiring layer unique to the flash memory cell, and a capacitance is formed between the counter gate electrode wiring. Since the gate electrode wiring is coupled to the data holding node, there is no need to provide a connection wiring between the conductive line and the holding node, and the capacity of the data holding mode is avoided by avoiding an increase in manufacturing process and an increase in layout area. Can be increased.

  In particular, in one embodiment, a conductive line is disposed in common to the memory cells that face the gate electrode of the SRAM cell transistor and are aligned in the gate electrode extending direction of the memory cell. There is no need to pattern the electrodes, and the manufacturing process is simplified. In addition, since the conductive line does not need to be connected to the storage node for each memory cell, contact with the capacitor electrode is not required in each cell, and an increase in the layout area of the cell can be suppressed.

  Further, the capacity of the storage node can be increased without changing the layout of the data holding unit and without increasing the number of manufacturing steps, and the data can be held stably.

[Embodiment 1]
FIG. 1 schematically shows an example of the entire configuration of a semiconductor integrated circuit device to which a semiconductor memory device (SRAM) according to the first embodiment of the present invention is applied. In FIG. 1, a semiconductor integrated circuit device 1 includes a processor 2, a flash memory 4, and a static RAM (SRAM) 6. These processor 2, flash memory 4 and static RAM 6 are coupled to each other via an internal bus 8.

  The flash memory 4 stores an OS (operating system) used by the processor 2, data such as image / sound, unique information (identification information, ID information) of the semiconductor integrated circuit device, and the like. The static RAM (SRAM) 6 stores data used by the processor 2.

  A semiconductor integrated circuit device 1 shown in FIG. 1 is a system LSI, and is integrated on one semiconductor substrate (chip). The processor 2, the flash memory 4, and the static RAM are formed in parallel using the same manufacturing process.

  FIG. 2 is a diagram schematically showing a cross-sectional structure of the memory cell of the flash memory 4. In FIG. 2, the flash memory cell is formed in impurity regions 12a and 12b formed on the surface of the semiconductor substrate region 10 and a part of the surface of the semiconductor substrate region 10 between the impurity regions 12a and 12b. The gate insulating film 13, the control gate electrode 14 formed on the gate insulating film 13, and the surface of the semiconductor substrate region 10 adjacent to the gate insulating film 13 and the side wall of the control gate electrode 14 are formed in an L shape. A multilayer insulating film 16 and a memory gate electrode 18 formed on the multilayer insulating film 16 are included.

  The multilayer insulating film 16 is a so-called ONO film composed of an oxide film, a nitride film, and an oxide film, and stores information in a nonvolatile manner by accumulating charges in the nitride film (N film).

  Control gate electrode 14 is coupled to control gate line CG, and memory gate electrode 18 is coupled to memory gate line MG. Impurity region 12a is coupled to bit line BL, and impurity region 12b is coupled to source line SL.

  In this flash memory cell, a select transistor (access transistor) is formed by the control gate electrode 14, the impurity region 12a, the gate insulating film 13, and the semiconductor substrate region 10 below the gate insulating film 13, and the memory gate electrode 18, impurity A memory transistor is formed by the region 12b, the multilayer insulating film 16, and the semiconductor substrate region 10 below the multilayer insulating film 16.

  In the flash memory cell shown in FIG. 2, data is written, erased and read as follows. That is, at the time of data writing, a positive write high voltage is applied to the source line SL, and the control gate line CG has a voltage at which a weak channel (weak inversion layer) is formed below the gate insulating film 13. Is applied. A positive write high voltage is also applied to memory gate line MG. Under this condition, a current flows from the source line SL toward the bit line BL in the selected memory cell. The voltage supplied from the control gate line CG to the control gate electrode 14 is relatively low, the inversion layer formed below the gate insulating film 13 is a weak inversion layer, and its resistance value is relatively high. Therefore, the voltage between the source line SL and the bit line BL is applied substantially between the regions under the gate insulating film 13, and a large electric field is generated in the boundary region between the multilayer insulating film 16 and the gate insulating film 13. Accordingly, hot electrons are generated from the current injected from the source line SL by this high electric field, and the generated hot electrons are attracted in the direction of the memory gate electrode by the positive voltage of the memory gate electrode 18, and the multilayer insulating film 16 is stored in a nitride film included in 16. In the written state, the threshold voltage of the memory transistor is high.

  In the non-selected memory cell, the bit line BL and the control gate line CG are at the same voltage level, no channel is formed below the gate insulating film 13, and a current flows between the source line SL and the bit line BL. No data is written.

  At the time of erasing, the source line SL is set to a positive erasing high voltage level, and the bit line BL and the control gate line CG are set to 0V. Memory gate line MG is set to a negative voltage level. In this case, a hot hole is generated by a high electric field between the impurity region 12b and the control gate electrode 18, and the generated hot hole is injected into the nitride film of the multilayer insulating film 16 by band-to-band tunneling, and is accumulated until then. The electron concentration of the nitride film of the multilayer insulating film 16 is neutralized by the combination of electrons and holes thus formed. In this erase state, the threshold voltage of the memory transistor is low.

  At the time of data reading, source line SL is set to the ground voltage level, bit line BL is applied with a positive read voltage, and control gate line CG is supplied with a higher positive voltage than at the time of writing. The Memory gate line MG is set to a voltage level between the threshold voltage of the erase state and the write state.

  In the memory cell, when electrons are injected into the nitride film of the multilayer insulating film 16, the memory cell is in a writing state, a threshold voltage is high, and a current flowing through the bit line BL is small. On the other hand, when the memory cell is in an erased state, that is, when the nitride film of the multilayer insulating film 16 is in a neutral state, the threshold voltage is low, and a relatively large amount of bit lines BL to source line SL Current flows. By detecting the current flowing through the bit line BL, the data stored in the memory cell is read.

  FIG. 3 is a diagram showing an example of an electrically equivalent circuit of a memory cell of static RAM (hereinafter referred to as SRAM) 6 according to the first embodiment of the present invention. In FIG. 3, the SRAM cell includes two P-channel MOS transistors (insulated gate field effect transistors) PQ1 and PQ2, and four N-channel MOS transistors NQ1-NQ4. MOS transistors PQ1 and NQ1 constitute a CMOS inverter, and MOS transistors PQ2 and NQ2 constitute another CMOS inverter. The gates of MOS transistors NQ1 and PQ1 are coupled to storage node ND1, and the gates of MOS transistors PQ2 and NQ2 are coupled to storage node ND2. MOS transistors NQ3 and NQ4 are selectively turned on according to the signal potential on word line WL, respectively, and when turned on, couple storage nodes ND1 and ND2 to bit lines BL and / BL, respectively.

  Therefore, storage nodes ND1 and ND2 hold complementary data by an inverter latch composed of MOS transistors PQ1, PQ2, NQ1, and NQ2.

  A conductive line 19 is provided in common for the SRAM cells aligned in the column direction (bit line extending direction). The gate electrodes of MOS transistors PQ1, PQ2, NQ1 and NQ2 are formed of wirings in the same wiring layer as the control gate line CG (control gate electrode) of the flash memory cell shown in FIG. 2, and this conductive line 19 is connected to the memory gate line. It is composed of wiring of the same wiring layer as MG. In the flash memory cell, the gate has a non-hierarchical structure, the control gate electrode 14 constitutes a part of the control gate electrode line CG, and the memory gate electrode 18 constitutes a part of the memory gate line MG. To do. In the flash memory cell, when the gate is composed of a high-resistance electrode wiring and an upper-layer low-resistance metal wiring, wiring in the same wiring layer as the control gate electrode 14 and the memory gate electrode 18 of the transistor of the lower-layer memory cell Thus, the gate electrode and the conductive line of the SRAM cell transistor are formed.

  The gates of MOS transistors PQ1 and PQ2 and conductive line 19 are arranged to intersect each other, and a parasitic capacitance Cp is formed in this intersecting region. Parasitic capacitance Cp is coupled to storage nodes ND1 and ND2 via the gate electrodes of MOS transistors (load transistors) PQ1 and PQ2, respectively. Conductive line 19 is coupled to, for example, the ground node and is maintained at a constant voltage level to suppress potential fluctuations at storage nodes ND1 and ND2.

  Conductive line 19 is composed of a wiring of the same wiring layer as memory gate line MG (memory gate electrode), and the gate electrodes of MOS transistors PQ1 and PQ2 are formed of a wiring of the same wiring layer as control gate line CG. In parallel with the manufacturing process of the flash memory cell, the conductive line 19 can be formed in the SRAM cell, and the increase in the number of manufacturing processes is suppressed. The conductive line 19 is provided in common to the SRAM cells aligned in the column direction, and no connection node (contact) for this capacitance is provided in the SRAM cell formation region. Therefore, when the parasitic capacitance Cp of the conductive line 19 is added, the layout pattern of the SRAM cell is not required to be changed, only the linear conductive line 19 is used, and the complexity of the pattern layout can be suppressed. It can be simplified. Further, by maintaining conductive line 19 at a fixed potential such as a ground voltage, the capacitor electrode can be set at a constant voltage level, and potential fluctuations at storage nodes ND1 and ND2 can be reliably suppressed.

  FIG. 4 schematically shows a planar layout of the SRAM cell shown in FIG. FIG. 4 shows a layout from the active region to the first metal wiring. In FIG. 4, an N channel MOS transistor is formed in each of P wells PWa and PWb, and N well NW forming a P channel MOS transistor is arranged between P wells PWa and PWb. These wells PWa, PWb and NW are formed so as to continuously extend in the Y direction.

  Active regions 20a and 20b are arranged in P wells PWa and PWb, respectively. Each of these active regions 20a and 20b has a region having a large length in the X direction and a region having a small length in the X direction.

  In the N well NW, rectangular active regions 20c and 20d that are long in the Y direction are arranged opposite to each other and shifted in the Y direction. A gate electrode wiring 21a is arranged so as to cross a wide region in the X direction of active region 20a and active region 20c. This gate electrode wiring 21a is arranged in the SRAM cell so as to extend in the X direction to the active region 20d.

  Further, the gate electrode wiring 21b is arranged so as to cross the narrow region of the active region 20a along the X direction. Gate electrode interconnection 21b is formed to extend to the boundary of P well PWa. A first metal wiring 24a having a rectangular shape that is long in the X direction is arranged with respect to a lower end portion in the Y direction of the active region 20a. The first metal wiring 24a is electrically connected to the lower end of the active region 20a in the Y direction via the contact 23a, and is connected to the upper layer wiring at the memory cell boundary region at the other end. One via 24a is provided.

  A first metal wiring 22b having a rectangular shape that is long in the Y direction is arranged at a cell boundary portion of the gate electrode wiring 21b. The first metal wiring 22b is electrically connected to the gate electrode wiring 21b through a contact, and a first via 24b for connection to the upper layer wiring is provided at a position different from the contact formation portion.

  A first metal wiring 22c is arranged in the upper layer of the gate electrode wiring 21b adjacent to the gate electrode wiring 21b in the narrow region of the active region 20a. The first metal wiring 22c is electrically connected to a narrow region of the active region 20a formed in the lower layer through a contact 23c. The first metal wiring 22c is provided with a first via 24c for electrical connection with the upper layer wiring.

  Also in N well NW, first metal interconnection 22d is arranged at the lower end of Y direction of active region 20c. First metal interconnection 22d is coupled to active region 20c through a contact (not shown). The first metal wiring 22d is also provided with a first via 24d for connection to the upper layer wiring. A lateral L-shaped first metal wiring 22e is provided for active regions 20a and 20c. The first metal wiring 22e is electrically connected to the active region 20c and the gate electrode wiring 21c through a shared contact 25a in a long region in the X direction.

  Also for the active region 20d, the first metal wiring 22f is provided at a point-symmetrical position with respect to the first metal wiring 22d. The first metal wiring 22f is electrically connected to the upper end portion in the Y direction of the active region 20d through a contact (not shown), and a first via 24e for connection with the upper layer wiring is provided.

  A first metal wiring 22g is provided at the wide end of the active region 20b. The first metal wiring 22g is electrically connected to the active region 20b through a contact 23e. The first metal wiring 22g is provided with a first via 24f for connection to the upper layer wiring.

  The first metal wiring 22i is arranged in a point-symmetric shape with respect to the first metal wiring 22e so as to face the first metal wiring 22g and the gate electrode wiring 21c. The first metal wiring 22i is electrically connected to the region between the gate electrode wirings 21c and 21d of the active region 20b through the contact 23f, and is connected to the active region 20d and the gate electrode wiring 21a through the shared contact 25b. Electrically connected.

  For gate electrode wiring 21d, first metal wiring 22j is provided at the memory cell boundary. The first metal wiring 22j is electrically connected to the gate electrode wiring 21d through the contact 23g, and a first via 24h for connection to the upper wiring is provided at an end different from the formation position of the contact 23g. .

  A first metal wiring 22h is provided in a narrow region at the lower end of the active region 20b in the Y direction. The first metal wiring 22h is electrically connected to the lower active region 20b through a contact (not shown), and a first via 24g for connection to the upper layer wiring is provided.

  In the boundary region between N well NW and P wells PWa and PWb, conductive wirings 26a and 26b in the same wiring layer as memory gate lines (MG) are provided so as to continuously extend in the Y direction. These conductive wirings 26a and 26b correspond to the conductive lines 19 shown in FIG. These conductive wirings 26a and 26b are wirings above the gate electrode wirings 21a-21d, and are wirings below the first metal wirings 22a-22j.

  The gate electrode wirings 21a-21d extend in the X direction in the SRAM cell and are arranged in alignment and are formed of wirings in the same wiring layer as the control gate line (CG) of the flash memory cell, and the memory gate line (MG) Formed earlier. This is because, after the memory gate line MG forms the control gate line CG, the memory gate line is usually formed by a process similar to the side wall insulating film forming process of the so-called MOS transistor in a self-aligned manner. . Capacitance elements are formed at the intersections of the conductive lines 26a and 26b and the gate electrode wirings 21a and 21c.

  By forming the conductive wirings 26a and 26B by using wirings other than the wirings unique to the flash memory cell, that is, the wiring of the wiring layer used for the position of the SRAM cell, wiring for forming the capacitance is formed. It is not necessary to use an extra manufacturing process for the arrangement, and an increase in the manufacturing process can be avoided.

  In the layout shown in FIG. 4, driver electrode (N channel MOS transistor) NQ1 is formed by gate electrode interconnection 21a and active region 20a, and load transistor (P channel MOS transistor) PQ1 is formed by gate electrode interconnection 21a and active region 20c. It is formed. Active transistor 20a and gate electrode interconnection 21b form access transistor (N channel MOS transistor) NQ3. The active region 20d and the gate electrode wiring 21c form a load transistor PQ2, and the active region 20b and the gate electrode wiring 21c form a driver transistor NQ2. Access transistor NQ4 is formed of active region 20b and gate electrode interconnection 21d.

  The first metal wirings 22b and 22j constitute part of the word line WL, and the first metal wirings 22d and 22f constitute part of the high-side power supply line that supplies the power supply voltage (cell high-side power supply voltage VDD). First metal interconnections 22a and 22g constitute part of a low-side cell power supply line for transmitting a ground voltage (cell low-side power supply voltage GND).

  First metal interconnections 22c and 22e constitute part of bit lines BL and / BL, respectively. Gate electrode interconnections 21a-21d each constitute a gate electrode of a MOS transistor at the intersection with the corresponding active region.

  FIG. 5 schematically shows a planar layout of the upper layer wiring in the planar layout shown in FIG. FIG. 5 also shows the arrangement of the first vias shown in FIG. In FIG. 5, second metal wirings 30a, 30b, 30c are arranged so as to be spaced apart from each other and continuously extending in the Y direction. Second metal interconnection 30a forms bit line BL, and is coupled to access transistor NQ3 formed in active region 20a shown in FIG. 4 via first via 24c. Second metal interconnection 30b constitutes a high-side power supply line for supplying power supply voltage VDD, and has protrusions connected to first vias 24d and 24e shown in FIG. These protrusions are arranged point-symmetrically with respect to the central position of the memory cell formation region.

  Second metal interconnection 30c forms complementary bit line / BL, and is coupled to access transistor NQ4 (active region 20b) shown in FIG. 4 through first via 24g.

  Rectangular-shaped second metal intermediate wires 30e and 30f are arranged apart from each other in the Y direction outside second metal wire 30a. Second metal intermediate interconnection 30e is electrically connected to first via 24b (not shown in FIG. 5) shown in FIG. 4, and is accordingly coupled to the gate electrode of access transistor NQ3 shown in FIG. Second metal intermediate interconnection 30f is electrically connected to first via 22a shown in FIG. 4, and is electrically connected to driver transistor NQ1 in active region 20a shown in FIG.

  Second metal intermediate wires 30h and 30g are arranged outside second metal wire 30c. Second metal intermediate interconnection 30h is coupled to first via 24g shown in FIG. 4, and is coupled to the source node of driver transistor NQ2. Second metal intermediate interconnection 30g is coupled to first via 24h shown in FIG. 4 and connected to the gate of access transistor NQ4.

  Further, third metal wirings 32a, 32b and 32c are arranged extending continuously along the X direction and spaced from each other. The third metal wiring 32a is electrically connected to the second metal wiring 30h via a second via (not shown). Second metal interconnection 32b is electrically connected to second metal intermediate interconnections 30e and 30g through second vias 37a and 37b, respectively. Second metal interconnection 32c is electrically connected to second metal intermediate interconnection 30f through a second via (not shown in FIG. 5).

  Second metal interconnections 32a and 32c constitute part of the low-side power supply line transmitting ground voltage GND, and third metal interconnection 32b constitutes part of word line WL. By using the second metal wirings 32a and 32c, the low-side power supply line can be arranged in a mesh shape with the main low-side power supply line in the upper layer, and the power supply line can be strengthened. Reduce the resistance of the low-side power line.

  Wide fourth metal wirings 34a and 34b are arranged extending continuously along the Y direction outside second metal wirings 30a and 30c, that is, at the boundary of the memory cell formation region. The fourth metal wiring 34a is electrically connected to the third metal wiring 32a through the third via 36a, and is electrically connected to the third metal wiring 32c through the third via 36b.

  The fourth metal wiring 34b is electrically connected to the third metal wiring 32a through the third via c, and is electrically connected to the third metal wiring 32c through the third via 36d. The fourth metal wirings 34a and 34b for transmitting the ground voltage GND are arranged in the boundary region of the memory cell MC, and are electrically connected to the third metal wiring, respectively. Strengthen and stabilize the ground voltage.

  As shown in FIGS. 4 and 5, even if the conductive wirings 26a and 26b constituting the conductive line 19 are continuously extended in the Y direction, the conductive lines 26a and 26b are not connected to the first metal wiring. It is a lower wiring layer and an upper wiring than the gate electrode wiring that forms the gate of the memory cell transistor, and an increase in the layout area of the SRAM cell MC is sufficiently suppressed. Further, a capacitance is simply formed at the intersection of the gate electrode wiring and the conductive wirings 26a and 26b, and a contact for connecting the capacitance to the storage node is not necessary, thereby avoiding a complicated layout. Further, only the conductive wiring is disposed in the well boundary region, and no SRAM cell transistor is formed in this region. Therefore, the conductive wirings 26a and 26b can be arranged without affecting the arrangement of the SRAM cell transistors, and an increase in the SRAM cell layout area and a complicated wiring layout can be avoided.

  FIG. 6 schematically shows a cross-sectional structure along the Y direction of gate electrode wiring 21a and conductive wiring 26a shown in FIG. In FIG. 6, an element isolation film (shallow trench isolation film: STI film) 42 is provided on a substrate region 40. A gate electrode wiring 44 (21 a) is disposed on the element isolation film 42. The gate electrode wiring 44 (21a) is formed of wiring in the same wiring layer as the control gate electrode (14) and the control gate line (CG) of the flash memory cell. An interlayer insulating film 46 is provided on the gate electrode wiring 44, and a conductive line 48 (26 a) is disposed on the insulating film 46. The conductive line 48 (conductive wiring 26a) is formed of a wiring in the same wiring layer as the memory gate electrode (18) and the memory gate line (MG) of the flash memory cell.

  Therefore, the interlayer insulating film 46 may be a multilayer insulating film (ONO film) or a single-layer insulating film (gate insulating film). A capacitor Cp is formed at the opposing portion of the conductive line 48 and the gate electrode wiring 44. Conductive line 48 is maintained at power supply voltage VDD or ground voltage GND through a fixed voltage source. Since the gate electrode wiring 44 (21a) is coupled to the storage node of the SRAM cell, a capacitor whose electrode is set to a fixed voltage is added to the storage node.

  FIG. 7 schematically shows a planar layout when SRAM cells (memory cells) MC shown in FIG. 4 are arranged in 3 rows and 2 columns. FIG. 7 shows a layout of memory cells MC0 to MC5. The planar layout of these memory cells MC0 to MC5 is a mirror-symmetric arrangement with respect to the X direction and the Y direction. Therefore, in FIG. 7, the same reference numerals are assigned to the portions corresponding to the components of the memory cell shown in FIG. 4 for the memory cell MC0, and the detailed description thereof is omitted.

  In FIG. 7, the first metal wiring 22f is electrically connected to the active region 20d through the contact 23k in the memory cell boundary region, and the first metal wiring 22d is activated through the contact 23m. The region 20c is electrically connected in the memory cell boundary region.

  As shown in FIG. 7, active regions 20a and 20b are arranged to extend continuously in the Y direction, and access transistor formation regions and driver transistor formation regions are provided alternately. In addition, with the mirror-symmetric layout in the X direction and the Y direction, contacts and vias can be shared in adjacent memory cells (SRAM cells), and the memory cell layout area can be reduced.

  Conductive wirings 26a and 26b include a PMOS formation region (N well NW) that forms a P channel MOS transistor (load transistor) and an NMOS formation region (P wells PWa and PWb) that form an N channel MOS transistor (access transistor and driver transistor). ). A transistor (active region) is not arranged in the boundary region of the MOS formation region. The conductive wirings 26a and 26b are wirings inherent in the flash memory cell. In the SRAM cell, the wirings in the same wiring layer as the memory gate wiring are used for forming transistors and connecting the transistors. Not used. Therefore, the conductive lines 26a and 26b for adding capacitance can be arranged without affecting the arrangement of the transistors of the memory cell.

  FIG. 8 is a diagram schematically showing the planar layout of the second metal wiring in the upper layer of the planar layout shown in FIG. 7 together with the layout of the active region and the gate electrode wiring. Also in FIG. 8, in the memory cells MC0 to MC5, reference numerals are assigned to the components related to the second metal wiring, the active region, and the gate electrode wiring among the components of the memory cell MC0.

  Also for the second metal wiring, the second metal wirings 30e, 30f, 30h and 30g are arranged in the boundary region of the memory cell (SRAM cell) MC, and these metal wirings are also mirrored along the X direction and the Y direction. Arranged symmetrically. The second metal wiring 30e is electrically connected to the lower first metal wiring (22b) via the first via 24b, and the second metal wiring 30f is connected to the lower first metal wiring (via the first via 24a). 22a).

  Second metal interconnection 30a is connected to lower first metal interconnection (22c) via first via 24c and further electrically connected to the active region of the access transistor via lower contact (20c). Second metal interconnection 30b is electrically connected to lower first metal interconnections 22d and 22f through first vias 24d and 24e, respectively, and further, memory cells are formed in active regions 20c and 20d through contacts (not shown). Connected at region boundaries.

  The second metal wiring 30c is electrically connected to the lower first metal wiring (22h) through the first via 24g. Second metal interconnections 30h and 30g are electrically connected to lower first metal interconnections 22g and 22j through first vias 24f and 24h, respectively.

  Second metal wirings 30a and 30c are wirings higher than conductive wirings 26a and 26b. Conductive wirings 26a and 26b are lower-layer wirings than the first metal wiring, and do not affect the arrangement of the first vias 24a-24h.

  Therefore, conductive wirings 26a and 26a have no influence on the arrangement of the first and second metal wirings, so that the planar layout of memory cells (SRAM cells) MC0-MC5 is provided with conductive wirings 26a and 26b. It can be set to the same layout as the planar layout in the case of no.

  FIG. 9 is a diagram showing the layout of the third metal wiring together with the layout of the active region and the gate electrode wiring. Also in FIG. 9, the memory cells (SRAM cells) MC0 to MC5 are arranged in a mirror-symmetric layout, have the same layout, and the components of the portion related to the third metal wiring for the memory cell (SRAM cell) MC0 and A reference number is assigned to the active region.

  In FIG. 9, the third metal wirings 32a, 32b, and 32c extend continuously in the X direction and are spaced apart from each other, like the planar layout shown in FIG. The third metal wiring 32a is electrically connected to the lower second metal wiring (30h) via the second via 37d, and is further connected to the lower second metal wiring (not shown) via the second via (24f). 30h). The third metal wiring 30a forms a local ground line for transmitting the ground voltage (low-side cell power supply voltage) GND.

  Third metal interconnection 32b is electrically connected to the lower second metal interconnection (30e and 30g) via second vias 37a and 37b arranged opposite to the boundary region along the X direction of memory cell MC0. Connected. Third metal interconnection 32b is further electrically connected to lower gate electrode interconnections (22b and 22j) via a contact and an intermediate metal interconnection. The third metal wiring 30b is provided in common to the SRAM cells aligned in the X direction and constitutes a word line.

  The third metal wiring 32c is electrically connected to the lower second metal wiring (30f) through the second via 37c. Contacts to the bit lines are arranged in mirror symmetry in the memory cell formation region, and contacts for ground voltage are also arranged in the memory cell formation region as mirror objects. Therefore, one bit line contact and a ground voltage contact can be arranged with a margin on one side of the memory cell formation region boundary. Further, by utilizing the two third metal wirings 32a and 32c, the ground voltage contact is arranged in a mirror-symmetric manner with respect to the memory cell arranged in the mirror symmetry, and the ground voltage is supplied to the memory cell. can do.

  Also in the arrangement of the third metal wiring, the via is arranged at the boundary of the memory cell formation region, and the arrangement of the conductive wirings 26a and 26b has no influence on the arrangement of the third metal wiring.

  FIG. 10 schematically shows an arrangement of fourth metal wirings in the upper layer of the planar layout shown in FIG. Also in FIG. 10, among the memory cells MC0 to MC5, reference numerals are assigned to components and active regions of portions related to the fourth metal wiring arranged for the memory cell MC0.

  Fourth metal interconnections 34a and 34b are arranged extending continuously in the Y direction in the boundary region along each X direction of the memory cell formation region. Fourth metal interconnection 34a is electrically connected to lower third metal interconnections 32a and 32c shown in FIG. 9 through third vias 36a and 36b. Fourth metal interconnection 34b is electrically connected to second metal interconnections 32a and 32c shown in FIG. 9 through third vias 36c and 36d.

  In the planar layouts shown in FIGS. 7 to 10, the conductive wirings 26a and 26b are prevented from overlapping with the wiring extending in the Y direction. Therefore, an increase in the height of the memory cell due to the arrangement of conductive wirings 26a and 26b is suppressed, and adverse effects on the arrangement of contacts / vias and wirings are prevented.

[Power supply fixing mode 1 of conductive wire]
FIG. 11 schematically shows a structure of the array portion of the SRAM according to the first embodiment of the present invention. In FIG. 11, the memory cell array is divided into subarrays 50a and 50b, and a tap region 52 is provided between these subarrays 50a and 50b. In each of subarrays 50a and 50b, SRAM cells (memory cells) MC are arranged in a matrix. In FIG. 11, only the gate electrode wiring 21 of the SRAM cell is typically given a reference number. Gate electrode wiring 21 for the load transistor and the driver transistor extends in the X direction in the SRAM cell. The gate electrode wiring for the access transistor is shared by two SRAM cells adjacent in the X direction.

  Conductive wirings 26a and 26b are arranged corresponding to each SRAM cell column, extending in the Y direction so as to cross subarrays 50a and 50b and tap region 52. Conductive wirings 26a and 26b are arranged corresponding to well boundaries. In the well, P wells PWa and PWb in which N channel MOS transistors (access transistors and driver transistors) are arranged and N well NW in which P channel MOS transistors (load transistors) are arranged are alternately arranged. P wells PWa and PWb are shared by adjacent memory cells in the X direction.

  In the tap region 52, an N-type high concentration impurity region 54 for applying a bias voltage is arranged for the N well NW, and for the P wells PWa and PWb, a high concentration P type for applying a bias voltage. Impurity region 56 is arranged. These impurity regions 54 and 56 are arranged in alignment in the X direction, and first metal wirings 60a and 60b extending continuously in the X direction are arranged on both sides in the Y direction of these impurity regions 54 and 56. The These first metal wirings 60a and 60b are wirings for transmitting ground voltage GND, respectively.

  As shown in FIG. 10, the ground line (low-side power line) for transmitting the ground voltage using the fourth metal wiring (34a, 34b) is arranged in the SRAM cell column boundary region. The ground line of the fourth metal wiring (fourth metal ground line) is electrically connected to the third metal wiring extending in the X direction as shown in FIG. 9, and finally the driver transistor of the SRAM cell is connected. A ground voltage is supplied to the source region (active region).

  In the tap region 52, the ground voltage is supplied to the first metal wires 60a and 60b extending in the X direction from the upper third metal wire via the second metal wire (not shown). Vias 63 are provided at the intersections of the first metal wires 60a and 60b and the conductive wires 26a and 26b, and the ground voltage GND is supplied to the conductive wires 26a and 26b. In tap region 52, intermediate wirings 64 and 65 made of a first metal wiring are provided to supply ground voltage to impurity region 56 and the gate electrode and active region of the dummy transistor adjacent in the Y direction.

  The SRAM cell transistors arranged in alignment on both sides of the tap region 52 are shape dummy cells, and are arranged to maintain the regularity of the repetition of the pattern of the SRAM cell. The gate electrode and the active region of these shape dummy cells are Fixed to ground voltage level. Impurity region 56 is coupled to first metal interconnections 65 and 64 through contact 66 and receives a ground voltage.

  On the other hand, with respect to impurity region 54, a power line (30a, 30b) of the second metal wiring is arranged on N well NW between conductive wirings 26a and 26b, and the first metal wiring coupled to the second metal wiring. The power supply voltage VDD is supplied through 61 and the contact 62. Thereby, in tap region 52, ground voltage GND is supplied to P wells PWa and PWb, and power supply voltage VDD is supplied to N well NW. Conductive wirings 26a and 26b constituting the capacitor electrode are fixed to the level of ground voltage GND by using a wiring for supplying a well bias voltage in tap region 52.

  The tap areas 52 are arranged at predetermined intervals in the Y direction in the memory cell array (when the memory cell array is divided into subarray blocks, the tap areas 52 are provided in the subarray block boundary areas). Similarly, the well bias voltage is also supplied from the tap region to the end of the memory cell sub-array in the Y direction.

  By fixing the voltage of the conductive wiring to the well bias voltage in the tap region for applying the well bias, there is no need to newly arrange another region for fixing the potential of the conductive wiring (conductive line), and the array area is increased. Is suppressed, and an increase in the manufacturing process is also avoided.

[Power supply fixing mode 2 of conductive wire]
FIG. 12 schematically shows a modification of the fixed potential supply mode of the capacitor electrode of the SRAM according to the first embodiment of the present invention. The arrangement shown in FIG. 12 is different from the arrangement shown in FIG. 11 in the arrangement of the first metal wiring with respect to the impurity regions 54 and 56.

  That is, in tap region 52, impurity region 54 is provided for N well NW, and impurity region 56 is provided for P wells PWa and PWb. The power supply voltage VDD is supplied to the impurity region 54 via the first metal intermediate wiring 70 and the contact 62. The first metal intermediate wiring 70 is coupled to a high-side power supply line constituted by an upper second metal wiring, and is extended to the ends of the conductive wirings 26a and 26b.

  First vias 72a and 72b are provided at intersections of the first metal intermediate wiring 70 and the conductive wirings 26a and 26b, respectively, to electrically couple the first intermediate wiring 70 and the conductive wirings 26a and 26b. As a result, the power supply voltage VDD is supplied to the conductive wiring lines 26 a and 26 b through the first metal intermediate wiring 70 from the high-side power supply line configured by the upper second metal wiring. Therefore, in the configuration shown in FIG. 12, the capacitor electrode is fixed at power supply voltage VDD.

  For impurity region 56, first metal wires 64 and 65 are coupled to first metal wires 60a and 60b, respectively, and supplied with ground voltage GND. These first metal wires 64 and 65 are separated from conductive wires 26a and 26b.

  Other configurations of the memory array and tap region in FIG. 12 are the same as those shown in FIG. 11, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIGS. 11 and 12, the conductive wiring under the first metal wiring is utilized by using the first metal wiring for supplying a bias voltage (VDD or GND) to the tap (impurity region for applying the substrate bias) in the tap region. A desired voltage (VDD or GND) is supplied to 26a and 26b. Therefore, the conductive line 19 (conductive wirings 26a and 26b) is set to a fixed potential without affecting the wiring layout of the tap region and without adversely affecting the layout of the entire memory cell array. Therefore, the storage node of the SRAM cell can be stably loaded with a capacity.

[Example of change]
FIG. 13 schematically shows a cross-sectional structure of a flash memory cell in a modification of the semiconductor integrated circuit device according to the first embodiment of the present invention. In FIG. 13, a flash memory cell includes impurity regions 82a and 82b formed on the surface of substrate region 80, and a floating gate electrode formed on the surface of substrate region 80 between impurity regions 82a and 82b. 84 and a control gate electrode 86 formed on the floating gate electrode 84 through an interlayer insulating film.

  Impurity region 82a is connected to bit line BL, and impurity region 82b is coupled to source line SL. The control gate electrode 86 is connected to the control gate line CG. The floating gate electrode 84 is arranged separately for each flash memory cell and is in an electrically floating state.

  The flash memory cell shown in FIG. 13 is formed of a floating gate type transistor. The threshold voltage of the memory transistor varies depending on the amount of charges (electrons) accumulated in the floating gate electrode 84, and data is stored according to the threshold voltage information.

  In the flash memory cell shown in FIG. 13, at the time of data writing, bit line BL is set to a high voltage level, and control gate line CG is also set to a positive write high voltage level. Source line SL is set to the ground voltage level. In this case, a current flows from the bit line BL to the source line SL, and channel hot electrons (CHE) are generated by a high electric field between the impurity region 82a and the control gate electrode 86. The channel hot electrons are injected into the floating gate electrode 84. As a result, the threshold voltage of the memory transistor rises.

  At the time of erasing, as an example, bit line BL is set in a floating state, source line SL is set at a positive voltage level, and control gate line CG is set at a negative voltage level. In this case, a Fowler-Nordheim tunnel current (FN tunnel current) flows between the floating gate electrode 84 and the impurity region 82b, electrons flow out of the floating gate electrode 84, and the threshold voltage of the memory transistor is low. Shift to. At the time of erasing, the bit line BL and the source line SL may be in a floating state, and electrons may be extracted from the floating gate to the substrate region 80.

  At the time of data reading, a read voltage between the threshold voltages of the write state and erase state is applied to control gate line CG, a positive read voltage is supplied to bit line BL, and source line SL is connected to ground voltage. Set to level. In the high threshold voltage state (write state), the amount of current flowing from the bit line BL to the source line SL is small. On the other hand, in the low threshold voltage state (erase state), the bit line BL to the source line SL. A large current flows through. Data is read by detecting the current flowing through bit line BL.

  Similarly, when a memory cell transistor having a stacked gate structure of floating gates and control gates is used as a flash memory cell, the capacity of the storage node of the SRAM cell can be increased.

  FIG. 14 schematically shows an electrically equivalent circuit of the SRAM cell according to the modification of the first embodiment of the present invention. 14, the SRAM cell includes two P-channel MOS transistors PQ1 and PQ2 and four N-channel MOS transistors NQ1-NQ4, similar to the SRAM cell shown in FIG. The arrangement of the SRAM cell transistors shown in FIG. 14 is the same as the arrangement of the SRAM cell transistors shown in FIG. 3. Access transistors NQ3 and NQ4 are turned on according to the signal potential of word line WL, and bit lines BL and / BL Are coupled to storage nodes ND1 and ND2, respectively, and complementary data is held in storage nodes ND1 and ND2.

  Conductive line 90 is arranged for this SRAM cell. The gate electrodes of transistors PQ1 and PQ2 and NQ1-NQ4 of this SRAM cell are formed in the same wiring process as control gate electrode 86 of the flash memory cell shown in FIG. On the other hand, the conductive line 90 is composed of a wiring in the same wiring layer as the floating gate electrode 84 (FG) of the flash memory cell shown in FIG. The control gate electrode 86 is an upper layer wiring than the floating gate electrode 84, and its electrical characteristics are superior to those of the floating gate, thereby speeding up the access operation of the SRAM cell.

  The wiring layout of the SRAM cell shown in FIG. 14 is the same as the wiring layout shown in FIG. 4 except that conductive lines 90 of the same wiring layer as the floating gate electrode layer are provided in place of conductive lines 26a and 26b.

  FIG. 15 schematically shows a planar layout of the first metal wiring from the active region of the SRAM cell according to the modification of the first embodiment of the invention. The SRAM cell shown in FIG. 15 is the same as the planar layout of the SRAM cell shown in FIG. That is, active regions 20a-20d are arranged in the same manner as the arrangement shown in FIG. 4, and first metal wirings 22a-22j are arranged correspondingly. Contacts 22a to 23g are arranged corresponding to the respective active regions and gate electrode wirings to electrically connect the active region and the first metal wiring or the gate electrode wiring and the first metal wiring. The arrangement of the contacts and the first metal wiring is the same as that of the SRAM cell shown in FIG. Accordingly, the same reference numerals are assigned to corresponding parts, and detailed description thereof is omitted.

  Conductive wirings 92a and 92b are the boundary region between the N well where P channel MOS transistors PQ1 and PQ2 are formed, the P well where N channel MOS transistors NQ1 and NQ3 are formed, and the P well where MOS transistors NQ4 and NQ2 are formed. Placed in. Conductive wirings 92a and 92b are composed of wirings in the same wiring layer as floating gate electrode 84 (FG) of the floating flash memory cell shown in FIG.

  On the other hand, the gate electrode wirings 94a-94d corresponding to the gate electrode wirings 21a-21d shown in FIG. 4 are formed of wirings in the same wiring layer as the control gate electrode 86 (CG) of the floating gate type flash memory cell shown in FIG. The Therefore, in this arrangement, gate electrode lines 94a and 94c are arranged above conductive lines 92a and 92b. The layout of the SRAM cell shown in FIG. 15 is the same as the layout shown in FIG. 4 except for the wiring layer where the wiring is arranged.

  FIG. 16 schematically shows a cross-sectional structure of conductive line 92a and gate electrode wiring 92a along line L16-L16 shown in FIG. In FIG. 16, an element isolation region 102 is formed on a substrate region (well region) 100, and a conductive wiring 92a having the same wiring layer as the floating gate electrode (FG) is disposed on the element isolation region 102. The substrate region 100 is a well in which an element isolation film is shallowly formed on the surface thereof. A gate electrode wiring 94a is disposed on the conductive wiring 92a with a gate insulating film 104 interposed therebetween. The gate electrode wiring 94a is a wiring in the same wiring layer as the control gate electrode wiring (CG) of the flash memory cell.

  Therefore, the conductive wiring 92 a is formed on the underlying element isolation film (shallow trench isolation film: STI film) 102, and the gate electrode wiring 94 a is disposed thereon via the gate insulating film 104. It becomes composition. Even if the gate electrode wiring 94a is disposed on the conductive wiring 92a via the gate insulating film 104, the active region is not formed in this region, so that the threshold voltage of the SRAM cell transistor is not affected. Absent. It suffices that the gate electrode wiring is disposed on the active region via the gate insulating film.

  FIG. 17 schematically shows a sectional structure taken along line L17-L17 shown in FIG. In FIG. 17, conductive wiring 92a of the same wiring layer as this floating gate electrode is arranged. A gate insulating film 104 is formed so as to cover the conductive wiring 92 a, and a gate electrode wiring 94 a is disposed on the gate insulating film 104.

  When a flash memory cell having a floating gate structure is used, the floating gate electrode (FG) is a lower layer wiring than the control gate electrode (CG). In the SRAM cell, the gate electrode wiring of the MOS transistor is used as the control gate of the flash memory cell. When the wiring of the same wiring layer as the electrode is used, a step is generated in the gate electrode wiring 94a on the element isolation region. However, this region is separated from the active region, and due to the gate insulating film 104 under the gate electrode wiring 94a, the distance between the active region surface and the gate electrode wiring 94a is set to a thickness defined by the gate insulating film 104. Therefore, deterioration of transistor characteristics such as threshold voltage can be suppressed.

  The region where conductive wirings 92a and 92b are disposed is a well boundary region, and is a region where transistors and wirings are not disposed. The layout of the upper layer wiring is shown in FIGS. 7 to 10 of the first embodiment. It is the same as the flat layout. Even if a step is generated in this region, no adverse effect is exerted on the transistor characteristics and the arrangement of the wiring (the same level as the case where the gate electrode wiring and the conductive wirings 26a and 26b are used). Further, when the STI film is used as the element isolation film and the surface of the STI film is flattened, the gate electrode wiring can be arranged at the same level as the LOCOS film (thermal oxide film). The same applies to a cell structure using an ONO film as a charge storage film as a flash memory cell.

  By using the wiring of the same wiring layer as the control gate (85) of the floating gate type flash memory cell as the gate electrode wiring of the SRAM cell and the transistor, the wiring with excellent film quality (excellent electrical characteristics) is gated. It can be used as an electrode, the gate potential of the transistor can be changed at high speed, and the SRAM cell transistor can be operated at high speed.

  As described above, according to the first embodiment of the present invention, in the SRAM cell column, the conductive lines are arranged so as to intersect the gate electrode wiring of the transistor by using the same layer wiring as the intrinsic electrode wiring of the flash memory cell. The capacity is added to the storage node. The conductive lines simply extend continuously in the column direction, and there is no need to provide extra contacts in the SRAM cell, thereby avoiding an increase in the layout area of the SRAM cell and an increase in the number of individual manufacturing steps. A capacity can be added to the memory cell to reliably improve the data retention characteristics of the SRAM cell. Further, the conductive lines are simply arranged in a straight line, and it is not necessary to establish a connection between the capacitor and the gate of the SRAM cell transistor or the active region inside the SRAM cell, thereby simplifying the wiring layout. The

[Embodiment 2]
FIG. 18 schematically shows a whole structure of the semiconductor integrated circuit device according to the second embodiment of the present invention. In FIG. 18, the semiconductor integrated circuit device 200 includes a logic circuit 202 and a flash memory 204. Logic circuit 202 and flash memory 204 are interconnected via an internal bus 206. The logic circuit 202 may be a processor that executes a program, a general-purpose DSP (digital signal processor), or a controller. In the logic circuit 202, a latch circuit 208 is provided inside. The latch circuit 208 holds signals / data. The latch circuit 208 may be used as a gate for transferring data, or may be used as a register for temporarily storing processing data. The latch circuit 208 only needs to have a function of holding data / signals.

  The flash memory 204 only needs to have flash memory cells that store data in a nonvolatile manner, and the flash memory cells may have either the cell structure shown in FIG. 2 or the cell structure shown in FIG. .

  FIG. 19 schematically shows an example of the configuration of one latch included in latch circuit 208 shown in FIG. 19, the latch included in latch circuit 208 includes an inverter 209 that inverts clock signal CLK, transmission gates 210 and 211 that are selectively turned on in accordance with clock signal CLK and the inverted clock signal from inverter 209, and transmission gate 210. Inverters 214 and 216 connected in cascade to receive a signal transmitted from the inverter 214 to the internal wiring 212 and an inverter 219 for inverting the signal transmitted from the inverter 214 to the internal wiring 217 are included.

  Transmission gate 210 conducts when clock signal CLK is at H level, and transmits input data DIN to internal wiring 212. Inverter 214 includes a P-channel MOS transistor PT1 and an N-channel MOS transistor NT1, inverts the signal / data on internal wiring 212 and transmits the inverted signal / data to internal wiring 217. Inverter 216 includes a P-channel MOS transistor PT2 and an N-channel MOS transistor NT2, and inverts a signal / data on internal wiring 217 to generate an output signal / data (hereinafter simply referred to as data) DOUT.

  Inverter 219 inverts data transmitted from internal wiring 217 via internal wiring 218. Transmission gate 211 conducts complementarily with transmission gate 210, and transmits the output data of inverter 219 to internal wiring 212 when conducting.

  A capacitor C is added to the internal wiring 218 using the conductive line 220. Conductive line 220 is formed using a wiring in the same wiring layer as memory gate line MG or floating gate FG included in flash memory 204, and is coupled to a ground node as an example. Therefore, by increasing the capacity of the internal wirings 217 and 218 by this capacity C, data inversion / noise on the internal wiring 217 can be prevented, and data can be held stably.

  In the latch shown in FIG. 19 as well, the conductive line 220 is formed by using a unique wiring used for the flash memory cell during the manufacturing process of the flash memory cell, which has no adverse effect on the arrangement of the components of the latch circuit. The conductive wire 220 can be arranged without affecting. “Unique wiring” refers to wiring in a wiring layer that is used in a flash memory cell and not used in a latch. This rule is the same in the first embodiment.

  FIG. 20 schematically shows a planar layout of inverters 214 and 216 shown in FIG. In FIG. 20, gate electrode wirings 230a and 230b are arranged to extend in the Y direction with a gap therebetween. In FIG. 20, an active region where a transistor is formed is not shown.

  A first metal wiring 236a is arranged at the center of gate electrode wiring 230a. The first metal wiring 236a is electrically connected to the gate electrode wiring 230a at the protruding portion. First metal interconnection 236b is arranged to meander between gate electrode interconnections 230a and between gate electrode interconnections 230a and 230b. First metal interconnection 236b is coupled to the drain node (drain impurity region) of P-channel MOS transistor PT1 through contact CT2 in the upper portion, and is electrically connected to gate electrode interconnection 230b through contact CT3 in the central portion. Further, at the lower part, it is connected to the drain node (drain impurity region) of N channel MOS transistor NT1 through contact CT4.

  A first metal wiring 236c is arranged adjacent to the gate electrode wiring 230b so as to extend substantially linearly in the Y direction. First metal interconnection 236c forms the output node of inverter 216, is connected to the drain node (drain impurity region) of P-channel MOS transistor PT2 via contact CT5, and is connected to the drain of N-channel MOS transistor NT2 via contact CT6. Connected to node (drain impurity region).

  T-shaped first metal wirings 233 and 234 having protrusions arranged between gate electrode wirings 230a and 230b face each other and are arranged outside first metal wiring 236b. The first metal wiring 233 has a protruding portion 233a and a top portion 233b. The top portion 233b transmits the power supply voltage VDD. The top portion 233b may be coupled to a power supply line (not shown) through a via, or may constitute the power supply line itself. Protrusion 233a is coupled to the source node (source impurity region) of MOS transistors PT1 and PT2 through contact CT7, and supplies power supply voltage VDD of top 233b to the source node.

  First metal interconnection 234 has a protruding portion 234a and a bottom portion 234b. The protruding portion 234a is coupled to the source node (source impurity region) of N channel MOS transistors NT1 and NT2 via contact CT8 and transmitted from bottom portion 234b. The ground voltage VSS is supplied to the source node. The bottom portion 234b may be coupled to a ground line (not shown) through a via, or may constitute the ground line itself.

  In FIG. 20, a region 240 of the first metal wiring 236b and the gate electrode wiring 230b surrounded by a broken line corresponds to a storage node constituted by the internal wirings 217 and 218 shown in FIG. For storage node 240, a capacitor C is arranged in region SC shown in FIG.

  Note that FIG. 20 does not show a wiring for feeding back data from the first metal wiring 236b to the inverter 219, but this feedback wiring is formed by using, for example, the second metal wiring in the upper layer.

  FIG. 21 schematically shows a planar layout of the latch according to the second embodiment of the present invention together with additional capacitor C. In FIG. The planar layout of the latch shown in FIG. 21 shows an arrangement of portions including inverters 214 and 216 and conductive line 220 shown in FIG. The planar layout shown in FIG. 21 is different from the planar layout shown in FIG. 24 in the following points. That is, the gate electrode wiring 230b is disposed beyond the bottom 234b of the first metal wiring 234 that supplies the ground voltage VSS. A conductive line 220 is disposed below the bottom 234 b of the first metal wiring 234.

  This conductive line 220 is a wiring in the same wiring layer as a wiring unique to the flash memory cell, that is, a wiring in a wiring layer that is not used in the transistors PT1, PT2, NT1 and NT2 of the flash memory cell transistor. Alternatively, the wiring is in the same wiring layer as the memory gate electrode. The conductive line 220 is simply disposed below the first metal wiring 234 so as to intersect the gate electrode wiring 230b. Therefore, conductive line 220 may be disposed in a region that does not affect the layout of the wiring and active region in which transistors PT1, PT2, NT1, and NT2 constituting inverters 214 and 216 are disposed.

  As apparent from the comparison of the wiring layouts of FIGS. 20 and 21, at the storage node 240, the capacitor C can be arranged without affecting the layout of the transistors of the inverters 214 and 216. The 240 load capacity can be increased.

  In the arrangement shown in FIG. 21, in a region (not shown), the upper metal wiring that supplies the ground voltage VSS to the first metal wiring 234 or the bottom 234b of the first metal wiring 234 and the conductive line 220 are connected via vias. What is necessary is just to be electrically connected.

  The conductive line 220 may be disposed so as to intersect the gate electrode 230b on the high-side power supply line (first metal wiring 233) side, and may be fixed to the power supply voltage VDD.

  In the above description, the latch circuit 208 is shown to be included in the logic circuit (202) integrated on the same semiconductor substrate as the flash memory. However, for example, a register circuit for latching write data is provided in the flash memory, and the wiring of the same wiring layer as the electrode wiring of the flash memory cell is used as an additional capacitor for the storage node of the latch of the register circuit. May be.

  As described above, according to the second embodiment of the present invention, the capacity of the storage node of the latch is set at the intersection with the gate electrode wiring of the latch transistor using the intrinsic electrode wiring of the transistor of the flash memory cell. Has also formed. Therefore, there is no need to provide a contact between the active region of the latching transistor or the internal node, and the capacity of the storage node can be increased without increasing the layout area of the latch and the number of manufacturing steps. Data can be retained.

  The semiconductor integrated circuit device according to the present invention may be any device as long as the flash memory and the data holding circuit are integrated on the same semiconductor chip (substrate). In particular, by using it in a processor such as a flash-equipped microcomputer (flash microcomputer), it is possible to stably hold data stored in the SRAM without increasing the layout chip area.

  Further, by applying the present invention to a semiconductor integrated circuit device having a latch circuit formed on the same semiconductor chip as the flash memory cell, the storage node (latch node) can be stored without increasing the layout area of the latch. Capacitance can be increased and data retention characteristics can be improved without increasing the size of the latch.

1 schematically shows an entire configuration of a semiconductor integrated circuit device according to a first embodiment of the invention. FIG. FIG. 3 is a diagram schematically showing a cross-sectional structure of a memory cell of the flash memory shown in FIG. 2. FIG. 2 schematically shows an electrical equivalent circuit of the memory cell of the static RAM shown in FIG. 1. FIG. 4 schematically shows a planar layout of the SRAM cell shown in FIG. 3. FIG. 5 is a diagram schematically showing a layout of upper layer wiring in the planar layout shown in FIG. 4. FIG. 5 is a diagram schematically showing a cross-sectional structure of a crossing portion of a conductive line and a gate electrode wiring shown in FIG. 4. FIG. 6 schematically shows a planar layout of the SRAM cell array according to the first embodiment of the present invention up to a first metal wiring layer. It is a figure which shows the layout of the 2nd metal wiring of the SRAM cell array according to Embodiment 1 of this invention with the layout of an active region and a gate electrode wiring. It is a figure which shows the layout of the 3rd metal interconnection of the SRAM cell array according to Embodiment 1 of this invention with the layout of a lower active region, a gate electrode interconnection, and a conductive line. It is a figure which shows the layout of the 4th metal wiring of the SRAM cell array according to Embodiment 1 of this invention with the lower active region, the gate electrode wiring, and the via | veer. It is a figure which shows roughly arrangement | positioning of the voltage application part of the conductive line of SRAM according to Embodiment 1 of this invention. It is a figure which shows roughly arrangement | positioning of the modified example of the voltage fixation of the conductive line of SRAM according to Embodiment 1 of this invention. It is a figure which shows roughly the cross-section of the flash memory cell of the modification of Embodiment 1 of this invention. It is a figure which shows roughly the electrical equivalent circuit of the SRAM cell of the modification of Embodiment 1 of this invention. FIG. 15 is a diagram schematically showing a planar layout of the SRAM cell shown in FIG. 14 up to a first metal wiring. FIG. 16 schematically shows a cross-sectional structure taken along line L16-L16 shown in FIG. FIG. 16 schematically shows a cross-sectional structure taken along line L17-L17 shown in FIG. It is a figure which shows roughly the whole structure of the semiconductor integrated circuit device according to Embodiment 2 of this invention. FIG. 19 is a diagram illustrating an example of a configuration of a latch of the latch circuit illustrated in FIG. 18. FIG. 20 schematically shows a planar layout of the two-stage inverter shown in FIG. 19. FIG. 20 is a diagram schematically showing a planar layout of a two-stage inverter and conductive lines (load capacitance) shown in FIG. 19.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device, 2 Processor, 6 Static RAM (SRAM), 94 Control gate electrode line, 18 Memory gate electrode wiring, PQ1, PQ2 P channel MOS transistor (load transistor), NQ1, NQ2 N channel MOS transistor (driver transistor) ), NQ3, NQ4 N channel MOS transistor (access transistor), 19 conductive lines, 20a-20d active region, 21a-21d gate electrode wiring, 26a, 26b conductive wiring, 44 control gate electrode wiring, 48 memory gate electrode wiring, MC MC0-MC5 memory cell, 50a, 50b memory sub-array, 52 tap region, 54, 56 impurity region, 60a, 60b, 64, 65, 61 first metal wiring, 62, 66 contour 63, 72a, 72b via, NW N well, PWa, PWb P well, 70 first metal wiring, 72a, 72b contact, 92a, 92b conductive line, 94a-94d gate electrode wiring, 200 semiconductor integrated circuit device, 202 Logic circuit, 204 flash memory, 208 latch circuit, 214, 216 inverter, 217, 218 internal wiring (storage node), 220 conductive line, 230a, 230b gate electrode wiring, 240 storage node.

Claims (7)

A semiconductor integrated circuit including a semiconductor memory device integrated on the same semiconductor substrate as a nonvolatile memory, the semiconductor memory device comprising:
A plurality of memory cells arranged in a matrix, each having a plurality of memory cells holding data in the first and second storage nodes, each of the memory cells holding a plurality of data in the first and second storage nodes The plurality of field effect transistors are arranged with their gate electrodes aligned in a first direction, and are connected to one of the first and second storage nodes. Combined,
A plurality of word lines arranged corresponding to each memory cell row, each of which is connected to a memory cell in a corresponding row;
A plurality of bit line pairs arranged corresponding to each memory cell column and connected to the memory cells in the corresponding column, and a memory cell aligned in a direction crossing the first direction. Each of the plurality of field-effect transistors of the corresponding memory cell, the plurality of conductive lines arranged to intersect with the gate electrodes of the plurality of field-effect transistors of the corresponding memory cell, A semiconductor integrated circuit device comprising wirings of the same wiring layer, wherein the unique wiring is wiring of a wiring layer that is not used for forming a memory cell of the semiconductor memory device.   The semiconductor integrated circuit device according to claim 1, wherein the conductive line is coupled to a node that supplies a fixed voltage. The non-volatile memory includes a non-volatile memory cell having a memory transistor that stores data according to a charge amount accumulated in a charge accumulation layer, and a selection transistor that selects the memory transistor,
The semiconductor integrated circuit device according to claim 1, wherein the conductive line is configured by a wiring in the same wiring layer as a gate electrode wiring of a memory transistor of the nonvolatile memory cell. The non-volatile memory includes a non-volatile memory cell having a floating gate transistor that stores data according to the amount of charge accumulated in a charge accumulation gate in a floating state,
The semiconductor integrated circuit device according to claim 1, wherein the conductive line is configured by a wiring in the same wiring layer as a charge storage gate of the nonvolatile memory cell. A plurality of memory cells of the semiconductor memory device are formed on a substrate region,
The semiconductor integrated circuit device further includes a power line for supplying a bias voltage to the semiconductor substrate region in the tap region and supplying a cell power voltage to the plurality of memory cells,
The semiconductor integrated circuit device according to claim 1, wherein the conductive line is coupled to the power supply line in the tap region. In each memory cell of the semiconductor memory device, the plurality of field effect transistors are a second conductivity type transistor formed in a first conductivity type substrate region and a first conductivity type formed in the second conductivity type substrate region. A conductive type transistor,
The semiconductor integrated circuit device according to claim 1, wherein the conductive line is arranged corresponding to a boundary region between the substrate regions of the first and second conductivity types.   In a semiconductor integrated circuit device in which a non-volatile memory and a data holding unit are integrated on the same semiconductor substrate, the non-volatile memory of the non-volatile memory crosses a gate electrode of a transistor coupled to a data holding node of the data holding unit. The wiring of the same wiring layer as the wiring of the memory cell is arranged, and the wiring of the wiring layer other than the wiring layer used for forming and arranging the transistor of the data holding unit is arranged. A semiconductor integrated circuit device which is a wiring.

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