JP2019133737A - Dual-port sram - Google Patents

Abstract

To provide a dual-port SRAM capable of increasing a write margin and suppressing an increase in area.SOLUTION: A dual-port SRAM includes: a memory cell; a metal wiring layer provided on an upper layer of the memory cell; first wiring that is disposed along a first direction in the metal wiring layer and supplies a first voltage to the memory cell; second wiring that is disposed along the first direction in the metal wiring layer and supplies a second voltage different from the first voltage to the memory cell; and first signal wiring that is disposed along the first direction in the metal wiring layer. In plan view, the second signal wiring is disposed between the second wiring and third wiring.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a semiconductor memory device, and more particularly to an SRAM (Static Random Access Memory).

  Miniaturization of transistor elements is advanced for high integration. With this miniaturization, the manufacturing variation increases and the transistor element characteristics also increase. In addition, with miniaturization, lowering of voltage is also progressing to ensure reliability and reduce power consumption. This causes a problem that the write margin of the SRAM is lowered.

  In order to solve this problem, there is a method of preventing a defective writing operation by setting the bit line to a negative voltage during writing and improving the current driving capability of the access MOS transistor of the memory cell (Patent Documents 1 and 2). Patent Documents 1 and 2).

  Japanese Patent Application Laid-Open No. 2004-228561 discloses a system in which a boost circuit including a boost capacitor and an inverter that drives the boost capacitor is provided for each bit line pair, and the bit line side boost circuit to be grounded is selected and driven.

  In Patent Document 2, one boost circuit including a boost capacitor and an inverter that drives the boost capacitor is provided, and is connected to each bit line pair via a switch. A system for selecting a switch on the bit line side driven to a ground potential and transmitting a negative voltage is shown.

  In Non-Patent Document 1, an inverter is provided for each bit line pair as a write drive circuit. The sources of these two write inverters are short-circuited and connected to the low voltage side power source VSS via the power switch. The boost capacitor is connected to the source of this shorted write inverter. When the power switch is turned off, only the output node of the inverter that outputs the ground voltage becomes floating. A system is shown in which the negative voltage due to boost is transmitted to the bit line via the NMOS and Y switch of the write inverter that outputs the ground voltage.

  Non-Patent Document 2 shows a method of driving a bit line to a ground voltage after driving the bit line to a ground voltage according to write data, and then boosting the bit line to a negative voltage via a boost capacitor. .

JP 2002-298586 A JP 2009-295246 A

J. Chang, et al, “A 20nm 112Mb SRAM Design in High K / Metal Gate Technology with Assist Circuitry for Low Leakage and Low Vmin Applications,” ISSCC’13 D.P. Wang, et al, “A 45nm Dual-Port SRAM with Write and Read Capability Enhancement at Low Voltage,” SOC Conference, 2007 IEEE International

  On the other hand, when there are IPs with different bit line lengths, such as a compiled memory, the bit line capacitance changes depending on the length of the bit line, so it is necessary to individually form a boost capacitor corresponding to the bit line length and increase the chip area. May be incurred.

  In order to solve the above problems, a semiconductor memory device capable of increasing a write margin and suppressing an increase in area is provided.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the dual port SRAM includes a memory cell, a metal wiring layer provided in an upper layer of the memory cell, a first wiring in the metal wiring layer, and a first voltage applied to the memory cell. A first wiring that supplies a second voltage different from the first voltage to the memory cell, and a first direction in the metal wiring layer. And a first signal wiring arranged along the line. In plan view, the second signal wiring is disposed between the second wiring and the third wiring.

  According to one embodiment, it is possible to increase the write margin and suppress the increase in area by the above configuration.

1 is a diagram for explaining the outline of the overall configuration of a semiconductor memory device according to Embodiment 1. FIG. It is a figure explaining the structure of the memory cell MC. FIG. 6 is a diagram for explaining a configuration of a first write drive circuit 6A and a first bit line pair charging circuit 7A based on the first embodiment. It is a figure explaining the structure of the 1st and 2nd write auxiliary circuits 5A and 5B according to this Embodiment 1. FIG. It is a figure explaining the signal waveform of the write-in operation based on this Embodiment 1. FIG. It is a figure explaining arrangement | positioning of the signal wiring according to Embodiment 1. FIG. It is a figure explaining the structure of the signal wiring according to this Embodiment 1. FIG. It is a figure explaining the arrangement | positioning of another signal wiring according to this Embodiment 1. FIG. It is a figure explaining arrangement | positioning of another signal wiring according to this Embodiment 1. FIG. It is a figure explaining the structure of 1st and 2nd write assist circuit 5A # according to the modification of this Embodiment 1, and 5B #. It is a figure explaining the structure of the 1st and 2nd write auxiliary circuits 5A and 5B according to this Embodiment 2. FIG. It is a figure explaining the structure of 1st and 2nd write assist circuit 5AP and 5BP according to this Embodiment 3. FIG. It is a figure explaining the signal waveform of the write-in operation based on this Embodiment 3. FIG.

  This embodiment will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
<Overall configuration of semiconductor memory device>
FIG. 1 is a diagram for explaining the outline of the overall configuration of the semiconductor memory device according to the first embodiment.

  As shown in FIG. 1, the semiconductor memory device includes a memory cell array 1 having a plurality of memory cells MC arranged in a matrix. Memory cell array 1 includes a plurality of word lines provided corresponding to memory cell rows and a plurality of bit line pairs provided corresponding to memory cell columns, respectively. Here, the memory cell MC includes the first word line WLA and the corresponding first bit line pair BLA, / BLA, the second word line WLB and the corresponding second bit line pair BLB, / BLB. Is a so-called dual port cell.

  The semiconductor memory device includes a first row selection drive circuit 2A that selects the first word line WLA, and a first column selection circuit 3A that generates a column selection signal for selecting the first column of the memory cell array 1. Have. The semiconductor memory device also includes a first input circuit 4A that inputs the first write data DA, and the first column selection circuit 3A that receives the first write data DA transmitted from the first input circuit 4A. And a first write drive circuit 6A for transmitting to the first bit line pair BLA, / BLA selected by. The semiconductor memory device also includes a first write assist circuit 5A, a first bit line pair charging circuit 7A that charges the first bit line pair BLA, / BLA, and a first control circuit 8A. .

  The semiconductor memory device includes a second row selection drive circuit 2B that selects the second word line WLB, a second row selection drive circuit 2B that selects the second word line WLB, and a second row of the memory cell array 1. And a second column selection circuit 3B that generates a column selection signal for selecting a column. The semiconductor memory device also includes a second write drive circuit 6B for transmitting the second write data DB to the second bit line pair BLB, / BLB selected by the second column selection circuit 3B, 2 write auxiliary circuits 5B, a second bit line pair charging circuit 7B for charging the second bit line pair BLB, / BLB, and a second control circuit 8B.

  First row selection drive circuit 2A drives word line WLA corresponding to the first row designated according to internal row address RAA from first control circuit 8A to a selected state.

  The first column selection circuit 3A generates a column selection signal for designating the first column of the memory cell array 1 according to the internal column address signal CAA from the first control circuit 8A.

  The first write data DA input to the first input circuit 4A is transmitted to the first write drive circuit 6A as a complementary pair of data.

  The first write drive circuit 6A transmits data to the first bit line pair BLA, / BLA selected by the first column selection circuit 3A according to the pair of data, and the first row selection drive circuit 2A. Data is written into the memory cell MC connected to the first word line WLA selected by the above.

  After completion of data writing to memory cell MC, first bit line pair charging circuit 7A charges first bit line pair BLA, / BLA to a predetermined voltage level.

  Second row selection drive circuit 2B, second column selection circuit 3B, second input circuit 4B, and second write drive circuit 6B for second word line WLB and second bit line pair BLB, / BLB The operations of the second write assist circuit 5B, the second bit line pair charging circuit 7B, and the second control circuit 8B are the same as described above, and thus detailed description thereof is omitted.

<Configuration of memory cell MC>
FIG. 2 is a diagram illustrating the configuration of the memory cell MC.

  As shown in FIG. 2, memory cell MC includes first and second CMOS inverters. The first CMOS inverter includes a P-channel load MOS (field effect type) transistor PQ1 and an N-channel driver MOS transistor NQ1 connected between the voltage VDD and the voltage VSS. The second CMOS inverter includes a P-channel load MOS transistor PQ2 and an N-channel driver MOS transistor NQ2 connected between the voltage VDD and the voltage VSS. The voltage VSS is a voltage lower than the voltage VDD.

  The output node of the first CMOS inverter is connected to the input node of the second COS inverter, and the output node of the second CMOS inverter is connected to the input node of the first CMOS inverter. A so-called inverter latch is formed. Therefore, complementary data is held in storage nodes MN and / MN which are output nodes of the inverter latch.

  The memory cell MC includes N-channel access MOS transistors NQ3 and NQ4 that are electrically connected to the storage nodes MN and / MN and the first bit line pair BLA and / BLA, and the storage nodes MN and / MN and the second bit line pair BLB. , / BLB and N channel access MOS transistors NQ5, NQ6.

  Access MOS transistors NQ3 and NQ4 have their gates connected to first word line WLA. Access MOS transistors NQ5 and NQ6 have their gates connected to second word line WLB. Each operates selectively.

The memory cell MC is a dual port 8-transistor SRAM cell.
A normal write operation of the memory cell MC of the dual port SRAM will be described.

  As an example, assume that the storage nodes MN and / MN hold “H” level and “L” level potentials, respectively. A case where the potentials of the storage nodes MN and / MN are inverted using the first word line WLA and the first bit line pair BLA and / BLA will be described.

Note that the second word line WLB is not selected (“L” level).
Here, potentials of “L” level and “H” level are applied to the first bit line pair BLA, / BLA, respectively.

Next, the first word line WLA is set to the “H” level.
Accordingly, the “L” level potential of first bit line pair BLA is transmitted to storage node MN through access MOS transistor NQ3. Then, it is inverted by the second CMOS inverter, and the storage node / MN becomes “H” level.

  On the other hand, the memory cell MC of the dual port SRAM has a characteristic state called disturb write. Specifically, the second word line WLB is in the “H” level potential during the write operation.

  It is assumed that second bit line pair BLB, / BLB is at the “H” level precharge level. This state occurs when writing / reading data to / from another memory cell sharing the second word line WLB.

  At this time, since access MOS transistors NQ3 and NQ5 are both conductive, storage node MN is not completely at the ground potential.

  When the threshold voltage of access MOS transistor NQ5 decreases, the potential of storage node MN further increases. Further, when the absolute value of the threshold voltage of load MOS transistor PQ2 increases, the ability to raise the potential of storage node / MN decreases, and the write operation is delayed.

  Therefore, the first and second write assist circuits 5A and 5B shown in FIG. 1 are provided in order to perform writing at high speed and surely even with miniaturization and a low power supply voltage associated therewith.

  In the normal write operation and disturb write, the case where writing is performed using the first word line WLA and the first bit line pair BLA, / BLA has been described as an example. The same applies to the case where the line WLB and the second bit line pair BLB, / BLB are used.

  The same applies to the case where the storage node / MN is pulled out from the “H” level to the “L” level.

  In the following description, the first word line WLA, the first bit line pair BLA, / BLA, the first input circuit 4A, the first write assist circuit 5A, the first write drive circuit 6A, the first The operation of inverting the storage node MN of the memory cell MC from the “H” level to the “L” level using the bit line pair charging circuit 7A will be described as an example, but the second word line WLB, the second bit line pair The same applies to the case where BLB, / BLB, second input circuit 4B, second write assist circuit, second write drive circuit 6B, and second bit line pair charging circuit 7B are used. The same applies when the storage node / MN of the MC is inverted from the “H” level to the “L” level.

<Configuration of other peripheral circuits>
FIG. 3 is a diagram illustrating the configuration of first write drive circuit 6A and first bit line pair charging circuit 7A based on the first embodiment.

  As shown in FIG. 3, a part of the memory cell MC, the first bit line pair charging circuit 7A, the first write driving circuit 6A, and the first write auxiliary circuit 5A is shown. .

  The first bit line pair charging circuit 7A pulls up the first bit line pair BLA, / BLA, a P channel equalize MOS transistor PQ3, and the first bit line pair BLA, / BLB to the voltage VDD. P channel MOS transistors PQ4 and PQ5 are included. The first bit line pair charging circuit 7A includes N-channel transfer MOS transistors NQ7, NQ7 that connect the first bit line pair BLA, / BLA to the output nodes CW, / CW of the first write drive circuit 6A. NQ8.

  Here, parasitic capacitances (grounding capacitances) attached to the first bit line pair BLA, / BLA are shown as Cg3T and Cg3B.

  The gates of the equalize MOS transistor PQ3, the pull-up MOS transistors PQ4 and PQ5, and the transfer MOS transistors NQ7 and NQ8 are connected to the first column selection signal YSA.

  First write drive circuit 6A is formed of a first write inverter formed of P channel MOS transistor PQ6 and N channel MOS transistor NQ9, and P channel MOS transistor PQ7 and N channel MOS transistor NQ10. And a second write inverter.

  Source nodes WBSA of the first and second write inverters are short-circuited and connected to first write auxiliary circuit 5A.

  Here, parasitic capacitances (grounding capacitances) attached to output nodes CW and / CW of the first and second write inverters are indicated as Cg2T and Cg2B.

  First write assist circuit 5A has an N-channel MOS transistor NQ11A connected between source node WBSA and voltage VSS. Details of the first write assist circuit 5A will be described later.

  The configurations of the second bit line pair charging circuit 7B, the second write drive circuit 6B, and the like are the same as the configurations of the first bit line pair charging circuit 7A and the first write drive circuit 6A. The detailed description will not be repeated.

Next, the configuration of the first write assist circuit 5A will be described.
FIG. 4 is a diagram illustrating the configuration of first and second write assist circuits 5A and 5B according to the first embodiment.

  As shown in FIG. 4, first write assist circuit 5A includes an N-channel MOS transistor NQ11A that connects source node WBSA of first and second write inverters to voltage VSS, inverter INV1A, and buffer BUF1A. And a first signal line ML11A and a second signal line ML12A. In this example, the first write assist circuit 5A is provided corresponding to each memory cell column.

  In this example, the boost capacitance element Cb13A of the first write assist circuit 5A is formed based on the coupling capacitance between the wirings between the first signal wiring ML11A and the second signal wiring ML12A.

  Further, the ground capacitive element Cg13A is formed based on the coupling capacitance between the second signal wiring ML12A and the power supply wiring of the voltage VSS.

The first inverter INV1A receives the input of the first boost signal BSTA.
The first boost signal BSTA is output from the first control circuit 8A.

  Output node / BSTA of first inverter INV1A is connected to the gate of N-channel MOS transistor NQ11A.

  Output node / BSTA is connected to the input of buffer BF1A, and buffer BF1A drives first signal line ML11A connected to output node NBSTA in accordance with output node / BSTA.

FIG. 5 is a diagram for explaining signal waveforms in the write operation based on the first embodiment.
As shown in FIG. 5, when the storage nodes MN and / MN are at the “H” level and the “L” level, the first word line WLA and the first bit line pair BLA and / BLA are used for storage. A case where the nodes MN and / MN are inverted to “L” level and “H” level will be described.

It is assumed that the second bit line pair BLB, / BLB is in a precharge state.
As an example, the waveform when the second word line WLB operates at the same timing as the first word line WLA is shown.

  As an initial state, the first and second word lines WLA and WLB are at the “L” level, the first column selection signal YSA is also at the “L” level, and the equalizing MOS transistor PQ3 and the precharge MOS transistors PQ4 and PQ5 First bit line pair BLA, / BLA is precharged to “H” level. On the other hand, transfer MOS transistors NQ7 and NQ8 are not conductive.

Next, the “L” level is input to the first write data DA.
Complementary first write input data DN and / DN are input to the first write drive circuit 6A by the first input circuit 4A in accordance with the first write data DA. Then, it is inverted and output to output nodes CW and / CW of the first and second write inverters. Here, as an example, the first write input data DN and / DN are at “H” level and “L” level, and the output nodes CW and / CW are at “L” level and “H” level.

  Next, first column selection signal YSA attains “H” level, and equalize MOS transistor PQ3 and pull-up MOS transistors PQ4 and PQ5 are rendered non-conductive. Then, transfer MOS transistors NQ7 and NQ8 are rendered conductive, and the potentials of output nodes CW and / CW of the first and second write inverters are transmitted to first bit line pair BLA and / BLA, and the first bit The line BLA is drawn to the “L” level.

  Next, the first and second word lines WLA and WLB are set to the “H” level, the potential of the first bit line BLA is transmitted to the storage node MN, and the potential of MN decreases.

  On the other hand, since the second word line WLB is also at the “H” level, a precharge current flows from the second bit line BLB, and the storage node MN is not completely at the ground potential.

  Therefore, load MOS transistor PQ2 is not sufficiently conductive, and the rate at which storage node / MN rises to "H" level is slow.

  Here, when first boost signal BSTA is set to “H” level, output node / BSTA connected to the gate of N-channel power MOS transistor NQ11A by inverter INV1A is set to “L” level. As a result, N channel power MOS transistor NQ11A is rendered non-conductive, and source node WBSA of the write inverter becomes floating.

  Next, the output node NBSTA of the buffer BF1A becomes “L” level. Accordingly, source node WBSA of the write inverter is boosted to a negative potential based on boost capacitor element Cb13A.

  The potential of source node WBSA pulls down the potential of first bit line BLA via N channel MOS transistor NQ9 and transfer MOS transistor NQ7 of the first write inverter.

  Then, gate-source voltage Vgs of access MOS transistor NQ3 increases, current drive capability of N-channel MOS transistor NQ3 increases, and the potential of storage node MN is further lowered.

  As load MOS transistor PQ2 becomes more conductive, storage node / MN is pulled up to the “H” level, and the inversion of the storage node is accelerated.

  As a result, variations due to miniaturization become large, and stable writing can be performed at high speed even when the power supply voltage is low.

  However, the potential of the first bit line BLA rises due to the inflow of current from the second bit line BLB. If the potential of the first bit line BLA changes to positive, the effect of assisting writing is lost, and the potential that has been inverted once may be restored.

  Therefore, before the potential of first bit line BLA changes to positive, boost signal BSTA needs to be returned to “L” level, power supply MOS transistor NQ11A is made conductive, and source node WBSA of the write inverter needs to be returned to the ground potential. is there.

  Thereafter, by setting the first word line WLA to the “L” level, the states of the storage nodes MN and / MN are inverted and stabilized.

  Thereafter, by setting the first column selection signal YSA to the “L” level, the first bit line pair BLA, / BLA is precharged, and the write operation is completed.

FIG. 6 is a diagram illustrating the arrangement of signal wirings according to the first embodiment.
As shown in FIG. 6, this example shows a case where a metal wiring layer is formed in the upper layer of the memory cell array 1.

  Specifically, the case where the signal wiring is arranged along the same row direction as the power supply wiring for supplying the voltage VDD and the power supply wiring for supplying the voltage VSS provided in the upper layer of the memory cell array 1 is shown. As an example, the same metal wiring layer as the power supply wiring for supplying the voltages VDD and VSS is used.

  In this example, signal wirings ML11A and ML12A are provided between the power supply wirings for supplying voltages VDD and VSS. Moreover, the case where signal wiring ML11B and ML12B are provided according to the same system is shown.

  Further, it is a configuration provided in the upper layer of the memory cell array 1, and is not a configuration in which a boost capacitance element is provided on the substrate, but the first and second signal wirings are arranged, and the boost capacitance is based on the coupling capacitance between the signal wirings. Since the element is provided, the chip area can be reduced.

  In the above configuration, the two signal wirings are sandwiched between the power supply wirings, but the number and order of the signal wirings are arbitrary. Further, a ground line may be sandwiched next to the signal wiring as appropriate.

  Further, the capacitance value of the boost capacitor element can be easily adjusted by adjusting the length of the signal wiring.

  Even if the bit lines provided in the memory cell array 1 have different lengths, the boost capacitance can be easily changed according to the length of the bit lines. Appropriate boost capacitance can be easily formed even for memory IPs having different bit line lengths.

FIG. 7 is a diagram illustrating the structure of the signal wiring according to the first embodiment.
As shown in FIG. 7, a MOS transistor is provided on a semiconductor substrate. A bit line pair BLA, / BLA is provided in the upper metal wiring layer. Further, a word line WLA is provided in an upper layer. Further, power supply wirings of voltages VDD and VSS are provided in an upper layer. And signal wiring ML11A and ML12A are provided in the same metal wiring layer.

  Further, the power supply wirings of the voltages VDD and VSS can also act as a shield effect for preventing crosstalk from the signal wiring in the same layer. Further, as long as the wiring is fixed during the boost operation with respect to the shield effect, the power supply wiring for supplying the voltages VDD and VSS may not be used.

FIG. 8 is a diagram for explaining another signal wiring arrangement according to the first embodiment.
As shown in FIG. 8, as compared with the memory cell array 1, signal wiring is not arranged from the upper end to the lower end along the row direction, but is half the length of the memory cell array 1A in the row direction. Is also possible.

FIG. 9 is a diagram for explaining another signal wiring arrangement according to the first embodiment.
As shown in FIG. 9, the memory cell array 1B is different in that a signal wiring is further added to the first signal wiring ML11A and the second signal wiring ML12A.

A plurality of sub signal wirings ML15A are provided for the first signal wiring ML11A.
A plurality of sub signal wirings ML16A are provided for the second signal wiring ML12A.

  The sub signal wiring ML11A is connected to the plurality of sub signal wirings ML15A via contacts CT1.

  The sub signal wiring ML12A is connected to the plurality of sub signal wirings ML16A through contacts CT2.

  The sub signal wirings ML15A and ML16A are arranged along the column direction with respect to the direction intersecting the power supply line. The plurality of sub signal wirings can be formed using the upper or lower metal wiring layer of the first signal wiring ML11A and the second signal wiring ML12A. With this configuration, the boost capacitance of the boost capacitance element can be easily adjusted.

(Modification)
In the above description, the boost capacitor element is formed by the signal wiring.

In the present modification, adjustment of the potential change ΔV by the boost capacitor element will be described.
The amount of voltage drop (potential change ΔV) when the negative voltage is boosted is determined by the ratio of the boost capacitance to the ground capacitance.

ΔV = −CB / (CB + CG) × VDD (Formula 1)
Here, CG = Cg13A + Cg2T + Cg3T
CB = Cb13A
CG is the sum of the parasitic capacitance Cg13A attached to the signal wiring ML12A, the parasitic capacitance Cg2T attached to the output node CW of the first write inverter, and the parasitic capacitance Cg3T attached to the first bit line BLA.

  However, the influence of the channel resistance, diffusion layer capacitance, and gate capacitance of N channel MOS transistors NQ9, NQ7, NQ5 is not taken into consideration for the sake of simplicity of explanation.

When the total capacity is Call, it is expressed by the following equation 2.
Call = CB + CG (Formula 2)
In the dual port SRAM, current flows from the bit line of the port in the half-selected state (the word line is selected, the bit line is not selected and the precharge state), and the negative voltage at the time of boost rises. Impairs driving ability. This becomes conspicuous when the bit line is short and the bit line capacitance is small.

  When the boost capacity is increased and the voltage drop amount (potential change ΔV) of the bit line is increased, the access MOS transistors of the memory cells that share the bit line and are connected to different word lines do not conduct. Cell data may be inverted. That is, since there is a possibility of erroneous writing, the potential change ΔV needs to be in a certain range.

  On the other hand, in the half-selected state (the word line is selected, the bit line is not selected and the precharge state), even if the bit line on the writing side is set to a negative potential, current flows from the bit line of the half-selected port Therefore, there is a possibility that the bit line on the writing side cannot be kept at a negative potential. Therefore, it is necessary to increase the ground capacitance in order to stably maintain the bit line on the writing side at a negative potential.

  Therefore, from the above formulas 1 and 2, in order to increase the total capacity Call while keeping the potential change ΔV at the optimum point, it is only necessary to increase both while keeping the ratio of CB and CG constant.

  FIG. 10 is a diagram illustrating the configuration of first and second write assist circuits 5A # and 5B # according to a modification of the first embodiment.

  As shown in FIG. 10, as compared with the configuration of FIG. 4, with respect to the first write assist circuit 5A #, capacitive elements Cg11A and Cg12A are further added as grounded capacitive elements, and boost capacitive elements Is different from the capacitor elements Cb11A and Cb12A.

  Capacitance elements Cb11A and Cb12A are provided between output node NBSTA and source node WBSA, respectively.

  The capacitive element Cg11A is provided between the source node WBSA and the voltage VSS. Capacitance element Cg12A is connected to source node WBSA.

  The capacitive element Cg12A is formed as a MOS capacitor. The source and drain of the MOS transistor are connected to source node WBSA, and the gate is connected to voltage VDD.

  Capacitance element Cb12A is formed as a MOS capacitor connected between output node NBSTA and source node WBSA.

  With this configuration, the ratio of CG and CB in Equation 1 can be made constant, and necessary capacitance can be secured and the potential change ΔV can be adjusted to an optimum value.

  In the present embodiment, the configuration in which the capacitive elements Cb11A and Cb12A are provided as the boost capacitive elements has been described. However, a single capacitive element is also possible. For example, MOS capacitors with good area efficiency may be used as the capacitors Cb12A and Cg12A. The same applies to the capacitive elements Cg11A and Cg12A.

  In this example, N-channel MOS capacitors are used as the capacitive elements Cb12A and Cg12A. However, P-channel MOS capacitors may be used.

  Since the configuration of first write assist circuit 5B # is the same, detailed description thereof will not be repeated.

  Capacitance elements Cg11A, Cg12A, Cg2T, Cg2B, Cg3T, and Cg3B are grounded capacitors for convenience of explanation. However, if the potential is fixed during the write operation, they are connected to the power supply VDD and other signal nodes. It is good also as a structure.

(Embodiment 2)
FIG. 11 is a diagram for explaining the configuration of the first write assist circuit 5A according to the second embodiment.

  Referring to FIG. 11, there is shown a case where a plurality of first write drive circuits 6A and a plurality of first write auxiliary circuits 5A are provided corresponding to a plurality of memory cell columns, respectively. The plurality of first write assist circuits 5A share the source node WBSA. Here, a case is shown in which the source nodes WBSA of the adjacent first write auxiliary circuits 5A are connected in common. The same applies to the other write assist circuits 5A, and the second write assist circuit 5B is provided in the same manner as the first write assist circuit 5A.

  In the disturb write described above, when the threshold voltage of the disturb-side access MOS transistor NQ5 becomes low, the potential rise of the write-side bit line becomes significant. However, the threshold voltage of NQ5 of all the memory cells that perform writing at the same time rarely varies and becomes low, and some of them have a high threshold voltage.

  Therefore, it is possible to share the total capacity Call by sharing the source node WBSA. As a result, it is possible to reinforce writing to a transistor having a slow writing operation due to transistor variations.

(Embodiment 3)
In the third embodiment, a method for further improving the boost capability will be described.

  FIG. 12 is a diagram illustrating the configuration of first and second write assist circuits 5AP and 5BP according to the third embodiment.

  As shown in FIG. 12, the first write assist circuit 5AP is different from the first write assist circuit 5A in that a buffer BF2A and a third signal line ML13A are added.

  The buffer BF2A is connected to the first signal wiring ML11A, and drives the third signal wiring ML13A according to the signal level transmitted to the first signal wiring ML11A.

Since the same applies to second write assist circuit 5BP, detailed description thereof will not be repeated.
Output node NBSTA is connected to signal line ML11A, and node WBSA is connected to signal line ML12A. The signal lines ML11A and ML12A are arranged in parallel with the bit lines and are arranged on the memory cell array 1.

  Boost capacitance element Cb13A is formed based on the coupling capacitance between the wirings between signal wiring ML11A and signal wiring ML12A. Further, the boost capacitor element Cb14A is formed based on the coupling capacitance between the signal wiring ML13A and the signal wiring ML12A.

A grounding capacitor Cg13A is formed between the signal line ML12A and the ground.
Although the case where the buffer BF2A is arranged inside the second write assist circuit 5BP is shown, the location is not particularly specified, and the buffer BF2A may be arranged at any position.

FIG. 13 is a diagram for explaining the signal waveform of the write operation according to the third embodiment.
In the third embodiment, a case where the boost operation is performed a plurality of times will be described with reference to FIG.

In this example, the case where the boost operation is performed twice is shown.
The delay time in the buffer BF2A is set to a shorter time than when the potential of the bit line on the write side rises to near 0V due to the inflow of current from the bit line on the disturb side.

  In a state where the storage nodes MN and / MN are at the “H” level and “L” level, the first word line WLA and the first bit line pair BLA and / BLA are used, and the storage nodes MN and / MN are set to “L”. ”Level and“ H ”level will be described.

It is assumed that the second bit line pair BLB, / BLB is in a precharge state.
As an example, the second word line WLB shows a waveform when operating at the same timing as the first word line WLA.

  As an initial state, the first and second word lines WLA and WLB are at the “L” level, the first column selection signal YSA is also at the “L” level, and the equalizing MOS transistor PQ3 and the precharge MOS transistors PQ4 and PQ5 First bit line pair BLA, / BLA is precharged to “H” level. On the other hand, transfer MOS transistors NQ7 and NQ8 are not conductive.

Next, the “L” level is input to the first write data DA.
According to the first write data DA, the first input circuit 4A complements the first write input data DN, / DN at "H" level and "L" level, and the output nodes CW, / CW are at "L" level. ”Level and“ H ”level.

  Next, first column selection signal YSA attains “H” level, and equalize MOS transistor PQ3 and pull-up MOS transistors PQ4 and PQ5 are rendered non-conductive. Then, transfer MOS transistors NQ7 and NQ8 are rendered conductive, and the potentials of output nodes CW and / CW of the first and second write inverters are transmitted to first bit line pair BLA and / BLA, and the first bit The line BLA is drawn to the “L” level.

  Next, the first and second word lines WLA and WLB are set to the “H” level, the potential of the first bit line BLA is transmitted to the storage node MN, and the potential of MN decreases.

  On the other hand, since the second word line WLB is also at the “H” level, a precharge current flows from the second bit line BLB, and the storage node MN is not completely at the ground potential.

  Therefore, load MOS transistor PQ2 is not sufficiently conductive, and the rate at which storage node / MN rises to "H" level is slow.

  When first boost signal BSTA is set to “H” level, node / BSTA connected to the gate of N-channel power MOS transistor NQ11A by inverter INV1A is set to “L” level. As a result, N channel power MOS transistor NQ11A is rendered non-conductive, and source node WBSA of the write inverter becomes floating.

  Next, the output node NBSTA of the buffer BF1A becomes “L” level. Accordingly, source node WBSA of the write inverter is boosted to a negative potential based on boost capacitor element Cb13A.

  The potential of source node WBSA pulls down the potential of first bit line BLA via N channel MOS transistor NQ9 and transfer MOS transistor NQ7 of the first write inverter.

  Then, the gate-source voltage Vgs of access MOS transistor NQ3 increases, the current driving capability of NQ3 increases, and the potential of storage node MN is further lowered.

  As load MOS transistor PQ2 becomes more conductive, storage node / MN is pulled up to the “H” level, and the inversion of the storage node is accelerated.

  However, the potential of the first bit line BLA rises due to the inflow of current from the second bit line BLB. If the potential of the first bit line BLA changes to positive, the effect of assisting writing is lost, and the potential that has been inverted once may be restored.

  In the third embodiment, re-boost is further performed by using the buffer BF2A and the signal wiring ML13A.

  The output node NBST2A of the buffer BF2A becomes “L” level. Along with this, the source node WBSA of the write inverter is further boosted to a negative potential based on the boost capacitor element Cb14A.

  Thereby, the inversion of the storage node is accelerated again. After that, before the potential of the first bit line BLA changes to positive, the boost signal BSTA needs to be returned to the “L” level, the power MOS transistor NQ11A is turned on, and the source node WSB of the write inverter needs to be returned to the ground potential. is there.

  Thereafter, by returning the first word line WLA to the “L” level, the states of the storage nodes MN and / MN are inverted and stabilized.

  Thereafter, by returning the first column selection signal YSA to the “L” level, the first bit line pair BLA, / BLA is precharged, and the write operation is completed.

  When the boost capacitor CB is increased, the potential change ΔV of the bit line potential due to the boost operation increases, and thus erroneous writing may occur in the memory cells connected to the unselected word lines.

  According to the third embodiment, it is possible to reduce the potential change ΔV per time by dividing the boost operation into a plurality of times, and thus it is possible to prevent the erroneous writing described above.

  In this example, the configuration of the 8-transistor type dual-port SRAM has been described. However, the configuration is not particularly limited to this configuration, and the present invention can be similarly applied to a so-called 6-transistor single-port SRAM.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  1, 1A, 1B memory cell array, 2A first row selection drive circuit, 2B second row selection drive circuit, 3A first column selection circuit, 3B second column selection circuit, 4A first input circuit, 4B 2nd input circuit, 5A, 5AP 1st write auxiliary circuit, 5B, 5BP 2nd write auxiliary circuit, 6A 1st write drive circuit, 6B 2nd write drive circuit, 7A 1st Bit line pair charging circuit, 7B Second bit line pair charging circuit, 8A First control circuit, 8B Second control circuit.

Claims (2)

A memory cell;
A metal wiring layer provided in an upper layer of the memory cell;
A first wiring disposed along the first direction in the metal wiring layer and supplying a first voltage to the memory cell;
A second wiring arranged along the first direction in the metal wiring layer and supplying a second voltage different from the first voltage to the memory cell;
A first signal wiring disposed along the first direction in the metal wiring layer;
Have
In plan view, the first signal wiring is a dual-port SRAM disposed between the first wiring and the second wiring. A third wiring that is disposed along the first direction and supplies the first voltage to the memory cell in the metal wiring layer;
The metal wiring layer further comprising a second signal wiring disposed along the first direction;
2. The dual port SRAM according to claim 1, wherein the second signal wiring is disposed between the second wiring and the third wiring in a plan view.

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