KR100970659B1 - Multilayer substrate for high reliability - Google Patents

Abstract

The present invention relates to a thin film multilayer substrate requiring high reliability, comprising: a ceramic laminate including a plurality of ceramic layers having a predetermined thickness and a plurality of inner conductor patterns disposed between the plurality of ceramic layers, respectively; The pattern includes a first signal line, a second signal line, a third signal line layer, a power supply layer, and a digital power supply layer, wherein the second and third signal lines are disposed between the power supply layer and the digital power supply layer. Prepare the composition.

By using the multilayer board as described above, malfunctions due to external noise and signal interference can be prevented, and the defense industry can maintain high reliability without affecting product functions even in harsh environments.

Noise, Ceramic, Power Supply Layer, Ground Layer

Description

Multilayer substrate for high reliability

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film multilayer substrate requiring high reliability. In particular, the present invention is directed to preventing malfunctions caused by external noise and signal interference, and to preventing product functions in a harsh environment such as the defense industry. It relates to a reliable multilayer substrate.

In addition, the present invention, in particular, in order to improve the interlayer adhesion of the Low Temperature Co-fired Ceramic (hereinafter referred to as 'LTCC') multilayer substrate, the ground (Analog Ground, Digital Ground) and voltage supply (3.3V Power, Low It relates to a high reliability multilayer substrate for designing a voltage power layer in a mesh structure.

In general, LTCC substrate manufacturing technology uses a high-conductivity Ag, Cu, etc. in a large number of green sheet layers based on glass-ceramic materials, and the internal electrodes and passive circuits of a circuit given in a screen printing process. Implement the devices (R, L, C), stack each layer, and simultaneously fire the ceramic and metal (usually 1000˚C or less) to manufacture MCM (Multi-chip module) and Multi-Chip Package I say that.

This LTCC technology has the advantage of implementing passive elements (R, L, C) inside the module according to the process characteristics that can simultaneously fire ceramics and metals, which enables complex and light and short components. LTCC boards are capable of implementing these embedded passives, which is why the system-on-a-

Package can be implemented to minimize parasitic effects in SMD (Surface Mounted Device) components, and to improve electrical characteristics and reduce soldering by reducing electrical noise signals generated at soldered parts during surface mounting. shroud

It has the advantage of improving reliability by reducing.

In the case of LTCC, the Tf (Temperature Coefficient of Resonant Frequency) value can be minimized by adjusting the coefficient of thermal expansion, so that the characteristics of the dielectric resonator can be controlled. Since the LTCC substrate implements a circuit therein and stacks a plurality of them to form a single substrate, external terminals that can be connected to the outside should be formed outside the substrate, and these external terminals are electrically connected to the internal circuit patterns. Should be connected.

That is, the passive element region is formed on the LTCC substrate, and the printing patterns for the passive elements R, L, and C are formed on the upper and lower portions of the passive element region, respectively. By electrically connecting through the passive element pattern is embedded.

As described above, the LTCC substrate can make the via size or via pad connecting the layers and the via pads smaller than the conventional printed circuit board (PCB), and have a passive element embedded therein.

However, the LTCC substrate has a problem that the interlayer adhesion of the multilayer substrate decreases as the number of layers increases. In addition, in areas such as the defense industry, there is a problem that the product function is degraded because of exposure to harsh environments. In other words, there is a lot of environments that can cause malfunction due to interference of the product due to the need for miniaturization, high reliability, high integration and high frequency of products applied in the defense industry. In particular, when operating in a missile launched from the ground or in a harsh environment, there is a lot of interference caused by the surrounding environment, so the products of the defense industry have to minimize the interference to noise to have the reliability of the product.

An object of the present invention is to solve the problems as described above, to provide a multi-layered substrate having a high degree of integration and high reliability.

Another object of the present invention is to provide a multi-layered substrate which improves the interlayer adhesion of the multi-layered substrate and improves the yield of the manufacturing process.

In order to achieve the above object, a high reliability multilayer substrate according to the present invention includes a ceramic laminate including a plurality of ceramic layers having a predetermined thickness and a plurality of inner conductor patterns disposed between the plurality of ceramic layers, respectively, The inner conductor pattern of includes a first signal line, a second signal line, a third signal line layer, a power supply layer and a digital power layer, wherein the second and third signal lines are between the power supply layer and the digital power layer. Characterized in that arranged.

In addition, the multilayer board according to the present invention is characterized in that it further comprises a bonding pad portion, which is a wire bonding layer formed on both main surfaces of the ceramic laminate, and a solder pad portion, which is an external output layer.

In the multilayer board according to the present invention, an analog ground layer is formed below the bonding pad portion, and a digital and analog ground layer is formed above the solder pad portion.

In the multilayer board according to the present invention, the first signal line is disposed between the analog ground layer and the power supply layer, and a signal affected by noise is input to the first signal line.

In the multilayer board according to the present invention, the analog ground layer and the power supply layer form a bypass capacitor layer.

In the multilayer board according to the present invention, the second signal line layer is characterized in that the edge is surrounded by an analog ground layer in order to prevent interference of the input signal by external noise to the maximum.

In the multilayer board according to the present invention, the solder pad part may be formed in a ball grid array (BGA) form.

In the multilayer substrate according to the present invention, the plurality of ceramic layers is characterized in that the low-temperature sintered ceramic.

In the multilayer board according to the present invention, the power supply layer is supplied with 3.3 V power, and the digital power layer is characterized in that the 1.8 V power is supplied.

In addition, in order to achieve the above object, a method of manufacturing a multilayer board according to the present invention is a multilayer having a ceramic laminate composed of a plurality of ceramic layers having a predetermined thickness and a plurality of inner conductor patterns respectively disposed between the plurality of ceramic layers. A method of manufacturing a substrate, comprising: an analog ground layer, a first signal line layer, a power supply layer, a second signal line layer, a third signal line layer, a digital power supply layer, a fourth signal line layer, as the plurality of internal conductor patterns; Laminating in order of the digital ground layer, and providing bonding pad portions and solder pad portions on both main surfaces of the ceramic laminate.

As described above, according to the multilayer board according to the present invention, it is possible to prevent malfunctions caused by external noise and signal interference, and to maintain high reliability without affecting product function even in the harsh environment of the defense industry. Lose.

These and other objects and novel features of the present invention will become more apparent from the description of the present specification and the accompanying drawings.

EMBODIMENT OF THE INVENTION Hereinafter, the structure of this invention is demonstrated according to drawing.

In addition, in description of this invention, the same code | symbol is attached | subjected to the same part and the repeated description is abbreviate | omitted.

1 is a cross-sectional view of a ceramic multilayer substrate according to the present invention.

As shown in FIG. 1, the ceramic multilayer substrate 100 of the present invention includes a ceramic laminate 10 made up of a plurality of ceramic layers, an inner conductor pattern 20 disposed between the ceramic layers, and a ceramic laminate ( A bonding pad portion 29, which is a wire bonding layer formed on both main surfaces (top and bottom surfaces of FIG. 1), and a solder pad portion 29 ', which is an outer output layer, are formed.

In addition, a plurality of surface mounting parts 40 are mounted via the surface electrodes 30 formed in the bonding pad portion 29. As the surface mount component 40, active devices such as semiconductor devices and gallium arsenide semiconductor devices, passive devices such as capacitors, inductors, and resistors, etc., are bonded via solder or conductive resin, or bonding wires 50 such as Au, Al, and Cu. It is electrically connected to the surface electrode 30 of the upper surface of a ceramic laminated body through the said via. The surface mounting components 40 are electrically connected to each other through the surface electrodes 30 and the inner conductor patterns and via holes 70 formed in the plurality of ceramic layers, respectively. The ceramic multilayer substrate 100 may be mounted on a mounting substrate such as a mother board through the ball bonding portion 60 formed on the solder pad portion 29 '.

The material of the ceramic layer constituting the ceramic laminate 10 is not particularly limited as long as it is a ceramic material. For example, a low temperature sintered ceramic (LTCC) material is preferable. Low-temperature sintered ceramic material is a ceramic material that can be sintered at a temperature of 900 ° C. or lower and capable of co-firing with silver or copper having a small specific resistance. Specific examples of low-temperature sintered ceramics include glass composite LTCC materials and ZnO-MgO-Al ₂ O ₃ -SiO ₂ based on a mixture of borosilicate glass and ceramic powder such as alumina or forsterite (Mg ₂ SiO ₄ ). Non-glass LTCC materials using crystallized glass LTCC materials, BaO-Al ₂ O ₃ -SiO ₂ based ceramic powders or Al ₂ O ₃ -CaO-SiO ₂ -MgO-B ₂ O ₃ based ceramic powders Etc. can be mentioned.

 In the structure shown in FIG. 1, the ceramic laminate 10 of the ceramic multilayer substrate 100 is illustrated as nine ceramic layers, but is not limited thereto. The ceramic layer may be added or subtracted according to a use.

In addition, the thickness of each ceramic layer and the inner conductor pattern 20 of the ceramic laminated body 10 is 90 micrometers, for example, and the thickness of the bonding pad part 29 and the soldering pad part 29 'is 30 micrometers. The total thickness of the ceramic multilayer substrate 100 can be formed to 870 탆. However, the thickness is not limited to the above description, and may be changed according to the use of the ceramic multilayer substrate 100.

In addition, the internal conductor pattern 20 provided between each ceramic layer is the first signal line layer which is an analog ground layer 21, CLK and noise sensitive signal lines sequentially from the top in the structure shown in FIG. 22, for example, a power supply layer 23 for supplying 3.3V of power, a second signal line layer 24 and a third signal line layer 25 as input terminals, for example, 1.8V of power. And a digital power supply layer 26, a fourth signal line layer 27 as an output signal line, and a digital ground layer 28.

Next, a structure and a design method of the inner conductor pattern 20, the bonding pad portion 29, and the solder pad portion 29 'will be described with reference to Figs.

FIG. 2 is a view showing a bonding pad portion as a wire bonding layer, FIG. 3 is a view showing an analog ground layer, FIG. 4 is a view showing a first signal line layer, FIG. 5 is a view showing a power supply layer, and FIG. 6 And FIG. 7 shows a second signal line layer and a third signal line layer, respectively, FIG. 8 shows a digital power supply layer, FIG. 9 shows a fourth signal line layer, and FIG. 10 shows a digital ground. It is a figure which shows a layer, and FIG. 11 is a figure which shows the soldering pad part which is an external output layer.

First, the bonding pad portion 29 has a structure as shown in FIG. 2. When providing a wire bonding layer as illustrated in FIG. 2, the surface electrode 30 shown in FIG. 1 may be omitted.

The site where the surface mount component 40 is to be mounted next arranges an analog ground layer 21, which becomes the earth ground as shown in FIG.

CLK, which is affected by noise, is disposed in the first signal line layer 22 as shown in FIG. A bypass capacitor Bypass of the analog ground layer 21 and the power supply layer 23 is disposed below the first signal line layer 22 by supplying a power supply layer 23 for supplying power as shown in FIG. 5. By forming a capacitor layer, noise can be canceled out.

The second signal line layer 24 shown in FIG. 6 is designed in such a way that the edge of the substrate is surrounded by an analog ground layer so as to prevent interference of the input signal mainly by external noise, thereby forming a layer resistant to noise. That is, as can be seen in Figures 4, 6, 7, 9, in order to improve the flatness between layers, a structure in which a dummy pad in the form of a diamond is provided where there is no circuit pattern is used.

The second signal line layer 24 and the third signal line layer 25 shown in FIG. 7 are arranged between the power supply layer 23 which is the power supply and the digital power layer 26 shown in FIG. The output terminal was disposed on the fourth signal line layer 27 shown in FIG. 9 and the digital ground layer 28 shown in FIG.

And the final output layer was designed in the form of a ball grid array (BGA) as shown in Figure 11 in order to form a short line to correspond to the high-speed switching to design a substrate suitable for high speed, high reliability.

Also according to the invention a method of manufacturing a thin film multilayer substrate is as follows,

First, in order to manufacture the low temperature calcined ceramic multilayer substrate 100, a ceramic layer having a predetermined thickness is prepared.

A pattern as shown in Figs. 2 to 11 is formed to implement circuit elements in this ceramic layer. Such a pattern implements various circuit elements together with patterns of other ceramic layers stacked up and down. Typically, the pattern has a smaller width than the external terminal formed later.

A plurality of ceramic layers having been subjected to the above steps are stacked, for example, nine in the structure shown in FIG. That is, in the present invention, the bonding pad portion 29, the analog ground layer 21, the first signal line layer 22, the power supply layer 23, the second signal line layer 24, and the third from the top are sequentially A signal line layer 25, a digital power supply layer 26, a fourth signal line layer 27, a digital ground layer 28, and a solder pad portion 29 '.

After that, it is baked like a normal low-temperature calcined ceramic multilayer substrate and the surface mounted component 40 is mounted to complete the structure as shown in FIG.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary.

The present invention is used in thin film multilayer substrates used in harsh environments in the defense industry.

1 is a cross-sectional view of a multi-layer substrate design according to the present invention,

2 is a view illustrating a bonding pad part that is a wire bonding layer;

3 shows an analog ground layer,

4 shows a first signal line layer,

5 shows a power supply layer,

6 and 7 are diagrams illustrating a second signal line layer and a third signal line layer, respectively;

8 shows a digital power layer,

9 is a view showing a fourth signal line layer;

10 shows a digital ground layer,

11 is a view showing a solder pad portion which is an outer output layer.

Claims (16)

A ceramic laminate comprising a plurality of ceramic layers having a predetermined thickness Comprising a plurality of inner conductor patterns respectively disposed between the plurality of ceramic layers, The plurality of inner conductor patterns include a first signal line, a second signal line, a third signal line layer, a power supply layer, and a digital power supply layer. Further comprising a bonding pad portion, which is a wire bonding layer formed on both main surfaces of the ceramic laminate, and a soldering pad portion, which is an external output layer, The second and third signal lines are disposed between the power supply layer and the digital power supply layer, An analog ground layer is formed below the bonding pad portion. Digital and analog ground layers are formed on the solder pad part, The first signal line is disposed between the analog ground layer and the power supply layer, And a signal affected by noise is input to the first signal line. delete delete delete The method of claim 1, And the analog ground layer and the power supply layer form a bypass capacitor layer. The method of claim 5, The second signal line layer has a structure in which the edge is surrounded by an analog ground layer in order to prevent interference of the input signal by external noise as much as possible, and where there is no circuit pattern, a dummy pad of diamond shape is provided. Board. The method of claim 6, The soldering pad unit is a multi-layer substrate, characterized in that the ball grid array (BGA) form. The method according to any one of claims 1 or 5 to 7, The plurality of ceramic layers is a multi-layer substrate, characterized in that made of low-temperature sintered ceramic. The method of claim 8, 3.3V power is supplied to the power supply layer, And a 1.8V power supply to the digital power supply layer. delete delete delete delete delete delete The method of claim 1, The power supply layer and the ground layer is a multi-layer substrate, characterized in that made of a mesh structure.

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