KR100958358B1 - 반도체 패키지 및 그 제조 방법 - Google Patents
반도체 패키지 및 그 제조 방법 Download PDFInfo
- Publication number
- KR100958358B1 KR100958358B1 KR1020080006878A KR20080006878A KR100958358B1 KR 100958358 B1 KR100958358 B1 KR 100958358B1 KR 1020080006878 A KR1020080006878 A KR 1020080006878A KR 20080006878 A KR20080006878 A KR 20080006878A KR 100958358 B1 KR100958358 B1 KR 100958358B1
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- Prior art keywords
- semiconductor chip
- substrate
- semiconductor package
- transparent
- semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Light Receiving Elements (AREA)
- Led Device Packages (AREA)
Abstract
Description
Claims (2)
- 투명 글래스와;상기 투명 글래스의 저면에 부착되는 FOW 특성을 갖는 투명필름과;기판의 반도체 칩 부착 영역에 부착된 반도체 칩과;상기 반도체 칩의 본딩패드와 상기 기판의 와이어 본딩영역간을 전기적으로 연결하는 와이어와;입출력수단으로서 상기 기판의 저면에 형성된 볼랜드에 융착된 솔더볼;을 포함하여 구성하되,상기 FOW 특성을 갖는 투명필름을 상기 반도체 칩과 와이어를 포함하는 기판의 전체 상면에 걸쳐 밀착시켜 부착시킨 것을 특징으로 하는 반도체 패키지.
- 투명 글래스의 저면에 FOW 특성을 갖는 투명필름을 부착시키는 단계와;스트립 단위의 반도체 패키지 영역 또는 매트릭스 단위의 반도체 패키지 영역을 갖는 기판의 반도체 칩 부착 영역에 반도체 칩을 부착하고, 이 반도체 칩의 본딩패드와 상기 기판의 와이어 본딩영역간을 와이어로 연결하는 와이어 본딩 단계와;상기 반도체 칩과 와이어를 포함하는 기판상에 상기 투명 글래스와 부착되어 있는 투명필름의 저면을 밀착시켜 부착시키는 단계와;상기 기판을 개개의 반도체 패키지로 소잉하는 단계와;소잉된 개개의 반도체 패키지 저면에 노출되어 있는 볼랜드에 입출력단자인 솔더볼을 융착시키는 단계;로 이루어지는 것을 특징으로 하는 반도체 패키지 제조 방법.
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KR1020080006878A KR100958358B1 (ko) | 2008-01-23 | 2008-01-23 | 반도체 패키지 및 그 제조 방법 |
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KR1020080006878A KR100958358B1 (ko) | 2008-01-23 | 2008-01-23 | 반도체 패키지 및 그 제조 방법 |
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KR20090081037A KR20090081037A (ko) | 2009-07-28 |
KR100958358B1 true KR100958358B1 (ko) | 2010-05-17 |
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KR1020080006878A KR100958358B1 (ko) | 2008-01-23 | 2008-01-23 | 반도체 패키지 및 그 제조 방법 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US12002725B2 (en) | 2015-06-04 | 2024-06-04 | Amkor Technology Singapore Holding Pte. Ltd. | Sensor package and manufacturing method thereof |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR102116962B1 (ko) * | 2013-06-25 | 2020-05-29 | 삼성전자주식회사 | 반도체 패키지 |
KR20160143071A (ko) | 2015-06-04 | 2016-12-14 | 앰코 테크놀로지 코리아 주식회사 | 지문센서 패키지 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20060075432A (ko) * | 2004-12-28 | 2006-07-04 | 주식회사 하이닉스반도체 | 스택 패키지 |
KR20080092001A (ko) * | 2007-04-10 | 2008-10-15 | (주)아스트로 | 조명용 발광 다이오드 모듈 |
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- 2008-01-23 KR KR1020080006878A patent/KR100958358B1/ko active IP Right Grant
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20060075432A (ko) * | 2004-12-28 | 2006-07-04 | 주식회사 하이닉스반도체 | 스택 패키지 |
KR20080092001A (ko) * | 2007-04-10 | 2008-10-15 | (주)아스트로 | 조명용 발광 다이오드 모듈 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US12002725B2 (en) | 2015-06-04 | 2024-06-04 | Amkor Technology Singapore Holding Pte. Ltd. | Sensor package and manufacturing method thereof |
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