KR100945792B1 - 어드레스 제어 회로를 포함하는 반도체 집적 회로 - Google Patents

어드레스 제어 회로를 포함하는 반도체 집적 회로 Download PDF

Info

Publication number
KR100945792B1
KR100945792B1 KR1020080022763A KR20080022763A KR100945792B1 KR 100945792 B1 KR100945792 B1 KR 100945792B1 KR 1020080022763 A KR1020080022763 A KR 1020080022763A KR 20080022763 A KR20080022763 A KR 20080022763A KR 100945792 B1 KR100945792 B1 KR 100945792B1
Authority
KR
South Korea
Prior art keywords
address
carry
internal
signal
response
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020080022763A
Other languages
English (en)
Korean (ko)
Other versions
KR20090097555A (ko
Inventor
이경하
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080022763A priority Critical patent/KR100945792B1/ko
Priority to US12/337,521 priority patent/US8068383B2/en
Priority to JP2009008136A priority patent/JP2009217926A/ja
Publication of KR20090097555A publication Critical patent/KR20090097555A/ko
Application granted granted Critical
Publication of KR100945792B1 publication Critical patent/KR100945792B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
KR1020080022763A 2008-03-12 2008-03-12 어드레스 제어 회로를 포함하는 반도체 집적 회로 Expired - Fee Related KR100945792B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020080022763A KR100945792B1 (ko) 2008-03-12 2008-03-12 어드레스 제어 회로를 포함하는 반도체 집적 회로
US12/337,521 US8068383B2 (en) 2008-03-12 2008-12-17 Semiconductor integrated circuit having address control circuit
JP2009008136A JP2009217926A (ja) 2008-03-12 2009-01-16 アドレス制御回路を含む半導体集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080022763A KR100945792B1 (ko) 2008-03-12 2008-03-12 어드레스 제어 회로를 포함하는 반도체 집적 회로

Publications (2)

Publication Number Publication Date
KR20090097555A KR20090097555A (ko) 2009-09-16
KR100945792B1 true KR100945792B1 (ko) 2010-03-08

Family

ID=41062896

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080022763A Expired - Fee Related KR100945792B1 (ko) 2008-03-12 2008-03-12 어드레스 제어 회로를 포함하는 반도체 집적 회로

Country Status (3)

Country Link
US (1) US8068383B2 (https=)
JP (1) JP2009217926A (https=)
KR (1) KR100945792B1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013073651A (ja) 2011-09-28 2013-04-22 Elpida Memory Inc 半導体装置
KR102471523B1 (ko) * 2018-04-26 2022-11-28 에스케이하이닉스 주식회사 반도체 집적 회로 장치 및 이를 포함하는 반도체 메모리 시스템
CN114882934B (zh) * 2021-02-05 2024-06-21 长鑫存储技术有限公司 测试电路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0122099B1 (ko) * 1994-03-03 1997-11-26 김광호 라이트레이턴시제어기능을 가진 동기식 반도체메모리장치
KR19980063307A (ko) * 1996-12-05 1998-10-07 키타오카타카시 반도체 기억장치
KR20070009822A (ko) * 2005-07-14 2007-01-19 주식회사 하이닉스반도체 반도체 메모리 장치의 어드레스 제어 회로
KR20070109104A (ko) * 2006-05-09 2007-11-15 주식회사 하이닉스반도체 반도체 메모리 장치의 로우 어드레스 제어 회로 및 방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652723A (en) * 1991-04-18 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
US5481581A (en) 1995-05-19 1996-01-02 United Memories, Inc. Programmable binary/interleave sequence counter
JPH1186596A (ja) * 1997-09-08 1999-03-30 Mitsubishi Electric Corp 半導体記憶装置
US6778443B2 (en) * 2001-12-25 2004-08-17 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device having memory blocks pre-programmed before erased
JP4232714B2 (ja) 2004-09-02 2009-03-04 ソニー株式会社 読出アドレス制御方法、物理情報取得装置、および半導体装置
KR100799124B1 (ko) * 2006-06-30 2008-01-29 주식회사 하이닉스반도체 동기식 반도체 메모리 소자 및 그의 구동방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0122099B1 (ko) * 1994-03-03 1997-11-26 김광호 라이트레이턴시제어기능을 가진 동기식 반도체메모리장치
KR19980063307A (ko) * 1996-12-05 1998-10-07 키타오카타카시 반도체 기억장치
KR20070009822A (ko) * 2005-07-14 2007-01-19 주식회사 하이닉스반도체 반도체 메모리 장치의 어드레스 제어 회로
KR20070109104A (ko) * 2006-05-09 2007-11-15 주식회사 하이닉스반도체 반도체 메모리 장치의 로우 어드레스 제어 회로 및 방법

Also Published As

Publication number Publication date
KR20090097555A (ko) 2009-09-16
US20090231947A1 (en) 2009-09-17
JP2009217926A (ja) 2009-09-24
US8068383B2 (en) 2011-11-29

Similar Documents

Publication Publication Date Title
KR101033464B1 (ko) 반도체 집적 회로
JP3894273B2 (ja) 同期式メモリ装置
US20090168485A1 (en) Pipe latch device of semiconductor memory device
JP4031102B2 (ja) 同期式半導体メモリ装置のカラム選択ライン制御回路
JP4987458B2 (ja) 半導体記憶装置のデータ出力回路及び方法
US20200098404A1 (en) Semiconductor device
KR100871377B1 (ko) 파이프 래치 장치 및 파이프 래치 방법
US6249483B1 (en) Semiconductor memory device having a circuit for latching data from a data line of a data output path and a related data latching method
KR20050059921A (ko) 반도체 메모리 소자의 ｄｑｓ 신호 생성 회로 및 그 생성방법
US6940321B2 (en) Circuit for generating a data strobe signal used in a double data rate synchronous semiconductor device
KR100682182B1 (ko) 내부 클럭 더블러 및 이를 포함한 반도체 메모리 장치 및그의 데이터 출력방법
KR100464937B1 (ko) 반도체 메모리의 테스트 모드 플래그 신호 발생 장치
KR100945792B1 (ko) 어드레스 제어 회로를 포함하는 반도체 집적 회로
JP2008059735A (ja) 半導体メモリ装置及びその駆動方法
US8483005B2 (en) Internal signal generator for use in semiconductor memory device
KR20110060514A (ko) 내부커맨드생성회로
US8694818B2 (en) Control circuit and operating method thereof
US6192005B1 (en) Clock control signal and output enable signal generator in semiconductor memory device
US7120083B2 (en) Structure and method for transferring column address
JP2009099156A (ja) フューズラッチ回路及びフューズラッチ方法
KR100743634B1 (ko) 반도체 메모리 장치의 명령어 디코딩 회로
KR100771551B1 (ko) 반도체 소자의 컬럼경로 제어신호 생성회로 및 컬럼경로제어신호 생성방법
KR100646202B1 (ko) 구동 주파수를 조절할 수 있는 반도체메모리소자
JP2014078313A (ja) 半導体装置
KR100881402B1 (ko) 반도체 메모리 장치의 입력 회로

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20130227

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20130227

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000