KR100919413B1 - 함몰형 패턴을 구비하는 기판 및 그 제조 방법 - Google Patents
함몰형 패턴을 구비하는 기판 및 그 제조 방법Info
- Publication number
- KR100919413B1 KR100919413B1 KR1020070134277A KR20070134277A KR100919413B1 KR 100919413 B1 KR100919413 B1 KR 100919413B1 KR 1020070134277 A KR1020070134277 A KR 1020070134277A KR 20070134277 A KR20070134277 A KR 20070134277A KR 100919413 B1 KR100919413 B1 KR 100919413B1
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- electrically conductive
- conductive layer
- substrate
- recessed
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000010030 laminating Methods 0.000 claims abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 abstract description 12
- 238000010292 electrical insulation Methods 0.000 abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004848 polyfunctional curative Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
Description
Claims (5)
- 전기 전도층의 표면에 원하는 패턴이 돌출되어 형성되도록 상기 전기 전도층의 표면의 일부를 제거하는 단계,상기 전기 전도층의 표면으로부터 돌출된 패턴이 전기 절연층에 함몰되도록 상기 전기 전도층을 상기 전기 절연층과 라미네이션(lamination)하는 단계, 그리고상기 전기 전도층 중 상기 전기 절연층에 함몰된 패턴을 제외한 부분을 제거하는 단계를 포함하는 기판 제조 방법.
- 제1항에서,상기 전기 전도층의 표면의 일부를 제거하는 단계는상기 전기 전도층의 표면에 포토레지스트층을 형성하는 단계,상기 원하는 패턴에 대응하여 선택적으로 오픈된 사이트를 상기 포토레지스트층에 형성하는 단계,상기 전기 전도층 중 상기 오픈된 사이트에 해당하는 부분을 에칭하여 상기 돌출된 패턴을 형성하는 단계, 그리고상기 포토레지스트층을 제거하는 단계를 포함하는 기판 제조 방법.
- 제1항에서,상기 함몰된 패턴을 제외한 부분을 제거하는 단계는 에칭 또는 필링(peeling)에 의해 수행되는 기판 제조 방법.
- 제1항 내지 제3항 중 어느 한 항의 방법에 따른 기판 제조 방법에 의해 제조된 기판.
- 삭제
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070134277A KR100919413B1 (ko) | 2007-12-20 | 2007-12-20 | 함몰형 패턴을 구비하는 기판 및 그 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070134277A KR100919413B1 (ko) | 2007-12-20 | 2007-12-20 | 함몰형 패턴을 구비하는 기판 및 그 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20090066641A KR20090066641A (ko) | 2009-06-24 |
KR100919413B1 true KR100919413B1 (ko) | 2009-09-29 |
Family
ID=40994609
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020070134277A KR100919413B1 (ko) | 2007-12-20 | 2007-12-20 | 함몰형 패턴을 구비하는 기판 및 그 제조 방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100919413B1 (ko) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100195332B1 (ko) * | 1995-12-29 | 1999-06-15 | 구본준 | 반도체 집적회로의 배선 형성방법 |
JP2000323838A (ja) * | 1999-03-04 | 2000-11-24 | Soshin Electric Co Ltd | 多層基板の製造方法 |
JP2004014672A (ja) * | 2002-06-05 | 2004-01-15 | Toppan Printing Co Ltd | 半導体装置用基板及びその製造方法 |
US7068519B2 (en) * | 1997-11-25 | 2006-06-27 | Matsushita Electric Industrial Co., Ltd. | Printed circuit board and method manufacturing the same |
-
2007
- 2007-12-20 KR KR1020070134277A patent/KR100919413B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100195332B1 (ko) * | 1995-12-29 | 1999-06-15 | 구본준 | 반도체 집적회로의 배선 형성방법 |
US7068519B2 (en) * | 1997-11-25 | 2006-06-27 | Matsushita Electric Industrial Co., Ltd. | Printed circuit board and method manufacturing the same |
JP2000323838A (ja) * | 1999-03-04 | 2000-11-24 | Soshin Electric Co Ltd | 多層基板の製造方法 |
JP2004014672A (ja) * | 2002-06-05 | 2004-01-15 | Toppan Printing Co Ltd | 半導体装置用基板及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20090066641A (ko) | 2009-06-24 |
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