KR100891317B1 - Method of fabricating carrier and coreless substrate manufactured thereof - Google Patents

Abstract

A method of fabricating a carrier and a coreless substrate manufactured thereof are provided to simplify the carrier manufacturing process by omitting the additional alkali etching for the copper film removal of the pad surface. A structure including a plurality of solder pads is formed on the surface of the first carrier phase. The second carrier consisting of a substrate, the release film(211), an adhesive(222) and a reinforcing material(223) is formed. The structure formed between the second carrier and the first carrier is cut. The insulating layer of the first carrier is peeled off from copper foils(120,130). The copper foil is removed by the alkali etching. The semiconductor die is mounted on the solder pad of the second carrier. The release film is exposed to the atmosphere by cutting the lateral side of the substrate.

Description

Carrier manufacturing method and coreless substrate manufactured using the same {METHOD OF FABRICATING CARRIER AND CORELESS SUBSTRATE MANUFACTURED THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coreless substrate, and to a carrier fabrication method, a coreless substrate and a method using the same. The present invention has a feature of preventing the substrate from bending or breaking in the package step by attaching and processing the carrier to the package step.

As electronic products become smaller and lighter, the thickness of printed circuit boards is becoming thinner. A coreless substrate without a core is used to reduce the thickness of the printed circuit board. When the substrate process is performed without the core, the substrate is bent or curled, which causes defects. . In order to solve such a problem, during a printed circuit process, an insulator and a copper foil structure are stacked on a carrier using a carrier, and a PCB process is performed while a substrate is completed.

1A to 1C are diagrams illustrating a carrier manufacturing method according to the prior art. Referring to FIG. 1A, the prior art cuts a cured copper clad copper layer (CCL; copper cladded layer), cuts a prepreg (PREPREG) of the same thickness into a window shape, lays up the layer, and laminates the same. The carrier is formed as follows. Subsequently, the insulating layer and the copper foil are repeatedly laminated on both carrier foil surfaces, and after the substrate processing is completed through a PCB process such as hole processing, plating, etching, and pattern formation, as shown in FIG. By trimming the substrate to separate the carrier to form an ultra-thin substrate. The gist of the prior art is to trim the hardened CCL and release the sealing vacuum to change to atmospheric pressure, so that the copper foil can be easily peeled off.

However, in the prior art, since the vacuum sealing is released and separated from the carrier by trimming to a length (for example, 1.5 cm) larger than the length of the prepreg (1 cm in FIG. 1A) in the trim process step, the trim process is performed. There is a big problem that the substrate loss occurs. When trimming the substrate, it is necessary to minimize the missing areas and this is called the array annual ratio.

In addition, in the prior art, it is troublesome to additionally perform alkali etching after trimming the substrate and then mounting the semiconductor die. In addition, in the prior art, it is not possible to perform auto final visual inspection (AFVI) inspection of the surface state of the pad before alkali etching.

Accordingly, a first object of the present invention is to provide a method for fabricating a coreless substrate which does not require additional alkali etching for removing copper film on the pad surface after mounting and packaging the semiconductor die on a carrier reinforced package substrate. .

A second object of the present invention is to provide a method of manufacturing a substrate that can minimize the loss that is cut off in the process of trimming the coreless substrate in addition to the first object.

In order to achieve the above object, the present invention forms a substrate on which a solder pad is manufactured on upper and lower surfaces of a first carrier, and cuts and laminates a release film on the solder pad, and compresses and laminates an adhesive and a reinforcing material on the second carrier. The carrier is formed on the upper end of the substrate. Subsequently, the structure formed with the substrate on the primary carrier, the secondary carrier composed of the release film, the adhesive and the reinforcement on the primary carrier is diced and cut for each solder pad, and the resin insulator of the unsealed primary carrier is Peel off the copper foil from each other to separate the structure into two substrates. When alkali etching is performed to remove the copper foil remaining as the primary carrier, the solder pad is formed on the secondary carrier. The semiconductor die is packaged on the solder pad and the package substrate on which the die is mounted is released. By cutting both sides to be cut, the vacuum seal of the release film is released to remove the second carrier from the substrate to complete the ultra-thin package substrate from which the carrier is removed.

In the method of manufacturing a coreless substrate, (a) forming a structure including a plurality of solder pads by repeating the lamination, pattern formation, hole processing, plating, and etching processes on the surface of the primary carrier. ; (b) cutting a release film into a size that can cover the solder pads, each of which is aligned on the solder pads, forming a second carrier on top of the structure by laminating and compressing adhesive and reinforcement thereon; (c) dicing and cutting the structure formed between the first carrier and the second carrier for each solder pad, peeling off the insulating layer of the unsealed first carrier from the copper foil, and then etching the copper foil by alkali etching. Thereby treating each of the structures with a solder pad attached to a second carrier; And (d) mounting the semiconductor die on a solder pad formed on the second carrier and cutting the side surface of the substrate to expose the release film to the atmosphere to release the seal and peel off the release film to peel off the second carrier. A method for manufacturing a coreless substrate includes separating and removing a die from a mounted structure.

The present invention can omit the alkali etching operation avoided by the package maker, even though the carrier is attached to secure the substrate strength when transferring the substrate to the package maker for semiconductor die surface mounting, and the carrier is attached. Since the packaging is performed, it is possible to prevent a problem that a defect occurs due to the substrate bending or the lack of strength during the packaging process.

In addition, the present invention does not include a trim process, unlike the prior art, it is possible to solve the problem of substrate loss that is cut off due to the trim and improve the array multiplication ratio of the substrate. In addition, in the conventional carrier method, AFVI inspection of the surface state of the pad before the alkali etching was impossible, but the present invention is constructed by attaching a secondary carrier after confirming the surface state of the pad, so that the PCB itself may be processed in the process itself. Inspection is possible at

The present invention provides a method of manufacturing a coreless substrate, comprising: (a) a first in which copper foil (called "first copper foil") is coated on both upper and lower surfaces with an insulating layer (called "first insulating layer") interposed therebetween. Laying an insulating layer (called a "second insulating layer") and a copper foil (called a "second copper foil") on the upper and lower surfaces of the carrier and selectively opening the second copper foil to define a portion to form a pad, A hole (referred to as "the first hole") is formed by etching the second insulating layer until the first copper foil is exposed from the exposed surface of the second insulating layer that is exposed through the opening, and Ni / Au plating on the opened surface. Subsequently performing copper plating to fill the inside of the first hole with copper plating to form copper foil (referred to as “third copper foil”) on the entire surface of the substrate; (b) selectively etching the third copper foil and the second copper foil to form a circuit, laminating an insulating layer (called a "third insulating layer") and a copper foil (called a "fourth copper foil") on the surface; Selectively opening the fourth copper foil to etch the third insulating layer to the upper portion of the pad where the third copper foil formed in the first hole is patterned to form a hole (referred to as a “second hole”), and to perform copper plating to Filling the inside of the second hole with copper plating to form a copper foil (referred to as "the fifth copper foil") throughout the substrate surface; (c) selectively etching the fifth copper foil and the fourth copper foil to form a circuit such that the pads on which the fifth copper foil is patterned are formed on the pads on which the third copper foil is patterned, and Ni on the surface of the fifth copper foil Performing / Au plating and applying a solder face; (d) laying up the cut release film in alignment with the Ni / Au plated pad of the substrate formed on the first carrier and laminating an adhesive and a reinforcement thereon to form a first carrier on top of the substrate; (e) cutting the substrate stacked between the first carrier and the second carrier to cut a substrate structure having a pair of pads between the second carriers, each of the upper and lower pads centered on the first carrier; (f) separating the copper foil of the first carrier from the insulating layer with the center of the insulating layer of the first carrier separated into a pair of upper and lower substrates, and performing alkali etching to remove the copper foil; And (g) solder-bonding the semiconductor die on the exposed Ni / Au plated pad after the copper foil is removed in the step (f), and cutting the side surface of the substrate on which the semiconductor die is mounted to expose the release film. And removing the second carrier from the substrate by releasing the vacuum seal and peeling off the release film.

Hereinafter, with reference to the accompanying drawings Figures 2a to 2q will be described in detail a preferred embodiment of a carrier manufacturing method and a coreless substrate manufacturing method using the same according to the present invention. Referring to FIG. 2A, a copper cladded layer (CCL) having copper foils 120 and 130 coated on both surfaces of the insulating layer 110 is used as a carrier. The insulating layer 140 and the copper foil 150 are laminated on the CCL (FIG. 2B), a dry film (not shown) is applied, and a dry film is patterned and opened so as to selectively etch only a desired portion, and the exposed copper foil By etching the 150 and the insulating layer 140, the copper foils 120 and 130 of the CCL carrier are selectively opened and exposed.

Ni / Au plating is performed on the surfaces of the selectively exposed copper foils 120 and 130 to form Au layer 165 and Ni layer 166, and copper plating is performed on the copper-filled surface of the inside of the hole by copper plating. ) Is formed (FIG. 2D). Subsequently, a dry film (not shown) is applied and a pattern is formed to form a pad on the Ni / Au surface to form a circuit as shown in FIG. 2E.

Then, the insulating layer 170 and the copper foil 171 are laminated (FIG. 2F), and the insulating layer 170 and the copper foil 171 are selectively formed so that the holes 173 are formed on the patterned copper foil 167. The pattern is etched (Fig. 2g). Subsequently, copper plating is performed to fill all of the inside of the hole 173 with copper plating to form copper foil 181 on the surface, and the copper foil 181 is additionally stacked on the copper foil 167 formed on the Ni / Au layer. An etch pattern is formed to form a copper foil circuit (FIG. 2H).

Next, Ni / Au plating is performed to form a Ni layer 182 and an Au layer 183, and a solder paste 184 is applied (FIG. 2I). Then, as shown in Figure 2j, the release film 211, the adhesive 222 and the reinforcing material 223 is laid up on the surface of the substrate laminated on the carrier and laminated. At this time, the release film 211 is cut in a rectangular shape to the extent that it covers the pads of the individual substrates to be diced and separated in a subsequent process, and laid up.

2K is a view showing a structure in which a release film 221, an adhesive 222, and a reinforcing material 223 are layed up on a surface of a substrate formed on a carrier according to a preferred embodiment of the present invention. Finally, when the stacked substrates are cut along the cutting plane 230 indicated by a dashed-dotted line as shown in FIG. 2L, as shown in FIG. 2M, all of the substrates formed above and below the carrier can be diced. Then, peeling off the copper foil with the insulator between the copper foils 120 and 130 interposed therebetween, the substrate of FIG. 2m can be separated into two upper and lower substrates as shown in FIG. 2n. The exposed copper foils 120 and 130 may then be removed through alkali etching.

Subsequently, the copper foil 130 is removed by alkali etching to obtain a substrate from which the copper foil is removed as shown in FIG. 2O. When the substrate of FIG. 2O is delivered to a packager (eg, an SMT processor), the packager may surface mount and package a semiconductor die using solder on a layer of gold 183, which is a pad side of the substrate, and then release film 211. The release film 211 is released from the vacuum sealing state by dicing along the cut surface 298 so that the () is exposed (Fig. 2P).

Then, the release film 211 is peeled off to peel off the adhesive 222 and the reinforcing material 223. 2q shows the package substrate with the reinforcing material finally removed.

The foregoing has outlined rather broadly the features and technical advantages of the present invention to better understand the claims of the invention which will be described later. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously evolved, substituted and changed without departing from the spirit or scope of the invention described in the claims.

The present invention relates to a method for manufacturing a coreless substrate, and in the package operation step for mounting the semiconductor die surface, the carrier is attached to secure the substrate strength, so that the alkaline etching operation can be omitted during the package step It is possible to prevent a problem that a defect occurs due to the bending of the substrate or the lack of strength. In addition, the present invention does not include a trim process, unlike the prior art, it is possible to solve the problem of substrate loss that is cut off due to the trim and improve the array age ratio of the substrate. In addition, in the conventional carrier method, AFVI inspection of the surface state of the pad before the alkali etching was impossible, but the present invention is constructed by attaching a secondary carrier after confirming the surface state of the pad. Inspection is possible.

1A to 1C show a carrier fabrication method according to the prior art.

Figure 2a to 2q is a view showing a carrier manufacturing method and a coreless substrate manufacturing method using the same according to the present invention.

<Explanation of symbols for the main parts of the drawings>

                   110, 140, 170: insulation layer

    120, 130, 150, 167, 171, 181: copper foil

                        165, 183: Au layer

                        166, 182: Ni layer

                             173: Hall

                             184: solder paste

                             211: release film

                             222: adhesive

                             223: reinforcement

                             298: cutting plane

Claims (3)

In the method of manufacturing a coreless substrate, (a) forming a structure including a plurality of solder pads by repeatedly performing lamination, pattern formation, hole processing, plating, and etching processes on a surface of the primary carrier; (b) cutting a release film into a size that can cover the solder pads, each of which is aligned on the solder pads, forming a second carrier on top of the structure by laminating and compressing adhesive and reinforcement thereon; (c) dicing and cutting the structure formed between the first carrier and the second carrier for each solder pad, peeling off the insulating layer of the unsealed first carrier from the copper foil, and then etching the copper foil by alkali etching. Thereby treating each of the structures with a solder pad attached to a second carrier; And (d) mounting the semiconductor die on a solder pad formed on the second carrier and cutting the side of the substrate to expose the release film to the atmosphere to release the seal and peel off the release film to peel off the second carrier Separating and removing from the mounted structure;  Coreless substrate manufacturing method comprising a. The method of claim 1, wherein step (a) (aa) An insulating layer ("second insulating layer") on the upper and lower surfaces of the first carrier coated with copper foil (called "first copper foil") on both upper and lower surfaces with an insulating layer (called "first insulating layer") interposed therebetween. And a copper foil (referred to as "second copper foil") and selectively opening the second copper foil to define a portion to form a pad, and selectively opening and exposing from the exposed second insulating layer surface 1 By forming the hole (referred to as "first hole") by etching the second insulating layer until the copper foil is exposed, the inside surface of the first hole by copper plating followed by Ni / Au plating on the opened surface Filling with copper plating to form copper foil (referred to as "third copper foil") throughout the substrate surface; (ab) selectively etching the third copper foil and the second copper foil to form a circuit, laminating an insulating layer (called "third insulating layer") and copper foil (called "fourth copper foil") on the surface, and Selectively opening the fourth copper foil to etch the third insulating layer to the upper portion of the pad where the third copper foil formed in the first hole is patterned to form a hole (referred to as a “second hole”), and to perform copper plating to Filling the inside of the second hole with copper plating to form a copper foil (referred to as "the fifth copper foil") throughout the substrate surface; And (ac) selectively etching the fifth copper foil and the fourth copper foil to form a circuit such that the pads on which the fifth copper foil is patterned are formed on the pads on which the third copper foil is patterned, and Ni on the surface of the fifth copper foil. Performing / Au plating and applying a solder face; Coreless substrate manufacturing method comprising a. A package substrate on which a semiconductor die manufactured by any one of claims 1 and 2 is mounted.

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