KR100862216B1 - The nonvolatile dram having capacitorless dram characteristic and nonvolatile memory characteristic by resistance switching material - Google Patents

Abstract

A non-volatile dram having a capacitorless dram characteristic and a non-volatile memory characteristic by a resistance switching material are provided to increase the degree of integration by removing a capacitor. A hole envelopment layer(110) is formed on a semiconductor substrate(100). A floating body(120) is formed on the hole envelopment layer. A resistance switching material layer(150) is formed on the floating body. A gate(160) is formed on the resistance switching material layer. A source and a drain are formed between the floating bodies on the hole envelopment layer. The hole envelopment layer is formed with an insulator. The hole envelopment layer is an ion implantation layer. The ion implantation layer is formed by implanting P type impurity ions into the semiconductor substrate.

Description

Non-volatile DRAM with Capacitor-less DRAM and Non-volatile Memory by Resistance Change Material

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly, to a fusion memory having characteristics of capacitorless DRAM and resistance random access memory.

The semiconductor memory device has a high number of memory cells per unit area, that is, a high degree of integration, a fast operation speed, and low power consumption. Various types of memory devices have been developed to satisfy these conditions.

In the case of DRAM (Dynamic Random Access Memory), a typical semiconductor memory device, a unit memory cell is generally composed of one transistor and one capacitor. DRAM has the advantage of high integration and fast operation speed. However, after the power is turned off, all the stored data is lost. In addition, the capacitor formation process is complicated when the device is scaled down for high integration, resulting in process problems as the integration of the device increases, and the capacitor formation process is also difficult to form embedded chips with other devices. Acts as.

Therefore, one of the things that are being studied as a device for overcoming the disadvantages of the DRAM is a capacitorless DRAM. A capacitorless DRAM is a DRAM that can store data without a capacitor that causes a complicated process in the DRAM, and stores data by storing an electric charge in a body.

1A is a cross-sectional view illustrating the operation of a capacitorless DRAM. In a transistor made on an insulating layer silicon-on-insulator (SOI) substrate, applying a large voltage to the gate 13 and the drain 12 causes it to exceed the channel on the drain 12 side by impact ionization. Holes 1 are created. These excess holes are gathered in the body 14 with the lowest potential because there is no exit to exit because of the insulating layer 10 below the body 14. In this case, the transistors with the collected holes have a difference in the threshold voltage and the current level when there is no hole in the previous body. The difference distinguishes '0' and '1'.

Meanwhile, a flash memory is a representative example of a nonvolatile memory device in which stored data may be preserved even after the power is turned off. Unlike volatile memory, flash memory has nonvolatile characteristics, but has a disadvantage of high operating voltage and slow operation speed. In addition, high integration is facing the physical limitations of scale-down.

Non-volatile memory devices that are currently being researched include magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase-change random access memory (PRAM), and resistance random access memory (RRAM).

RRAM is a memory device whose resistance change material varies depending on the voltage. Since RRAM can operate without a transistor like a DRAM, it is very advantageous in terms of integration and its structure is simple and the process is very simple. have.

1B is a cross-sectional view schematically showing an RRAM. A resistance change material layer 21 is formed between the lower electrode 20 and the upper electrode 22. The lower electrode 20 and the upper electrode 22 are formed of a general conductive material, and the resistance change material layer 21 is formed of a material having resistance change characteristics. When an appropriate voltage is applied between the upper electrode 22 and the lower electrode 20, the resistance value of the resistance change material layer 21 is changed, and the difference between the resistance values of the resistance change material layer 21, that is, the resistance value is changed. 0 'and' 1 'are distinguished by the difference between the low state (LRS-Low Resistance State) and the high resistance state (HRS-High Resistance State).

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile DRAM (ReSFET) capable of maintaining data stored as an RRAM device even when a power supply is interrupted, and capable of operating at a high speed such as a DRAM or a capacitorless DRAM at the time of power supply. .

The nonvolatile DRAM according to the present invention includes a semiconductor substrate, a hole encapsulation layer formed on the semiconductor substrate, a floating body formed on the hole encapsulation layer, a resistance change material layer formed on the floating body, a gate formed on the resistance change material layer, and a hole encapsulation layer. And a source and a drain formed to be spaced apart from each other with the floating body therebetween.

Here, it is preferable that a hole surrounding layer consists of an insulator.

Alternatively, the hole envelope layer is preferably an ion implantation layer.

Here, the ion implantation layer is preferably a layer in which impurity ions are implanted into the semiconductor substrate.

Here, the ion implantation layer is preferably a layer in which germanium (Ge) is injected into the semiconductor substrate.

Here, the floating body is preferably formed so that the thickness is thicker than the maximum depletion width of the channel of the nonvolatile DRAM.

Here, it is preferable to further include a back gate formed under the semiconductor substrate.

Here, the floating body is preferably formed so that its thickness is thinner than the maximum depletion width of the channel of the nonvolatile DRAM.

Here, the floating body is preferably formed of a fin (Fin) structure.

Here, the resistance change material layer is nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, zinc (Zn) oxide, tungsten (W) oxide, (cobalt) Co oxide, vanadium It is preferred to include at least one substance of (V) oxide.

The nonvolatile DRAM according to the present invention can maintain data stored in a unit cell even when power supply is interrupted, and can operate at high speed like a DRAM when power is supplied. In addition, since the nonvolatile DRAM according to the present invention does not include a capacitor, high integration can be realized.

Hereinafter, a nonvolatile DRAM according to the present invention will be described in detail with reference to the accompanying drawings. Components that are the same or serve the same throughout the drawings are indicated by the same reference numerals.

[First Embodiment]

2 illustrates a nonvolatile DRAM according to a first embodiment of the present invention. The nonvolatile DRAM (ReSFET) according to the first embodiment of the present invention may include a substrate 100, a hole encapsulation layer 110, a floating body 120, a source 130 and a drain 140, and a resistance change material 150. And gate 160. The hole encapsulation layer 110 is formed on the substrate 100, and the floating body 120 is formed on the hole encapsulation layer 110. In addition, the source 130 and the drain 140 are formed on the hole enveloping layer 110 with the floating body 120 interposed therebetween. A resistance change material layer 150 is formed on the floating body 120, and a gate 160 is formed thereon.

Hereinafter, the semiconductor substrate 100 will be described based on using a P-type silicon substrate for convenience. However, the semiconductor substrate 100 may be formed of a general material used for the semiconductor substrate, and may be formed of any one of silicon, silicon germanium, tensile silicon, or tensile silicon germanium and silicon carbide.

The hole enveloping layer 110 is a layer for preventing holes from escaping from the floating body 120 so that holes can accumulate in the floating body 120 as described below. The hole envelope layer 110 may be formed of an insulator such as a general oxide. Alternatively, the hole envelope layer 110 may be an ion implantation layer. Here, the ion implantation layer refers to a layer in which germanium or a high concentration of P-type impurity ions are implanted into the semiconductor substrate 100. 3 is a diagram illustrating an energy band diagram of the floating body 120-the hole encapsulation layer 110-the substrate 100. 3A illustrates a case where the hole encapsulation layer 110 is an ion implantation layer implanted with germanium ions, and FIG. 3B illustrates an ion implantation layer where the hole encapsulation layer 110 is implanted with P-type impurity ions. If Referring to FIG. 3A, the electron affinity (Х) values of silicon and germanium are almost the same, and the energy levels of the conduction band (Ec) are almost the same, so that a barrier to electrons is not formed. . However, the difference in the valence band (Ev) energy level occurs due to the difference in the energy bandgap (Eg) according to the material difference, and due to this difference, a hole barrier is formed so that holes are localized in the barrier. Enemies are trapped and can collect holes. FIG. 3B is an energy band diagram in the case where a high concentration of P-type impurities are injected. As in the case of (a), a barrier is formed so that holes can be surrounded.

In order to form an insulating layer on the semiconductor substrate 100, it is common to use a silicon on insulator (SOI) substrate, but it is expensive and difficult to commercialize. In addition, another method of growing an insulating film on a silicon wafer and then depositing silicon thereon is that the performance of a semiconductor device is very degraded because the degree of crystallization of silicon deposited on the insulating layer is lower than that of the wafer itself. There are disadvantages. In contrast, the method of forming the hole encapsulation layer 110 as an ion implantation layer only needs to inject ions into the semiconductor substrate 100 using a normal semiconductor process as it is, thereby lowering the device manufacturing cost and Can improve the performance.

The floating body 120 is formed of a material constituting the body of a conventional field effect transistor. Here, the floating body 120 may be made of any one of silicon, silicon germanium, tensile silicon or tensile silicon germanium, silicon carbide. The floating body 120 is formed so that its thickness is thicker than the maximum depletion width of the channel of the nonvolatile DRAM according to the present invention. The resistance change material layer 150 refers to a layer made of any known material having a property that the resistance of the material varies depending on the applied voltage. The resistance change material layer 150 includes nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, zinc (Zn) oxide, tungsten (W) oxide, and (cobalt) Co oxide. And vanadium (V) oxide.

4 is a cross-sectional view illustrating a method of manufacturing a nonvolatile DRAM (ReSFET) according to a first embodiment of the present invention according to a manufacturing process sequence. As shown in FIG. 4A, the hole encapsulation layer 110, the floating body 120, and the resistance change material layer 150 are sequentially formed on the semiconductor substrate 100. The floating body 120 is formed so that its thickness becomes a PDiI Partially Depleted Silicon On Insulator (PD SOI) substrate that is thicker than the maximum depletion width of the channel. If the thickness of the floating body is thinner than the maximum depletion width, the entire floating body is depleted, and in that depleted region, the newly formed holes are immediately recombined and disappear, so that the floating body can become PD SOI. The thickness of the should be sufficient.

 Alternatively, an insulating layer embedded silicon (SOI) substrate in which an insulating layer as the hole enveloping layer 110 is formed in the substrate 100 may be used. The insulating layer buried silicon substrate is divided into PD SOI (Partially Depleted Silicon On Insulator) and FD SOI (Fully Depleted Silicon On Insulator) substrate. Here, too, a PD SOI substrate is used in which the thickness of the floating body 120 is thicker than the maximum depletion width of the channel. The floating body 120 may collect holes in an area adjacent to the hole enveloping layer 110 and may also be used as a channel between the source 130 and the drain 140.

Next, as shown in FIG. 3B, after the gate 160 is formed on the resistance change material layer 150, the gate 160 and the resistance change material layer 150 are etched. As shown in (c) of FIG. 3, the source body 130 and the drain 140 spaced apart by the channel length from the floating body 120 may be subjected to a diffusion or ion implantation process and subsequent heat treatment. To form.

The nonvolatile DRAM (ReSFET) according to the first embodiment of the present invention has the following characteristics. When a large voltage is applied to the gate 160 and the drain 140, excess holes are generated in the channel on the drain 140 by collision ionization. These excess holes are gathered in the floating body 120 having the lowest potential because there is no place to escape because there is a hole surrounding layer 110 below the body 120. In this way, the transistors with the collected holes have a difference in the threshold voltage and current level when there is no hole in the floating body of the previous, and the difference is divided into '0' and '1'. In this case, the resistance change material layer serves as a gate insulating film of the transistor. Therefore, the nonvolatile DRAM (ReSFET) can be used as a DRAM without a capacitor.

In addition, the nonvolatile DRAM according to the present invention has the characteristics of a nonvolatile memory device. When a voltage higher than a certain value is applied to the gate, the resistance of the resistance change material layer 150 changes, and the resistance change is maintained even when the voltage applied to the gate is removed, so that 0 and 1 can be distinguished according to the difference in resistance value. It can operate with nonvolatile memory device. Whether to operate the nonvolatile DRAM according to the present invention as a DRAM or a nonvolatile memory device may be determined according to the magnitude of the voltage applied to the gate. For example, since a gate voltage for operating with a DRAM is generally lower than a gate voltage for operating with a nonvolatile memory device, a specific voltage between the gate voltages is set as a reference voltage, and when operating with a DRAM, When the device is operated at a voltage lower than the reference voltage and the nonvolatile memory device is operated, the operation of the nonvolatile DRAM according to the present invention can be determined by operating the device at a voltage higher than the reference voltage.

Second Embodiment

5 illustrates a nonvolatile DRAM according to a second embodiment of the present invention. The nonvolatile DRAM (ReSFET) according to the second embodiment of the present invention has a hole encapsulation layer 110 such that the thickness of the floating body 120 is smaller than the maximum depletion width of the channel, compared to the nonvolatile DRAM according to the first embodiment. ) Is formed on the substrate 100, and further includes a back gate 170 under the substrate 100. As such, the structure in which the thickness of the floating body 120 is smaller than the maximum depletion width of the channel is referred to as FD SOI (Fully Depleted Silicon On Insulator). Since the FD SOI structure prevents holes from collecting at the junction of the source 130 and the floating body 120, the floating body effect does not appear and memory characteristics are not obtained. However, when the back gate 170 is formed under the substrate 100 and a negative voltage is applied to the back gate 170, the negative voltage may form a potential well to accumulate holes in the floating body 120. Can be.

Third Embodiment

6 illustrates a nonvolatile DRAM (ReSFET) according to a third embodiment of the present invention. The nonvolatile DRAM (ReSFET) according to the third embodiment of the present invention has a fin structure (or three-dimensional structure) in which the floating body 120 is not a planar structure, compared to the nonvolatile DRAM according to the first embodiment. Vertical structure) and the gate 160 surrounds the channel region in three dimensions on three surfaces. This structure can improve the channel control capability of the gate 160.

7 is a cross-sectional view illustrating a method of manufacturing a nonvolatile DRAM (ReSFET) according to a third embodiment of the present invention according to a manufacturing process sequence. As shown in FIG. 7A, the semiconductor substrate 100, the hole encapsulation layer 110, and the floating body 120 are sequentially formed. In the present specification, the semiconductor substrate 100 will be described based on being a P-type silicon substrate for convenience, but the semiconductor substrate 100 means a general material, and among the silicon substrate, silicon germanium, tensile silicon or tensile silicon germanium, and silicon carbide substrate, It can be one. In addition, the floating body 120 is formed in a three-dimensional vertical fin structure using a patterning process (patterning). The upper and side surfaces of the floating body 120 are used as channel regions. Shallow Trench Isolation (STI) 115 is formed at an outer lower end of the floating body 120 to insulate other adjacent cells.

Next, as shown in FIG. 7B, the resistance change material layer 150 is formed on the floating body 120. Next, as shown in FIG. 7C, the gate 160 is formed. In addition, although not shown in the drawings, the source and drain spaced apart by the channel length inside the floating body 120 are formed by using a diffusion or ion implantation process and subsequent heat treatment.

As described above, those skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without changing the technical spirit or essential features. Therefore, the above-described embodiments are to be understood in all respects as illustrative and not restrictive, the scope of the present invention being indicated by the following claims rather than the foregoing description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

FIG. 1A is a cross-sectional view illustrating the operation of a capacitorless DRAM, and FIG. 1B is a cross-sectional view schematically illustrating an RRAM.

2 illustrates a nonvolatile DRAM according to a first embodiment of the present invention.

3 is a diagram illustrating an energy band diagram of the floating body 120-the hole encapsulation layer 110-the substrate 100.

4 is a cross-sectional view illustrating a method of manufacturing a nonvolatile DRAM (ReSFET) according to a first embodiment of the present invention according to a manufacturing process sequence.

5 illustrates a nonvolatile DRAM according to a second embodiment of the present invention.

6 illustrates a nonvolatile DRAM (ReSFET) according to a third embodiment of the present invention.

7 is a cross-sectional view illustrating a method of manufacturing a nonvolatile DRAM (ReSFET) according to a third embodiment of the present invention according to a manufacturing process sequence.

***** Description of the symbols for the main parts of the drawings *****

100: substrate

110: hole enveloping layer 115: STI (Shallow Tranch Isloation)

120: floating body 130: source

140: drain 150: resistance change material layer

160: gate 170: back gate

Claims (16)

Semiconductor substrates; A hole envelope layer formed on the semiconductor substrate; A floating body formed on the hole enveloping layer; A resistance change material layer formed on the floating body; A gate formed on the resistance change material layer; And A nonvolatile DRAM comprising a source and a drain formed on the hole encapsulation layer spaced apart from each other with the floating body interposed therebetween The method of claim 1, And the hole enveloping layer is made of an insulator. The method of claim 1, And the hole encapsulation layer is an ion implantation layer. The method of claim 3, The ion implantation layer is a non-volatile DRAM, a layer implanted with P-type impurity ions in the semiconductor substrate. The method of claim 3, The ion implantation layer is a non-volatile DRAM, a layer in which germanium (Ge) is injected into the semiconductor substrate. The method of claim 1, And the floating body is formed so that its thickness is thicker than the maximum depletion width of the channel of the nonvolatile DRAM. The method of claim 1, And a back gate formed under the semiconductor substrate. The method of claim 7, wherein And the floating body is formed so that its thickness is thinner than the maximum depletion width of the channel of the nonvolatile DRAM. The method of claim 1, The floating body is a non-volatile DRAM, formed of a fin (Fin) structure. The method of claim 1, The resistance change material layer is nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zr) oxide, zinc (Zn) oxide, tungsten (W) oxide, (cobalt) Co oxide, vanadium (V) A nonvolatile DRAM comprising at least one substance of an oxide. Forming a hole encapsulation layer on the semiconductor substrate; Sequentially stacking a floating body and a resistance change material layer on the hole encapsulation layer; Forming a gate on the resistive change material layer; Etching the gate and the resistance change material layer; Forming a source and a drain on the floating body. The method of claim 11, The hole encapsulation layer is formed by implanting germanium (Ge) or P-type impurity ions into the semiconductor substrate. The method of claim 11, And stacking the floating body so that its thickness is thicker than the maximum depletion width of the channel of the nonvolatile DRAM. The method of claim 11, And forming a back gate under the semiconductor substrate. The method of claim 14, Stacking the floating body such that its thickness is thinner than a maximum depletion width of a channel of the nonvolatile DRAM. Sequentially stacking a floating body and a resistance change material layer on an insulating buried silicon (SOI) substrate; Forming a gate on the resistive change material layer; Etching the gate and the resistance change material layer; Forming a source and a drain on the floating body.

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